gcc/testsuite/gcc.target/riscv/shift-and-2.c

   1 /* { dg-do compile { target { riscv64*-*-* } } } */
   2 /* { dg-options "-march=rv64gc -mabi=lp64" } */
   3 /* { dg-skip-if "" { *-*-* } { "-O0" } } */
   4
   5 /* Test for <optab>si3_mask_1.  */
   6 extern int k;
   7 void
   8 sub2 (int i, long j)
   9 {
  10   k = i << (j & 0x1f);
  11 }
  12
  13 /* Test for <optab>si3_extend_mask.  */
  14 int
  15 sub3 (short mask)
  16 {
  17   return 1 << ((int)mask & 0x1f);
  18 }
  19
  20 /* Test for <optab>si3_extend_mask_1.  */
  21 int
  22 sub4 (int i, int j)
  23 {
  24   return i << (j & 0x1f);
  25 }
  26
  27 /* Test for <optab>di3_mask.  */
  28 long
  29 sub5 (long i, int j)
  30 {
  31   char k = j & 0x3f;
  32   return i << k;
  33 }
  34
  35 /* Test for <optab>di3_mask_1.  */
  36 long
  37 sub6 (long i, long j)
  38 {
  39   return i << (j & 0x3f);
  40 }
  41
  42 /* Test for <optab>si3_extend. */
  43 int
  44 sub7 (int i, int j) {
  45   return (i << 10) & j;
  46 }
  47
  48 /* Test for <optab>si3_extend. */
  49 unsigned
  50 sub8 (unsigned i, unsigned j) {
  51   return (i << 10) & j;
  52 }
  53
  54 /* Test for <optab>si3_extend. */
  55 unsigned
  56 sub9 (unsigned i, unsigned j) {
  57   return (i >> 10) & j;
  58 }
  59
  60 /* { dg-final { scan-assembler-not "andi" } } */
  61 /* { dg-final { scan-assembler-not "sext.w" } } */