gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
   3 /* { dg-skip-if "" { *-*-* } { "-O0" } } */
   4
   5 /* RV64 only*/
   6 unsigned int rol(unsigned int rs1, unsigned int rs2)
   7 {
   8     int shamt = rs2 & (32 - 1);
   9     return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (32 - 1)));
  10 }
  11 unsigned int ror(unsigned int rs1, unsigned int rs2)
  12 {
  13     int shamt = rs2 & (64 - 1);
  14     return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
  15 }
  16
  17 /* { dg-final { scan-assembler-times "rolw" 1 } } */
  18 /* { dg-final { scan-assembler-times "rorw" 1 } } */
  19 /* { dg-final { scan-assembler-not "and" } } */
  20 /* { dg-final { scan-assembler-not "sext.w" } } */