gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2024 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include <stdbool.h>
  26 #include "config/riscv/riscv-opts.h"
  27
  28 #define SWITCHABLE_TARGET 1
  29
  30 /* Target CPU builtins.  */
  31 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  32
  33 #ifdef TARGET_BIG_ENDIAN_DEFAULT
  34 #define DEFAULT_ENDIAN_SPEC    "b"
  35 #else
  36 #define DEFAULT_ENDIAN_SPEC    "l"
  37 #endif
  38
  39 /* Default target_flags if no switches are specified  */
  40
  41 #ifndef TARGET_DEFAULT
  42 #define TARGET_DEFAULT 0
  43 #endif
  44
  45 #ifndef RISCV_TUNE_STRING_DEFAULT
  46 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  47 #endif
  48
  49 extern const char *riscv_expand_arch (int argc, const char **argv);
  50 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
  51 extern const char *riscv_default_mtune (int argc, const char **argv);
  52 extern const char *riscv_multi_lib_check (int argc, const char **argv);
  53
  54 # define EXTRA_SPEC_FUNCTIONS                                           \
  55   { "riscv_expand_arch", riscv_expand_arch },                           \
  56   { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu },         \
  57   { "riscv_default_mtune", riscv_default_mtune },                       \
  58   { "riscv_multi_lib_check", riscv_multi_lib_check },
  59
  60 /* Support for a compile-time default CPU, et cetera.  The rules are:
  61    --with-arch is ignored if -march or -mcpu is specified.
  62    --with-abi is ignored if -mabi is specified.
  63    --with-tune is ignored if -mtune or -mcpu is specified.
  64    --with-isa-spec is ignored if -misa-spec is specified.
  65
  66    But using default -march/-mtune value if -mcpu don't have valid option.  */
  67 #define OPTION_DEFAULT_SPECS \
  68   {"tune", "%{!mtune=*:"                                                \
  69            "  %{!mcpu=*:-mtune=%(VALUE)}"                               \
  70            "  %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" },  \
  71   {"arch", "%{!march=*:"                                                \
  72            "  %{!mcpu=*:-march=%(VALUE)}"                               \
  73            "  %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" },  \
  74   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  75   {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
  76
  77 #ifdef IN_LIBGCC2
  78 #undef TARGET_64BIT
  79 /* Make this compile time constant for libgcc2 */
  80 #define TARGET_64BIT           (__riscv_xlen == 64)
  81 #endif /* IN_LIBGCC2 */
  82
  83 #ifdef HAVE_AS_MISA_SPEC
  84 #define ASM_MISA_SPEC "%{misa-spec=*}"
  85 #else
  86 #define ASM_MISA_SPEC ""
  87 #endif
  88
  89 /* Reference:
  90      https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing  */
  91 #define STRINGIZING(s) __STRINGIZING(s)
  92 #define __STRINGIZING(s) #s
  93
  94 #define MULTILIB_DEFAULTS \
  95   {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \
  96    "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) }
  97
  98 #undef ASM_SPEC
  99 #define ASM_SPEC "\
 100 %(subtarget_asm_debugging_spec) \
 101 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
 102 %{march=*} \
 103 %{mabi=*} \
 104 %{mno-relax} \
 105 %{mbig-endian} \
 106 %{mlittle-endian} \
 107 %(subtarget_asm_spec)" \
 108 ASM_MISA_SPEC
 109
 110 #undef DRIVER_SELF_SPECS
 111 #define DRIVER_SELF_SPECS                                       \
 112 "%{march=*:%:riscv_expand_arch(%*)} "                           \
 113 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
 114
 115 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
 116
 117 #define LOCAL_LABEL_PREFIX      "."
 118 #define USER_LABEL_PREFIX       ""
 119
 120 /* Offsets recorded in opcodes are a multiple of this alignment factor.
 121    The default for this in 64-bit mode is 8, which causes problems with
 122    SFmode register saves.  */
 123 #define DWARF_CIE_DATA_ALIGNMENT -4
 124
 125 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 126 #define DWARF_FRAME_REGNUM(REGNO)                                              \
 127   (FRM_REG_P (REGNO)    ? RISCV_DWARF_FRM                                      \
 128    : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM                                     \
 129    : VL_REG_P (REGNO)   ? RISCV_DWARF_VL                                       \
 130    : VTYPE_REG_P (REGNO)                                                       \
 131      ? RISCV_DWARF_VTYPE                                                       \
 132      : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO)                \
 133           ? REGNO                                                              \
 134           : INVALID_REGNUM))
 135
 136 /* The DWARF 2 CFA column which tracks the return address.  */
 137 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
 138 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
 139
 140 /* Describe how we implement __builtin_eh_return.  */
 141 #define EH_RETURN_DATA_REGNO(N) \
 142   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 143
 144 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
 145
 146 /* Target machine storage layout */
 147
 148 #define BITS_BIG_ENDIAN 0
 149 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 150 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
 151
 152 #define MAX_BITS_PER_WORD 64
 153
 154 /* Width of a word, in units (bytes).  */
 155 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
 156 #define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD)
 157 #ifndef IN_LIBGCC2
 158 #define MIN_UNITS_PER_WORD 4
 159 #endif
 160
 161 /* Allows SImode op in builtin overflow pattern, see internal-fn.cc.  */
 162 #undef TARGET_MIN_ARITHMETIC_PRECISION
 163 #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision
 164
 165 /* The `Q' extension is not yet supported.  */
 166 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 167 /* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */
 168 #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk)
 169
 170 /* The largest type that can be passed in floating-point registers.  */
 171 #define UNITS_PER_FP_ARG                                                \
 172   ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E                   \
 173     || riscv_abi == ABI_LP64 || riscv_abi == ABI_LP64E)                 \
 174    ? 0                                                                  \
 175    : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
 176
 177 /* Set the sizes of the core types.  */
 178 #define SHORT_TYPE_SIZE 16
 179 #define INT_TYPE_SIZE 32
 180 #define LONG_LONG_TYPE_SIZE 64
 181 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 182 #define LONG_TYPE_SIZE POINTER_SIZE
 183
 184 #define FLOAT_TYPE_SIZE 32
 185 #define DOUBLE_TYPE_SIZE 64
 186 #define LONG_DOUBLE_TYPE_SIZE 128
 187
 188 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 189 #define PARM_BOUNDARY BITS_PER_WORD
 190
 191 /* Allocation boundary (in *bits*) for the code of a function.  */
 192 #define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32)
 193
 194 /* The smallest supported stack boundary the calling convention supports.  */
 195 #define STACK_BOUNDARY \
 196   (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \
 197    ? BITS_PER_WORD \
 198    : 2 * BITS_PER_WORD)
 199
 200 /* The ABI stack alignment.  */
 201 #define ABI_STACK_BOUNDARY \
 202   (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \
 203    ? BITS_PER_WORD \
 204    : 128)
 205
 206 /* There is no point aligning anything to a rounder boundary than this.  */
 207 #define BIGGEST_ALIGNMENT 128
 208
 209 /* The user-level ISA permits unaligned accesses, but they are not required
 210    of the privileged architecture.  */
 211 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 212
 213 /* Define this if you wish to imitate the way many other C compilers
 214    handle alignment of bitfields and the structures that contain
 215    them.
 216
 217    The behavior is that the type written for a bit-field (`int',
 218    `short', or other integer type) imposes an alignment for the
 219    entire structure, as if the structure really did contain an
 220    ordinary field of that type.  In addition, the bit-field is placed
 221    within the structure so that it would fit within such a field,
 222    not crossing a boundary for it.
 223
 224    Thus, on most machines, a bit-field whose type is written as `int'
 225    would not cross a four-byte boundary, and would force four-byte
 226    alignment for the whole structure.  (The alignment used may not
 227    be four bytes; it is controlled by the other alignment
 228    parameters.)
 229
 230    If the macro is defined, its definition should be a C expression;
 231    a nonzero value for the expression enables this behavior.  */
 232
 233 #define PCC_BITFIELD_TYPE_MATTERS 1
 234
 235 /* An integer expression for the size in bits of the largest integer machine
 236    mode that should actually be used.  We allow pairs of registers.  */
 237 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 238
 239 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition.  */
 240 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN)                       \
 241   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 242     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 243         || TREE_CODE (TYPE) == UNION_TYPE                               \
 244         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 245
 246 /* If defined, a C expression to compute the alignment for a static
 247    variable.  TYPE is the data type, and ALIGN is the alignment that
 248    the object would ordinarily have.  The value of this macro is used
 249    instead of that alignment to align the object.
 250
 251    If this macro is not defined, then ALIGN is used.
 252
 253    One use of this macro is to increase alignment of medium-size
 254    data to make it all fit in fewer cache lines.  Another is to
 255    cause character arrays to be word-aligned so that `strcpy' calls
 256    that copy constants to character arrays can be done inline.  */
 257
 258 #define DATA_ALIGNMENT(TYPE, ALIGN)                                             \
 259   RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen,  \
 260                           TYPE, ALIGN)
 261
 262 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 263    character arrays to be word-aligned so that `strcpy' calls that copy
 264    constants to character arrays can be done inline, and 'strcmp' can be
 265    optimised to use word loads. */
 266 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 267   RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
 268
 269 /* Define if operations between registers always perform the operation
 270    on the full register even if a narrower mode is specified.  */
 271 #define WORD_REGISTER_OPERATIONS 1
 272
 273 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 274    moves.  All other references are zero extended.  */
 275 #define LOAD_EXTEND_OP(MODE) \
 276   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 277
 278 /* Define this macro if it is advisable to hold scalars in registers
 279    in a wider mode than that declared by the program.  In such cases,
 280    the value is constrained to be within the bounds of the declared
 281    type, but kept valid in the wider mode.  The signedness of the
 282    extension may differ from that of the type.  */
 283
 284 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 285   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 286       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 287     {                                           \
 288       if ((MODE) == SImode)                     \
 289         (UNSIGNEDP) = 0;                        \
 290       (MODE) = word_mode;                       \
 291     }
 292
 293 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 294    Extensions of pointers to word_mode must be signed.  */
 295 #define POINTERS_EXTEND_UNSIGNED false
 296
 297 /* Define if loading short immediate values into registers sign extends.  */
 298 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 299
 300 /* Standard register usage.  */
 301
 302 /* Number of hardware registers.  We have:
 303
 304    - 32 integer registers
 305    - 32 floating point registers
 306    - 2 fake registers:
 307         - ARG_POINTER_REGNUM
 308         - FRAME_POINTER_REGNUM
 309    - 1 vl register
 310    - 1 vtype register
 311    - 30 unused registers for future expansion
 312    - 32 vector registers  */
 313
 314 #define FIRST_PSEUDO_REGISTER 128
 315
 316 /* x0, sp, gp, and tp are fixed.  */
 317
 318 #define FIXED_REGISTERS                                                 \
 319 { /* General registers.  */                                             \
 320   1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 321   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 322   /* Floating-point registers.  */                                      \
 323   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 324   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 325   /* Others.  */                                                        \
 326   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 327   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 328   /* Vector registers.  */                                              \
 329   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 330   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0                        \
 331 }
 332
 333 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 334    The call RTLs themselves clobber ra.  */
 335
 336 #define CALL_USED_REGISTERS                                             \
 337 { /* General registers.  */                                             \
 338   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 339   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 340   /* Floating-point registers.  */                                      \
 341   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 342   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 343   /* Others.  */                                                        \
 344   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 345   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 346   /* Vector registers.  */                                              \
 347   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 348   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1                        \
 349 }
 350
 351 /* Select a register mode required for caller save of hard regno REGNO.
 352    Contrary to what is documented, the default is not the smallest suitable
 353    mode but the largest suitable mode for the given (REGNO, NREGS) pair and
 354    it quickly creates paradoxical subregs that can be problematic.  */
 355 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 356   ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
 357
 358 /* Internal macros to classify an ISA register's type.  */
 359
 360 #define GP_REG_FIRST 0
 361 #define GP_REG_LAST  (TARGET_RVE ? 15 : 31)
 362 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 363
 364 #define FP_REG_FIRST 32
 365 #define FP_REG_LAST  63
 366 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 367
 368 #define V_REG_FIRST 96
 369 #define V_REG_LAST  127
 370 #define V_REG_NUM   (V_REG_LAST - V_REG_FIRST + 1)
 371
 372 /* The DWARF 2 CFA column which tracks the return address from a
 373    signal handler context.  This means that to maintain backwards
 374    compatibility, no hard register can be assigned this column if it
 375    would need to be handled by the DWARF unwinder.  */
 376 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 377
 378 #define GP_REG_P(REGNO) \
 379   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 380 #define FP_REG_P(REGNO)  \
 381   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 382 #define HARDFP_REG_P(REGNO)  \
 383   ((REGNO) >= FP_REG_FIRST && (REGNO) <= FP_REG_LAST)
 384 #define V_REG_P(REGNO)  \
 385   ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM)
 386 #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM)
 387 #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM)
 388 #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM)
 389 #define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM)
 390
 391 /* True when REGNO is in SIBCALL_REGS set.  */
 392 #define SIBCALL_REG_P(REGNO)    \
 393   TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
 394
 395 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 396
 397 /* Use s0 as the frame pointer if it is so requested.  */
 398 #define HARD_FRAME_POINTER_REGNUM 8
 399 #define STACK_POINTER_REGNUM 2
 400 #define THREAD_POINTER_REGNUM 4
 401
 402 /* These two registers don't really exist: they get eliminated to either
 403    the stack or hard frame pointer.  */
 404 #define ARG_POINTER_REGNUM 64
 405 #define FRAME_POINTER_REGNUM 65
 406
 407 /* Define Dwarf for RVV.  */
 408 #define RISCV_DWARF_FRM (4096 + 0x003)
 409 #define RISCV_DWARF_VXRM (4096 + 0x00a)
 410 #define RISCV_DWARF_VL (4096 + 0xc20)
 411 #define RISCV_DWARF_VTYPE (4096 + 0xc21)
 412 #define RISCV_DWARF_VLENB (4096 + 0xc22)
 413
 414 /* Register in which static-chain is passed to a function.  */
 415 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 416
 417 /* Registers used as temporaries in prologue/epilogue code.
 418
 419    The prologue registers mustn't conflict with any
 420    incoming arguments, the static chain pointer, or the frame pointer.
 421    The epilogue temporary mustn't conflict with the return registers,
 422    the frame pointer, the EH stack adjustment, or the EH data registers. */
 423
 424 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
 425 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 426 #define RISCV_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST + 1)
 427 #define RISCV_PROLOGUE_TEMP2(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP2_REGNUM)
 428
 429 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 430 #define RISCV_CALL_ADDRESS_TEMP(MODE) \
 431   gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
 432
 433 #define RETURN_ADDR_MASK (1 << RETURN_ADDR_REGNUM)
 434 #define S0_MASK (1 << S0_REGNUM)
 435 #define S1_MASK (1 << S1_REGNUM)
 436 #define S2_MASK (1 << S2_REGNUM)
 437 #define S3_MASK (1 << S3_REGNUM)
 438 #define S4_MASK (1 << S4_REGNUM)
 439 #define S5_MASK (1 << S5_REGNUM)
 440 #define S6_MASK (1 << S6_REGNUM)
 441 #define S7_MASK (1 << S7_REGNUM)
 442 #define S8_MASK (1 << S8_REGNUM)
 443 #define S9_MASK (1 << S9_REGNUM)
 444 #define S10_MASK (1 << S10_REGNUM)
 445 #define S11_MASK (1 << S11_REGNUM)
 446
 447 #define MULTI_PUSH_GPR_MASK                                                    \
 448   (RETURN_ADDR_MASK | S0_MASK | S1_MASK | S2_MASK | S3_MASK | S4_MASK          \
 449    | S5_MASK | S6_MASK | S7_MASK | S8_MASK | S9_MASK | S10_MASK | S11_MASK)
 450 #define ZCMP_MAX_SPIMM 3
 451 #define ZCMP_SP_INC_STEP 16
 452 #define ZCMP_INVALID_S0S10_SREGS_COUNTS 11
 453 #define ZCMP_S0S11_SREGS_COUNTS 12
 454 #define ZCMP_MAX_GRP_SLOTS 13
 455
 456 #define MCOUNT_NAME "_mcount"
 457
 458 #define NO_PROFILE_COUNTERS 1
 459
 460 /* Emit rtl for profiling.  Output assembler code to FILE
 461    to call "_mcount" for profiling a function entry.  */
 462 #define PROFILE_HOOK(LABEL)                                             \
 463   {                                                                     \
 464     rtx fun, ra;                                                        \
 465     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 466     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 467     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 468   }
 469
 470 /* All the work done in PROFILE_HOOK, but still required.  */
 471 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 472
 473 /* Define this macro if it is as good or better to call a constant
 474    function address than to call an address kept in a register.  */
 475 #define NO_FUNCTION_CSE 1
 476
 477 /* Define the classes of registers for register constraints in the
 478    machine description.  Also define ranges of constants.
 479
 480    One of the classes must always be named ALL_REGS and include all hard regs.
 481    If there is more than one class, another class must be named NO_REGS
 482    and contain no registers.
 483
 484    The name GENERAL_REGS must be the name of a class (or an alias for
 485    another name such as ALL_REGS).  This is the class of registers
 486    that is allowed by "g" or "r" in a register constraint.
 487    Also, registers outside this class are allocated only when
 488    instructions express preferences for them.
 489
 490    The classes must be numbered in nondecreasing order; that is,
 491    a larger-numbered class must never be contained completely
 492    in a smaller-numbered class.
 493
 494    For any two classes, it is very desirable that there be another
 495    class that represents their union.  */
 496
 497 enum reg_class
 498 {
 499   NO_REGS,                      /* no registers in set */
 500   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 501   JALR_REGS,                    /* registers used by indirect calls */
 502   GR_REGS,                      /* integer registers */
 503   FP_REGS,                      /* floating-point registers */
 504   FRAME_REGS,                   /* arg pointer and frame pointer */
 505   VM_REGS,                      /* v0.t registers */
 506   VD_REGS,                      /* vector registers except v0.t */
 507   V_REGS,                       /* vector registers */
 508   ALL_REGS,                     /* all registers */
 509   LIM_REG_CLASSES               /* max value + 1 */
 510 };
 511
 512 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 513
 514 #define GENERAL_REGS GR_REGS
 515
 516 /* An initializer containing the names of the register classes as C
 517    string constants.  These names are used in writing some of the
 518    debugging dumps.  */
 519
 520 #define REG_CLASS_NAMES                                                 \
 521 {                                                                       \
 522   "NO_REGS",                                                            \
 523   "SIBCALL_REGS",                                                       \
 524   "JALR_REGS",                                                          \
 525   "GR_REGS",                                                            \
 526   "FP_REGS",                                                            \
 527   "FRAME_REGS",                                                         \
 528   "VM_REGS",                                                            \
 529   "VD_REGS",                                                            \
 530   "V_REGS",                                                             \
 531   "ALL_REGS"                                                            \
 532 }
 533
 534 /* An initializer containing the contents of the register classes,
 535    as integers which are bit masks.  The Nth integer specifies the
 536    contents of class N.  The way the integer MASK is interpreted is
 537    that register R is in the class if `MASK & (1 << R)' is 1.
 538
 539    When the machine has more than 32 registers, an integer does not
 540    suffice.  Then the integers are replaced by sub-initializers,
 541    braced groupings containing several integers.  Each
 542    sub-initializer must be suitable as an initializer for the type
 543    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 544
 545 #define REG_CLASS_CONTENTS                                              \
 546 {                                                                       \
 547   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* NO_REGS */           \
 548   { 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 },   /* SIBCALL_REGS */      \
 549   { 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 },   /* JALR_REGS */         \
 550   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 },   /* GR_REGS */           \
 551   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 },   /* FP_REGS */           \
 552   { 0x00000000, 0x00000000, 0x00000003, 0x00000000 },   /* FRAME_REGS */        \
 553   { 0x00000000, 0x00000000, 0x00000000, 0x00000001 },   /* V0_REGS */           \
 554   { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe },   /* VNoV0_REGS */        \
 555   { 0x00000000, 0x00000000, 0x00000000, 0xffffffff },   /* V_REGS */            \
 556   { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff }    /* ALL_REGS */          \
 557 }
 558
 559 /* A C expression whose value is a register class containing hard
 560    register REGNO.  In general there is more that one such class;
 561    choose a class which is "minimal", meaning that no smaller class
 562    also contains the register.  */
 563
 564 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 565
 566 /* A macro whose definition is the name of the class to which a
 567    valid base register must belong.  A base register is one used in
 568    an address which is the register value plus a displacement.  */
 569
 570 #define BASE_REG_CLASS GR_REGS
 571
 572 /* A macro whose definition is the name of the class to which a
 573    valid index register must belong.  An index register is one used
 574    in an address where its value is either multiplied by a scale
 575    factor or added to another register (as well as added to a
 576    displacement).  */
 577
 578 #define INDEX_REG_CLASS riscv_index_reg_class()
 579
 580 /* We generally want to put call-clobbered registers ahead of
 581    call-saved ones.  (IRA expects this.)  */
 582
 583 #define REG_ALLOC_ORDER                                                 \
 584 { \
 585   /* Call-clobbered GPRs.  */                                           \
 586   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 587   /* Call-saved GPRs.  */                                               \
 588   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 589   /* GPRs that can never be exposed to the register allocator.  */      \
 590   0, 2, 3, 4,                                                           \
 591   /* Call-clobbered FPRs.  */                                           \
 592   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 593   60, 61, 62, 63,                                                       \
 594   /* Call-saved FPRs.  */                                               \
 595   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 596   /* v1 ~ v31 vector registers.  */                                     \
 597   97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,    \
 598   111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123,      \
 599   124, 125, 126, 127,                                                   \
 600   /* The vector mask register.  */                                      \
 601   96,                                                                   \
 602   /* None of the remaining classes have defined call-saved              \
 603      registers.  */                                                     \
 604   64, 65, 66, 67                                                        \
 605 }
 606
 607 /* True if VALUE is a signed 12-bit number.  */
 608
 609 #define SMALL_OPERAND(VALUE) \
 610   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 611
 612 #define POLY_SMALL_OPERAND_P(POLY_VALUE)                \
 613   (POLY_VALUE.is_constant () ?                          \
 614      SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
 615
 616 /* True if VALUE can be loaded into a register using LUI.  */
 617
 618 #define LUI_OPERAND(VALUE)                                              \
 619   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 620    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 621
 622 /* If this is a single bit mask, then we can load it with bseti.  Special
 623    handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
 624 #define SINGLE_BIT_MASK_OPERAND(VALUE)                                  \
 625   (pow2p_hwi (TARGET_64BIT                                              \
 626                 ? (VALUE)                                               \
 627                 : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1))))
 628
 629 /* True if VALUE can be represented as an immediate with 1 extra bit
 630    set: we check that it is not a SMALL_OPERAND (as this would be true
 631    for all small operands) unmodified and turns into a small operand
 632    once we clear the top bit. */
 633 #define UIMM_EXTRA_BIT_OPERAND(VALUE)                                   \
 634   (!SMALL_OPERAND (VALUE)                                               \
 635    && SMALL_OPERAND (VALUE & ~(HOST_WIDE_INT_1U << floor_log2 (VALUE))))
 636
 637 /* True if bit BIT is set in VALUE.  */
 638 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
 639
 640 /* Stack layout; function entry, exit and calling.  */
 641
 642 #define STACK_GROWS_DOWNWARD 1
 643
 644 #define FRAME_GROWS_DOWNWARD 1
 645
 646 #define RETURN_ADDR_RTX riscv_return_addr
 647
 648 #define ELIMINABLE_REGS                                                 \
 649 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 650  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 651  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 652  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 653
 654 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 655   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 656
 657 /* Allocate stack space for arguments at the beginning of each function.  */
 658 #define ACCUMULATE_OUTGOING_ARGS 1
 659
 660 /* The argument pointer always points to the first argument.  */
 661 #define FIRST_PARM_OFFSET(FNDECL) 0
 662
 663 #define REG_PARM_STACK_SPACE(FNDECL) 0
 664
 665 /* Define this if it is the responsibility of the caller to
 666    allocate the area reserved for arguments passed in registers.
 667    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 668    of this macro is to determine whether the space is included in
 669    `crtl->outgoing_args_size'.  */
 670 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 671
 672 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
 673
 674 /* Symbolic macros for the registers used to return integer and floating
 675    point values.  */
 676
 677 #define GP_RETURN GP_ARG_FIRST
 678 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 679
 680 #define MAX_ARGS_IN_REGISTERS \
 681   (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \
 682    ? 6 \
 683    : 8)
 684
 685 #define MAX_ARGS_IN_VECTOR_REGISTERS (16)
 686 #define MAX_ARGS_IN_MASK_REGISTERS (1)
 687
 688 /* Symbolic macros for the first/last argument registers.  */
 689
 690 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 691 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 692 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 693 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 694 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 695 #define V_ARG_FIRST (V_REG_FIRST + 8)
 696 #define V_ARG_LAST (V_ARG_FIRST + MAX_ARGS_IN_VECTOR_REGISTERS - 1)
 697
 698 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 699   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 700    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 701
 702 #define CALLEE_SAVED_FREG_NUMBER(REGNO) CALLEE_SAVED_REG_NUMBER (REGNO - 32)
 703
 704 #define LIBCALL_VALUE(MODE) \
 705   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 706
 707 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 708   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 709
 710 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 711
 712 /* 1 if N is a possible register number for function argument passing.
 713    We have no FP argument registers when soft-float.  */
 714
 715 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 716 #define FUNCTION_ARG_REGNO_P(N)                                         \
 717   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 718    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 719
 720 /* Define the standard RISC-V calling convention and variants.  */
 721
 722 enum riscv_cc
 723 {
 724   RISCV_CC_BASE = 0, /* Base standard RISC-V ABI.  */
 725   RISCV_CC_V, /* For functions that pass or return values in V registers.  */
 726   RISCV_CC_UNKNOWN
 727 };
 728
 729 typedef struct {
 730   /* The calling convention that current function used.  */
 731   enum riscv_cc variant_cc;
 732
 733   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 734   unsigned int num_gprs;
 735
 736   /* Number of floating-point registers used so far, likewise.  */
 737   unsigned int num_fprs;
 738
 739   /* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS.  */
 740   unsigned int num_mrs;
 741
 742   /* The used state of args in vector registers, true for used by prev arg,
 743      initial to false.  */
 744   bool used_vrs[MAX_ARGS_IN_VECTOR_REGISTERS];
 745 } CUMULATIVE_ARGS;
 746
 747 /* Return riscv calling convention of call_insn.  */
 748 extern enum riscv_cc get_riscv_cc (const rtx use);
 749
 750 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 751    for a call to a function whose data type is FNTYPE.
 752    For a library call, FNTYPE is 0.  */
 753
 754 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 755   riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
 756                         (N_NAMED_ARGS) != -1)
 757
 758 #define EPILOGUE_USES(REGNO)    riscv_epilogue_uses (REGNO)
 759
 760 /* Align based on stack boundary, which might have been set by the user.  */
 761 #define RISCV_STACK_ALIGN(LOC) \
 762   (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
 763
 764 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 765    the stack pointer does not matter.  The value is tested only in
 766    functions that have frame pointers.
 767    No definition is equivalent to always zero.  */
 768
 769 #define EXIT_IGNORE_STACK 1
 770
 771
 772 /* Trampolines are a block of code followed by two pointers.  */
 773
 774 #define TRAMPOLINE_CODE_SIZE 16
 775 #define TRAMPOLINE_SIZE         \
 776   ((Pmode == SImode)            \
 777    ? TRAMPOLINE_CODE_SIZE       \
 778    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 779 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 780
 781 /* Addressing modes, and classification of registers for them.  */
 782
 783 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 784   riscv_regno_ok_for_index_p (REGNO)
 785
 786 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 787   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 788
 789 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 790    and check its validity for a certain class.
 791    We have two alternate definitions for each of them.
 792    The usual definition accepts all pseudo regs; the other rejects them all.
 793    The symbol REG_OK_STRICT causes the latter definition to be used.
 794
 795    Most source files want to accept pseudo regs in the hope that
 796    they will get allocated to the class that the insn wants them to be in.
 797    Some source files that are used after register allocation
 798    need to be strict.  */
 799
 800 #ifndef REG_OK_STRICT
 801 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 802   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 803 #else
 804 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 805   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 806 #endif
 807
 808 #define REG_OK_FOR_INDEX_P(X) 0
 809
 810 /* Maximum number of registers that can appear in a valid memory address.  */
 811
 812 #define MAX_REGS_PER_ADDRESS 1
 813
 814 #define CONSTANT_ADDRESS_P(X) \
 815   (CONSTANT_P (X) && memory_address_p (SImode, X))
 816
 817 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 818    'the start of the function that this code is output in'.  */
 819
 820 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 821   do {                                                                  \
 822     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 823       asm_fprintf ((FILE), "%U%s",                                      \
 824                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 825                                0), 0));                                 \
 826     else                                                                \
 827       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 828   } while (0)
 829
 830 #undef ASM_OUTPUT_OPCODE
 831 #define ASM_OUTPUT_OPCODE(STREAM, PTR)  \
 832   (PTR) = riscv_asm_output_opcode(STREAM, PTR)
 833
 834 #define JUMP_TABLES_IN_TEXT_SECTION 0
 835 #define CASE_VECTOR_MODE SImode
 836 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 837
 838 #define LOCAL_SYM_P(sym)                                                \
 839      ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))                  \
 840          || ((GET_CODE (sym) == CONST)                                  \
 841              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 842              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))
 843
 844 /* The load-address macro is used for PC-relative addressing of symbols
 845    that bind locally.  Don't use it for symbols that should be addressed
 846    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 847    currently results in more opportunities for linker relaxation.  */
 848 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 849   (!TARGET_EXPLICIT_RELOCS &&                                           \
 850    ((flag_pic && LOCAL_SYM_P (sym)) || riscv_cmodel == CM_MEDANY))
 851
 852 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 853 #define DEFAULT_SIGNED_CHAR 0
 854
 855 #define MOVE_MAX UNITS_PER_WORD
 856 #define MAX_MOVE_MAX 8
 857
 858 /* The SPARC port says:
 859    Nonzero if access to memory by bytes is slow and undesirable.
 860    For RISC chips, it means that access to memory by bytes is no
 861    better than access by words when possible, so grab a whole word
 862    and maybe make use of that.  */
 863 #define SLOW_BYTE_ACCESS 1
 864
 865 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
 866    in the md file instead.  */
 867 #define SHIFT_COUNT_TRUNCATED 0
 868
 869 /* Specify the machine mode that pointers have.
 870    After generation of rtl, the compiler makes no further distinction
 871    between pointers and any other objects of this machine mode.  */
 872
 873 #define Pmode word_mode
 874
 875 /* Specify the machine mode that registers have.  */
 876
 877 #define Xmode (TARGET_64BIT ? DImode : SImode)
 878
 879 /* Give call MEMs SImode since it is the "most permissive" mode
 880    for both 32-bit and 64-bit targets.  */
 881
 882 #define FUNCTION_MODE SImode
 883
 884 /* A C expression for the cost of a branch instruction.  A value of 2
 885    seems to minimize code size.  */
 886
 887 #define BRANCH_COST(speed_p, predictable_p) \
 888   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 889
 890 /* True if the target optimizes short forward branches around integer
 891    arithmetic instructions into predicated operations, e.g., for
 892    conditional-move operations.  The macro assumes that all branch
 893    instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
 894    support this feature.  The macro further assumes that any integer
 895    arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
 896    SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
 897    counterparts, including C.MV and C.LI) can be in the branch shadow.  */
 898
 899 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
 900
 901 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 902
 903 /* Control the assembler format that we output.  */
 904
 905 /* Output to assembler file text saying following lines
 906    may contain character constants, extra white space, comments, etc.  */
 907
 908 #ifndef ASM_APP_ON
 909 #define ASM_APP_ON " #APP\n"
 910 #endif
 911
 912 /* Output to assembler file text saying following lines
 913    no longer contain unusual constructs.  */
 914
 915 #ifndef ASM_APP_OFF
 916 #define ASM_APP_OFF " #NO_APP\n"
 917 #endif
 918
 919 #define REGISTER_NAMES                                          \
 920 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 921   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 922   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 923   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 924   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 925   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 926   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 927   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 928   "arg", "frame", "vl", "vtype", "vxrm", "frm", "N/A", "N/A",   \
 929   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 930   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 931   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 932   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",        \
 933   "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",       \
 934   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",       \
 935   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",}
 936
 937 #define ADDITIONAL_REGISTER_NAMES                                       \
 938 {                                                                       \
 939   { "x0",        0 + GP_REG_FIRST },                                    \
 940   { "x1",        1 + GP_REG_FIRST },                                    \
 941   { "x2",        2 + GP_REG_FIRST },                                    \
 942   { "x3",        3 + GP_REG_FIRST },                                    \
 943   { "x4",        4 + GP_REG_FIRST },                                    \
 944   { "x5",        5 + GP_REG_FIRST },                                    \
 945   { "x6",        6 + GP_REG_FIRST },                                    \
 946   { "x7",        7 + GP_REG_FIRST },                                    \
 947   { "x8",        8 + GP_REG_FIRST },                                    \
 948   { "x9",        9 + GP_REG_FIRST },                                    \
 949   { "x10",      10 + GP_REG_FIRST },                                    \
 950   { "x11",      11 + GP_REG_FIRST },                                    \
 951   { "x12",      12 + GP_REG_FIRST },                                    \
 952   { "x13",      13 + GP_REG_FIRST },                                    \
 953   { "x14",      14 + GP_REG_FIRST },                                    \
 954   { "x15",      15 + GP_REG_FIRST },                                    \
 955   { "x16",      16 + GP_REG_FIRST },                                    \
 956   { "x17",      17 + GP_REG_FIRST },                                    \
 957   { "x18",      18 + GP_REG_FIRST },                                    \
 958   { "x19",      19 + GP_REG_FIRST },                                    \
 959   { "x20",      20 + GP_REG_FIRST },                                    \
 960   { "x21",      21 + GP_REG_FIRST },                                    \
 961   { "x22",      22 + GP_REG_FIRST },                                    \
 962   { "x23",      23 + GP_REG_FIRST },                                    \
 963   { "x24",      24 + GP_REG_FIRST },                                    \
 964   { "x25",      25 + GP_REG_FIRST },                                    \
 965   { "x26",      26 + GP_REG_FIRST },                                    \
 966   { "x27",      27 + GP_REG_FIRST },                                    \
 967   { "x28",      28 + GP_REG_FIRST },                                    \
 968   { "x29",      29 + GP_REG_FIRST },                                    \
 969   { "x30",      30 + GP_REG_FIRST },                                    \
 970   { "x31",      31 + GP_REG_FIRST },                                    \
 971   { "f0",        0 + FP_REG_FIRST },                                    \
 972   { "f1",        1 + FP_REG_FIRST },                                    \
 973   { "f2",        2 + FP_REG_FIRST },                                    \
 974   { "f3",        3 + FP_REG_FIRST },                                    \
 975   { "f4",        4 + FP_REG_FIRST },                                    \
 976   { "f5",        5 + FP_REG_FIRST },                                    \
 977   { "f6",        6 + FP_REG_FIRST },                                    \
 978   { "f7",        7 + FP_REG_FIRST },                                    \
 979   { "f8",        8 + FP_REG_FIRST },                                    \
 980   { "f9",        9 + FP_REG_FIRST },                                    \
 981   { "f10",      10 + FP_REG_FIRST },                                    \
 982   { "f11",      11 + FP_REG_FIRST },                                    \
 983   { "f12",      12 + FP_REG_FIRST },                                    \
 984   { "f13",      13 + FP_REG_FIRST },                                    \
 985   { "f14",      14 + FP_REG_FIRST },                                    \
 986   { "f15",      15 + FP_REG_FIRST },                                    \
 987   { "f16",      16 + FP_REG_FIRST },                                    \
 988   { "f17",      17 + FP_REG_FIRST },                                    \
 989   { "f18",      18 + FP_REG_FIRST },                                    \
 990   { "f19",      19 + FP_REG_FIRST },                                    \
 991   { "f20",      20 + FP_REG_FIRST },                                    \
 992   { "f21",      21 + FP_REG_FIRST },                                    \
 993   { "f22",      22 + FP_REG_FIRST },                                    \
 994   { "f23",      23 + FP_REG_FIRST },                                    \
 995   { "f24",      24 + FP_REG_FIRST },                                    \
 996   { "f25",      25 + FP_REG_FIRST },                                    \
 997   { "f26",      26 + FP_REG_FIRST },                                    \
 998   { "f27",      27 + FP_REG_FIRST },                                    \
 999   { "f28",      28 + FP_REG_FIRST },                                    \
1000   { "f29",      29 + FP_REG_FIRST },                                    \
1001   { "f30",      30 + FP_REG_FIRST },                                    \
1002   { "f31",      31 + FP_REG_FIRST },                                    \
1003 }
1004
1005 /* Globalizing directive for a label.  */
1006 #define GLOBAL_ASM_OP "\t.globl\t"
1007
1008 /* This is how to store into the string LABEL
1009    the symbol_ref name of an internal numbered label where
1010    PREFIX is the class of label and NUM is the number within the class.
1011    This is suitable for output with `assemble_name'.  */
1012
1013 #undef ASM_GENERATE_INTERNAL_LABEL
1014 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
1015   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
1016
1017 /* This is how to output an element of a case-vector that is absolute.  */
1018
1019 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
1020   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
1021
1022 /* This is how to output an element of a PIC case-vector. */
1023
1024 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
1025   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
1026            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
1027
1028 /* This is how to output an assembler line
1029    that says to advance the location counter
1030    to a multiple of 2**LOG bytes.  */
1031
1032 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
1033   fprintf (STREAM, "\t.align\t%d\n", (LOG))
1034
1035 /* Define the strings to put out for each section in the object file.  */
1036 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
1037 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
1038 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
1039 #define BSS_SECTION_ASM_OP      "\t.bss"
1040 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
1041 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
1042
1043 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
1044 do                                                                      \
1045   {                                                                     \
1046     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
1047              reg_names[STACK_POINTER_REGNUM],                           \
1048              reg_names[STACK_POINTER_REGNUM],                           \
1049              TARGET_64BIT ? "sd" : "sw",                                \
1050              reg_names[REGNO],                                          \
1051              reg_names[STACK_POINTER_REGNUM]);                          \
1052   }                                                                     \
1053 while (0)
1054
1055 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
1056 do                                                                      \
1057   {                                                                     \
1058     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
1059              TARGET_64BIT ? "ld" : "lw",                                \
1060              reg_names[REGNO],                                          \
1061              reg_names[STACK_POINTER_REGNUM],                           \
1062              reg_names[STACK_POINTER_REGNUM],                           \
1063              reg_names[STACK_POINTER_REGNUM]);                          \
1064   }                                                                     \
1065 while (0)
1066
1067 #define ASM_COMMENT_START "#"
1068
1069 /* Add output .variant_cc directive for specific function definition.  */
1070 #undef ASM_DECLARE_FUNCTION_NAME
1071 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)                             \
1072   riscv_declare_function_name (STR, NAME, DECL)
1073
1074 #undef ASM_DECLARE_FUNCTION_SIZE
1075 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)                           \
1076   riscv_declare_function_size (FILE, FNAME, DECL)
1077
1078 /* Add output .variant_cc directive for specific alias definition.  */
1079 #undef ASM_OUTPUT_DEF_FROM_DECLS
1080 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET)                           \
1081   riscv_asm_output_alias (STR, DECL, TARGET)
1082
1083 /* Add output .variant_cc directive for specific extern function.  */
1084 #undef ASM_OUTPUT_EXTERNAL
1085 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME)                                   \
1086   riscv_asm_output_external (STR, DECL, NAME)
1087
1088 #undef SIZE_TYPE
1089 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
1090
1091 #undef PTRDIFF_TYPE
1092 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
1093
1094 /* The maximum number of bytes copied by one iteration of a cpymemsi loop.  */
1095
1096 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
1097
1098 /* The maximum number of bytes that can be copied by a straight-line
1099    cpymemsi implementation.  */
1100
1101 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
1102
1103 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1104    move-instruction pairs, we will do a cpymem or libcall instead.
1105    Do not use move_by_pieces at all when strict alignment is not
1106    in effect but the target has slow unaligned accesses; in this
1107    case, cpymem or libcall is more efficient.  */
1108
1109 #define MOVE_RATIO(speed)                                               \
1110   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
1111    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
1112    CLEAR_RATIO (speed) / 2)
1113
1114 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
1115    of the length of a memset call, but use the default otherwise.  */
1116
1117 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
1118
1119 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
1120    optimizing for size adjust the ratio to account for the overhead of
1121    loading the constant and replicating it across the word.  */
1122
1123 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
1124
1125 #ifndef USED_FOR_TARGET
1126 extern const enum reg_class riscv_regno_to_class[];
1127 extern bool riscv_slow_unaligned_access_p;
1128 extern bool riscv_user_wants_strict_align;
1129 extern unsigned riscv_stack_boundary;
1130 extern unsigned riscv_bytes_per_vector_chunk;
1131 extern poly_uint16 riscv_vector_chunks;
1132 extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int);
1133 extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int);
1134 extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
1135 extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
1136 /* The number of bits and bytes in a RVV vector.  */
1137 #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8))
1138 #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))
1139 #endif
1140
1141 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1142   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
1143
1144 #define XLEN_SPEC \
1145   "%{march=rv32*:32}" \
1146   "%{march=rv64*:64}" \
1147
1148 #define ABI_SPEC \
1149   "%{mabi=ilp32:ilp32}" \
1150   "%{mabi=ilp32e:ilp32e}" \
1151   "%{mabi=ilp32f:ilp32f}" \
1152   "%{mabi=ilp32d:ilp32d}" \
1153   "%{mabi=lp64:lp64}" \
1154   "%{mabi=lp64e:lp64e}" \
1155   "%{mabi=lp64f:lp64f}" \
1156   "%{mabi=lp64d:lp64d}" \
1157
1158 /* ISA constants needed for code generation.  */
1159 #define OPCODE_LW    0x2003
1160 #define OPCODE_LD    0x3003
1161 #define OPCODE_AUIPC 0x17
1162 #define OPCODE_JALR  0x67
1163 #define OPCODE_LUI   0x37
1164 #define OPCODE_ADDI  0x13
1165 #define SHIFT_RD  7
1166 #define SHIFT_RS1 15
1167 #define SHIFT_IMM 20
1168 #define IMM_BITS 12
1169 #define C_S_BITS 5
1170 #define C_SxSP_BITS 6
1171
1172 #define IMM_REACH (1LL << IMM_BITS)
1173 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
1174 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
1175
1176 #define SWSP_REACH (4LL << C_SxSP_BITS)
1177 #define SDSP_REACH (8LL << C_SxSP_BITS)
1178
1179 /* This is the maximum value that can be represented in a compressed load/store
1180    offset (an unsigned 5-bit value scaled by 4).  */
1181 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)
1182
1183 /* Called from RISCV_REORG, this is defined in riscv-sr.cc.  */
1184
1185 extern void riscv_remove_unneeded_save_restore_calls (void);
1186
1187 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
1188
1189 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1190   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1191 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1192   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1193
1194 #define TARGET_SUPPORTS_WIDE_INT 1
1195
1196 #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas ()
1197
1198 #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE)
1199
1200 #define RISCV_DWARF_VLENB (4096 + 0xc22)
1201
1202 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */)
1203
1204 #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \
1205   ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO)
1206
1207 /* Like s390, riscv also defined this macro for the vector comparision.  Then
1208    the simplify-rtx relational_result will canonicalize the result to the
1209    CONST1_RTX for the simplification.  */
1210 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE))
1211
1212 /* Mode switching (Lazy code motion) for RVV rounding mode instructions.  */
1213 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
1214 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
1215
1216 /* The size difference between different RVV modes can be up to 64 times.
1217    e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64].  */
1218 #define MAX_POLY_VARIANT 64
1219
1220 #define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX
1221 #define HAVE_PRE_MODIFY_DISP  TARGET_XTHEADMEMIDX
1222
1223 #endif /* ! GCC_RISCV_H */