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testsuite: Fix optimize_one.c FAIL on i686-linux
[official-gcc.git] / gcc / config / riscv / riscv.h
blobead97867eb8e304a25a973095935312e48af30a2
1 /* Definition of RISC-V target for GNU compiler.
2 Copyright (C) 2011-2024 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_RISCV_H
23 #define GCC_RISCV_H
24
25 #include <stdbool.h>
26 #include "config/riscv/riscv-opts.h"
27
28 #define SWITCHABLE_TARGET 1
29
30 /* Target CPU builtins. */
31 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
32
33 #ifdef TARGET_BIG_ENDIAN_DEFAULT
34 #define DEFAULT_ENDIAN_SPEC "b"
35 #else
36 #define DEFAULT_ENDIAN_SPEC "l"
37 #endif
38
39 /* Default target_flags if no switches are specified */
40
41 #ifndef TARGET_DEFAULT
42 #define TARGET_DEFAULT 0
43 #endif
44
45 #ifndef RISCV_TUNE_STRING_DEFAULT
46 #define RISCV_TUNE_STRING_DEFAULT "rocket"
47 #endif
48
49 extern const char *riscv_expand_arch (int argc, const char **argv);
50 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
51 extern const char *riscv_default_mtune (int argc, const char **argv);
52 extern const char *riscv_multi_lib_check (int argc, const char **argv);
53 extern const char *riscv_arch_help (int argc, const char **argv);
54
55 # define EXTRA_SPEC_FUNCTIONS \
56 { "riscv_expand_arch", riscv_expand_arch }, \
57 { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \
58 { "riscv_default_mtune", riscv_default_mtune }, \
59 { "riscv_multi_lib_check", riscv_multi_lib_check }, \
60 { "riscv_arch_help", riscv_arch_help },
61
62 /* Support for a compile-time default CPU, et cetera. The rules are:
63 --with-arch is ignored if -march or -mcpu is specified.
64 --with-abi is ignored if -mabi is specified.
65 --with-tune is ignored if -mtune or -mcpu is specified.
66 --with-isa-spec is ignored if -misa-spec is specified.
67 --with-tls is ignored if -mtls-dialect is specified.
68
69 But using default -march/-mtune value if -mcpu don't have valid option. */
70 #define OPTION_DEFAULT_SPECS \
71 {"tune", "%{!mtune=*:" \
72 " %{!mcpu=*:-mtune=%(VALUE)}" \
73 " %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" }, \
74 {"arch", "%{!march=*:" \
75 " %{!mcpu=*:-march=%(VALUE)}" \
76 " %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \
77 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
78 {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
79 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, \
80
81 #ifdef IN_LIBGCC2
82 #undef TARGET_64BIT
83 /* Make this compile time constant for libgcc2 */
84 #define TARGET_64BIT (__riscv_xlen == 64)
85 #endif /* IN_LIBGCC2 */
86
87 #ifdef HAVE_AS_MISA_SPEC
88 #define ASM_MISA_SPEC "%{misa-spec=*}"
89 #else
90 #define ASM_MISA_SPEC ""
91 #endif
92
93 /* Reference:
94 https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing */
95 #define STRINGIZING(s) __STRINGIZING(s)
96 #define __STRINGIZING(s) #s
97
98 #define MULTILIB_DEFAULTS \
99 {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \
100 "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) }
101
102 #undef ASM_SPEC
103 #define ASM_SPEC "\
104 %(subtarget_asm_debugging_spec) \
105 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
106 %{march=*} \
107 %{mabi=*} \
108 %{mno-relax} \
109 %{mbig-endian} \
110 %{mlittle-endian} \
111 %(subtarget_asm_spec)" \
112 ASM_MISA_SPEC
113
114 #undef DRIVER_SELF_SPECS
115 #define DRIVER_SELF_SPECS \
116 "%{march=help:%:riscv_arch_help()} " \
117 "%{print-supported-extensions:%:riscv_arch_help()} " \
118 "%{-print-supported-extensions:%:riscv_arch_help()} " \
119 "%{march=*:%:riscv_expand_arch(%*)} " \
120 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
121
122 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
123
124 #define LOCAL_LABEL_PREFIX "."
125 #define USER_LABEL_PREFIX ""
126
127 /* Offsets recorded in opcodes are a multiple of this alignment factor.
128 The default for this in 64-bit mode is 8, which causes problems with
129 SFmode register saves. */
130 #define DWARF_CIE_DATA_ALIGNMENT -4
131
132 /* The mapping from gcc register number to DWARF 2 CFA column number. */
133 #define DWARF_FRAME_REGNUM(REGNO) \
134 (FRM_REG_P (REGNO) ? RISCV_DWARF_FRM \
135 : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM \
136 : VL_REG_P (REGNO) ? RISCV_DWARF_VL \
137 : VTYPE_REG_P (REGNO) \
138 ? RISCV_DWARF_VTYPE \
139 : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) \
140 ? REGNO \
141 : INVALID_REGNUM))
142
143 /* The DWARF 2 CFA column which tracks the return address. */
144 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
145 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
146
147 /* Describe how we implement __builtin_eh_return. */
148 #define EH_RETURN_DATA_REGNO(N) \
149 ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
150
151 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
152
153 /* Target machine storage layout */
154
155 #define BITS_BIG_ENDIAN 0
156 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
157 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
158
159 #define MAX_BITS_PER_WORD 64
160
161 /* Width of a word, in units (bytes). */
162 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
163 #define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD)
164 #ifndef IN_LIBGCC2
165 #define MIN_UNITS_PER_WORD 4
166 #endif
167
168 /* Allows SImode op in builtin overflow pattern, see internal-fn.cc. */
169 #undef TARGET_MIN_ARITHMETIC_PRECISION
170 #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision
171
172 /* The `Q' extension is not yet supported. */
173 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
174 /* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */
175 #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk)
176
177 /* The largest type that can be passed in floating-point registers. */
178 #define UNITS_PER_FP_ARG \
179 ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \
180 || riscv_abi == ABI_LP64 || riscv_abi == ABI_LP64E) \
181 ? 0 \
182 : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
183
184 /* Set the sizes of the core types. */
185 #define SHORT_TYPE_SIZE 16
186 #define INT_TYPE_SIZE 32
187 #define LONG_LONG_TYPE_SIZE 64
188 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
189 #define LONG_TYPE_SIZE POINTER_SIZE
190
191 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
192 #define PARM_BOUNDARY BITS_PER_WORD
193
194 /* Allocation boundary (in *bits*) for the code of a function. */
195 #define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32)
196
197 /* The smallest supported stack boundary the calling convention supports. */
198 #define STACK_BOUNDARY \
199 (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \
200 ? BITS_PER_WORD \
201 : 2 * BITS_PER_WORD)
202
203 /* The ABI stack alignment. */
204 #define ABI_STACK_BOUNDARY \
205 (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \
206 ? BITS_PER_WORD \
207 : 128)
208
209 /* There is no point aligning anything to a rounder boundary than this. */
210 #define BIGGEST_ALIGNMENT 128
211
212 /* The user-level ISA permits unaligned accesses, but they are not required
213 of the privileged architecture. */
214 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
215
216 /* Define this if you wish to imitate the way many other C compilers
217 handle alignment of bitfields and the structures that contain
218 them.
219
220 The behavior is that the type written for a bit-field (`int',
221 `short', or other integer type) imposes an alignment for the
222 entire structure, as if the structure really did contain an
223 ordinary field of that type. In addition, the bit-field is placed
224 within the structure so that it would fit within such a field,
225 not crossing a boundary for it.
226
227 Thus, on most machines, a bit-field whose type is written as `int'
228 would not cross a four-byte boundary, and would force four-byte
229 alignment for the whole structure. (The alignment used may not
230 be four bytes; it is controlled by the other alignment
231 parameters.)
232
233 If the macro is defined, its definition should be a C expression;
234 a nonzero value for the expression enables this behavior. */
235
236 #define PCC_BITFIELD_TYPE_MATTERS 1
237
238 /* An integer expression for the size in bits of the largest integer machine
239 mode that should actually be used. We allow pairs of registers. */
240 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
241
242 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */
243 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \
244 (((COND) && ((ALIGN) < BITS_PER_WORD) \
245 && (TREE_CODE (TYPE) == ARRAY_TYPE \
246 || TREE_CODE (TYPE) == UNION_TYPE \
247 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
248
249 /* If defined, a C expression to compute the alignment for a static
250 variable. TYPE is the data type, and ALIGN is the alignment that
251 the object would ordinarily have. The value of this macro is used
252 instead of that alignment to align the object.
253
254 If this macro is not defined, then ALIGN is used.
255
256 One use of this macro is to increase alignment of medium-size
257 data to make it all fit in fewer cache lines. Another is to
258 cause character arrays to be word-aligned so that `strcpy' calls
259 that copy constants to character arrays can be done inline. */
260
261 #define DATA_ALIGNMENT(TYPE, ALIGN) \
262 RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \
263 TYPE, ALIGN)
264
265 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
266 character arrays to be word-aligned so that `strcpy' calls that copy
267 constants to character arrays can be done inline, and 'strcmp' can be
268 optimised to use word loads. */
269 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
270 RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
271
272 /* Define if operations between registers always perform the operation
273 on the full register even if a narrower mode is specified. */
274 #define WORD_REGISTER_OPERATIONS 1
275
276 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
277 moves. All other references are zero extended. */
278 #define LOAD_EXTEND_OP(MODE) \
279 (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
280
281 /* Define this macro if it is advisable to hold scalars in registers
282 in a wider mode than that declared by the program. In such cases,
283 the value is constrained to be within the bounds of the declared
284 type, but kept valid in the wider mode. The signedness of the
285 extension may differ from that of the type. */
286
287 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
288 if (GET_MODE_CLASS (MODE) == MODE_INT \
289 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
290 { \
291 if ((MODE) == SImode) \
292 (UNSIGNEDP) = 0; \
293 (MODE) = word_mode; \
294 }
295
296 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
297 Extensions of pointers to word_mode must be signed. */
298 #define POINTERS_EXTEND_UNSIGNED false
299
300 /* Define if loading short immediate values into registers sign extends. */
301 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
302
303 /* Standard register usage. */
304
305 /* Number of hardware registers. We have:
306
307 - 32 integer registers
308 - 32 floating point registers
309 - 2 fake registers:
310 - ARG_POINTER_REGNUM
311 - FRAME_POINTER_REGNUM
312 - 1 vl register
313 - 1 vtype register
314 - 28 unused registers for future expansion
315 - 32 vector registers */
316
317 #define FIRST_PSEUDO_REGISTER 128
318
319 /* x0, sp, gp, and tp are fixed. */
320
321 #define FIXED_REGISTERS \
322 { /* General registers. */ \
323 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
324 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
325 /* Floating-point registers. */ \
326 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
327 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
328 /* Others. */ \
329 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
330 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
331 /* Vector registers. */ \
332 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
333 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
334 }
335
336 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
337 The call RTLs themselves clobber ra. */
338
339 #define CALL_USED_REGISTERS \
340 { /* General registers. */ \
341 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
342 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
343 /* Floating-point registers. */ \
344 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
345 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
346 /* Others. */ \
347 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
348 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
349 /* Vector registers. */ \
350 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
351 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
352 }
353
354 /* Select a register mode required for caller save of hard regno REGNO.
355 Contrary to what is documented, the default is not the smallest suitable
356 mode but the largest suitable mode for the given (REGNO, NREGS) pair and
357 it quickly creates paradoxical subregs that can be problematic. */
358 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
359 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
360
361 /* Internal macros to classify an ISA register's type. */
362
363 #define GP_REG_FIRST 0
364 #define GP_REG_LAST (TARGET_RVE ? 15 : 31)
365 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
366
367 #define FP_REG_FIRST 32
368 #define FP_REG_LAST 63
369 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
370
371 #define V_REG_FIRST 96
372 #define V_REG_LAST 127
373 #define V_REG_NUM (V_REG_LAST - V_REG_FIRST + 1)
374
375 /* The DWARF 2 CFA column which tracks the return address from a
376 signal handler context. This means that to maintain backwards
377 compatibility, no hard register can be assigned this column if it
378 would need to be handled by the DWARF unwinder. */
379 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
380
381 #define GP_REG_P(REGNO) \
382 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
383 #define FP_REG_P(REGNO) \
384 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
385 #define HARDFP_REG_P(REGNO) \
386 ((REGNO) >= FP_REG_FIRST && (REGNO) <= FP_REG_LAST)
387 #define V_REG_P(REGNO) \
388 ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM)
389 #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM)
390 #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM)
391 #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM)
392 #define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM)
393
394 /* True when REGNO is in SIBCALL_REGS set. */
395 #define SIBCALL_REG_P(REGNO) \
396 TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
397
398 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
399
400 /* Use s0 as the frame pointer if it is so requested. */
401 #define HARD_FRAME_POINTER_REGNUM 8
402 #define STACK_POINTER_REGNUM 2
403 #define THREAD_POINTER_REGNUM 4
404
405 /* These two registers don't really exist: they get eliminated to either
406 the stack or hard frame pointer. */
407 #define ARG_POINTER_REGNUM 64
408 #define FRAME_POINTER_REGNUM 65
409
410 /* Define Dwarf for RVV. */
411 #define RISCV_DWARF_FRM (4096 + 0x003)
412 #define RISCV_DWARF_VXRM (4096 + 0x00a)
413 #define RISCV_DWARF_VL (4096 + 0xc20)
414 #define RISCV_DWARF_VTYPE (4096 + 0xc21)
415 #define RISCV_DWARF_VLENB (4096 + 0xc22)
416
417 /* Register in which static-chain is passed to a function. */
418 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
419
420 /* Registers used as temporaries in prologue/epilogue code.
421
422 The prologue registers mustn't conflict with any
423 incoming arguments, the static chain pointer, or the frame pointer.
424 The epilogue temporary mustn't conflict with the return registers,
425 the frame pointer, the EH stack adjustment, or the EH data registers. */
426
427 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
428 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
429 #define RISCV_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST + 1)
430 #define RISCV_PROLOGUE_TEMP2(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP2_REGNUM)
431
432 /* Both prologue temp registers are used in the vector probe loop for when
433 stack-clash protection is enabled, so we need to copy SP to a new register
434 and set it as CFA during the loop, we are using T3 for that. */
435 #define RISCV_STACK_CLASH_VECTOR_CFA_REGNUM (GP_TEMP_FIRST + 23)
436
437 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
438 #define RISCV_CALL_ADDRESS_TEMP(MODE) \
439 gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
440
441 #define RETURN_ADDR_MASK (1 << RETURN_ADDR_REGNUM)
442 #define S0_MASK (1 << S0_REGNUM)
443 #define S1_MASK (1 << S1_REGNUM)
444 #define S2_MASK (1 << S2_REGNUM)
445 #define S3_MASK (1 << S3_REGNUM)
446 #define S4_MASK (1 << S4_REGNUM)
447 #define S5_MASK (1 << S5_REGNUM)
448 #define S6_MASK (1 << S6_REGNUM)
449 #define S7_MASK (1 << S7_REGNUM)
450 #define S8_MASK (1 << S8_REGNUM)
451 #define S9_MASK (1 << S9_REGNUM)
452 #define S10_MASK (1 << S10_REGNUM)
453 #define S11_MASK (1 << S11_REGNUM)
454
455 #define MULTI_PUSH_GPR_MASK \
456 (RETURN_ADDR_MASK | S0_MASK | S1_MASK | S2_MASK | S3_MASK | S4_MASK \
457 | S5_MASK | S6_MASK | S7_MASK | S8_MASK | S9_MASK | S10_MASK | S11_MASK)
458 #define ZCMP_MAX_SPIMM 3
459 #define ZCMP_SP_INC_STEP 16
460 #define ZCMP_INVALID_S0S10_SREGS_COUNTS 11
461 #define ZCMP_S0S11_SREGS_COUNTS 12
462 #define ZCMP_MAX_GRP_SLOTS 13
463
464 #define MCOUNT_NAME "_mcount"
465
466 #define NO_PROFILE_COUNTERS 1
467
468 /* Emit rtl for profiling. Output assembler code to FILE
469 to call "_mcount" for profiling a function entry. */
470 #define PROFILE_HOOK(LABEL) \
471 { \
472 rtx fun, ra; \
473 ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \
474 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
475 emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \
476 }
477
478 /* All the work done in PROFILE_HOOK, but still required. */
479 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
480
481 /* Define this macro if it is as good or better to call a constant
482 function address than to call an address kept in a register. */
483 #define NO_FUNCTION_CSE 1
484
485 /* Define the classes of registers for register constraints in the
486 machine description. Also define ranges of constants.
487
488 One of the classes must always be named ALL_REGS and include all hard regs.
489 If there is more than one class, another class must be named NO_REGS
490 and contain no registers.
491
492 The name GENERAL_REGS must be the name of a class (or an alias for
493 another name such as ALL_REGS). This is the class of registers
494 that is allowed by "g" or "r" in a register constraint.
495 Also, registers outside this class are allocated only when
496 instructions express preferences for them.
497
498 The classes must be numbered in nondecreasing order; that is,
499 a larger-numbered class must never be contained completely
500 in a smaller-numbered class.
501
502 For any two classes, it is very desirable that there be another
503 class that represents their union. */
504
505 enum reg_class
506 {
507 NO_REGS, /* no registers in set */
508 SIBCALL_REGS, /* registers used by indirect sibcalls */
509 JALR_REGS, /* registers used by indirect calls */
510 GR_REGS, /* integer registers */
511 FP_REGS, /* floating-point registers */
512 FRAME_REGS, /* arg pointer and frame pointer */
513 VM_REGS, /* v0.t registers */
514 VD_REGS, /* vector registers except v0.t */
515 V_REGS, /* vector registers */
516 ALL_REGS, /* all registers */
517 LIM_REG_CLASSES /* max value + 1 */
518 };
519
520 #define N_REG_CLASSES (int) LIM_REG_CLASSES
521
522 #define GENERAL_REGS GR_REGS
523
524 /* An initializer containing the names of the register classes as C
525 string constants. These names are used in writing some of the
526 debugging dumps. */
527
528 #define REG_CLASS_NAMES \
529 { \
530 "NO_REGS", \
531 "SIBCALL_REGS", \
532 "JALR_REGS", \
533 "GR_REGS", \
534 "FP_REGS", \
535 "FRAME_REGS", \
536 "VM_REGS", \
537 "VD_REGS", \
538 "V_REGS", \
539 "ALL_REGS" \
540 }
541
542 /* An initializer containing the contents of the register classes,
543 as integers which are bit masks. The Nth integer specifies the
544 contents of class N. The way the integer MASK is interpreted is
545 that register R is in the class if `MASK & (1 << R)' is 1.
546
547 When the machine has more than 32 registers, an integer does not
548 suffice. Then the integers are replaced by sub-initializers,
549 braced groupings containing several integers. Each
550 sub-initializer must be suitable as an initializer for the type
551 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
552
553 #define REG_CLASS_CONTENTS \
554 { \
555 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
556 { 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
557 { 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 }, /* JALR_REGS */ \
558 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
559 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \
560 { 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \
561 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \
562 { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \
563 { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \
564 { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff } /* ALL_REGS */ \
565 }
566
567 /* A C expression whose value is a register class containing hard
568 register REGNO. In general there is more that one such class;
569 choose a class which is "minimal", meaning that no smaller class
570 also contains the register. */
571
572 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
573
574 /* A macro whose definition is the name of the class to which a
575 valid base register must belong. A base register is one used in
576 an address which is the register value plus a displacement. */
577
578 #define BASE_REG_CLASS GR_REGS
579
580 /* A macro whose definition is the name of the class to which a
581 valid index register must belong. An index register is one used
582 in an address where its value is either multiplied by a scale
583 factor or added to another register (as well as added to a
584 displacement). */
585
586 #define INDEX_REG_CLASS riscv_index_reg_class()
587
588 /* We generally want to put call-clobbered registers ahead of
589 call-saved ones. (IRA expects this.) */
590
591 #define REG_ALLOC_ORDER \
592 { \
593 /* Call-clobbered GPRs. */ \
594 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \
595 /* Call-saved GPRs. */ \
596 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
597 /* GPRs that can never be exposed to the register allocator. */ \
598 0, 2, 3, 4, \
599 /* Call-clobbered FPRs. */ \
600 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \
601 60, 61, 62, 63, \
602 /* Call-saved FPRs. */ \
603 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
604 /* v1 ~ v31 vector registers. */ \
605 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, \
606 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \
607 124, 125, 126, 127, \
608 /* The vector mask register. */ \
609 96, \
610 /* None of the remaining classes have defined call-saved \
611 registers. */ \
612 64, 65, 66, 67 \
613 }
614
615 /* True if VALUE is a signed 12-bit number. */
616
617 #define SMALL_OPERAND(VALUE) \
618 ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
619
620 #define POLY_SMALL_OPERAND_P(POLY_VALUE) \
621 (POLY_VALUE.is_constant () ? \
622 SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
623
624 /* True if VALUE can be loaded into a register using LUI. */
625
626 #define LUI_OPERAND(VALUE) \
627 (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \
628 || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
629
630 /* True if a VALUE (constant) can be expressed as sum of two S12 constants
631 (in range -2048 to 2047).
632 Range check logic:
633 from: min S12 + 1 (or -1 depending on what side of zero)
634 to: two times the min S12 value (to max out S12 bits). */
635
636 #define SUM_OF_TWO_S12_N(VALUE) \
637 (((VALUE) >= (-2048 * 2)) && ((VALUE) <= (-2048 - 1)))
638
639 #define SUM_OF_TWO_S12_P(VALUE) \
640 (((VALUE) >= (2047 + 1)) && ((VALUE) <= (2047 * 2)))
641
642 #define SUM_OF_TWO_S12(VALUE) \
643 (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P (VALUE))
644
645 /* Variant with first value 8 byte aligned if involving stack regs. */
646 #define SUM_OF_TWO_S12_P_ALGN(VALUE) \
647 (((VALUE) >= (2032 + 1)) && ((VALUE) <= (2032 * 2)))
648
649 #define SUM_OF_TWO_S12_ALGN(VALUE) \
650 (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P_ALGN (VALUE))
651
652 /* If this is a single bit mask, then we can load it with bseti. Special
653 handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
654 #define SINGLE_BIT_MASK_OPERAND(VALUE) \
655 (pow2p_hwi (TARGET_64BIT \
656 ? (VALUE) \
657 : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1))))
658
659 /* True if VALUE can be represented as an immediate with 1 extra bit
660 set: we check that it is not a SMALL_OPERAND (as this would be true
661 for all small operands) unmodified and turns into a small operand
662 once we clear the top bit. */
663 #define UIMM_EXTRA_BIT_OPERAND(VALUE) \
664 (!SMALL_OPERAND (VALUE) \
665 && SMALL_OPERAND (VALUE & ~(HOST_WIDE_INT_1U << floor_log2 (VALUE))))
666
667 /* True if bit BIT is set in VALUE. */
668 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
669
670 /* Stack layout; function entry, exit and calling. */
671
672 #define STACK_GROWS_DOWNWARD 1
673
674 #define FRAME_GROWS_DOWNWARD 1
675
676 #define RETURN_ADDR_RTX riscv_return_addr
677
678 #define ELIMINABLE_REGS \
679 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
680 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
681 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
682 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
683
684 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
685 (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
686
687 /* Allocate stack space for arguments at the beginning of each function. */
688 #define ACCUMULATE_OUTGOING_ARGS 1
689
690 /* The argument pointer always points to the first argument. */
691 #define FIRST_PARM_OFFSET(FNDECL) 0
692
693 #define REG_PARM_STACK_SPACE(FNDECL) 0
694
695 /* Define this if it is the responsibility of the caller to
696 allocate the area reserved for arguments passed in registers.
697 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
698 of this macro is to determine whether the space is included in
699 `crtl->outgoing_args_size'. */
700 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
701
702 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
703
704 /* Symbolic macros for the registers used to return integer and floating
705 point values. */
706
707 #define GP_RETURN GP_ARG_FIRST
708 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
709 #define V_RETURN V_REG_FIRST
710
711 #define GP_RETURN_FIRST GP_ARG_FIRST
712 #define GP_RETURN_LAST GP_ARG_FIRST + 1
713 #define FP_RETURN_FIRST FP_RETURN
714 #define FP_RETURN_LAST FP_RETURN + 1
715
716 #define MAX_ARGS_IN_REGISTERS \
717 (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \
718 ? 6 \
719 : 8)
720
721 #define MAX_ARGS_IN_VECTOR_REGISTERS (16)
722 #define MAX_ARGS_IN_MASK_REGISTERS (1)
723
724 /* Symbolic macros for the first/last argument registers. */
725
726 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
727 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
728 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
729 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
730 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
731 #define V_ARG_FIRST (V_REG_FIRST + 8)
732 #define V_ARG_LAST (V_ARG_FIRST + MAX_ARGS_IN_VECTOR_REGISTERS - 1)
733
734 #define CALLEE_SAVED_REG_NUMBER(REGNO) \
735 ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \
736 (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
737
738 #define CALLEE_SAVED_FREG_NUMBER(REGNO) CALLEE_SAVED_REG_NUMBER (REGNO - 32)
739
740 #define LIBCALL_VALUE(MODE) \
741 riscv_function_value (NULL_TREE, NULL_TREE, MODE)
742
743 #define FUNCTION_VALUE(VALTYPE, FUNC) \
744 riscv_function_value (VALTYPE, FUNC, VOIDmode)
745
746 /* 1 if N is a possible register number for function argument passing.
747 We have no FP argument registers when soft-float. */
748
749 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */
750 #define FUNCTION_ARG_REGNO_P(N) \
751 (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \
752 || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
753
754 /* Define the standard RISC-V calling convention and variants. */
755
756 enum riscv_cc
757 {
758 RISCV_CC_BASE = 0, /* Base standard RISC-V ABI. */
759 RISCV_CC_V, /* For functions that pass or return values in V registers. */
760 RISCV_CC_UNKNOWN
761 };
762
763 typedef struct {
764 /* The calling convention that current function used. */
765 enum riscv_cc variant_cc;
766
767 /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
768 unsigned int num_gprs;
769
770 /* Number of floating-point registers used so far, likewise. */
771 unsigned int num_fprs;
772
773 /* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */
774 unsigned int num_mrs;
775
776 /* The used state of args in vector registers, true for used by prev arg,
777 initial to false. */
778 bool used_vrs[MAX_ARGS_IN_VECTOR_REGISTERS];
779 } CUMULATIVE_ARGS;
780
781 /* Return riscv calling convention of call_insn. */
782 extern enum riscv_cc get_riscv_cc (const rtx use);
783
784 /* Initialize a variable CUM of type CUMULATIVE_ARGS
785 for a call to a function whose data type is FNTYPE.
786 For a library call, FNTYPE is 0. */
787
788 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
789 riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \
790 (N_NAMED_ARGS) != -1)
791
792 #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO)
793
794 /* Align based on stack boundary, which might have been set by the user. */
795 #define RISCV_STACK_ALIGN(LOC) \
796 (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
797
798 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
799 the stack pointer does not matter. The value is tested only in
800 functions that have frame pointers.
801 No definition is equivalent to always zero. */
802
803 #define EXIT_IGNORE_STACK 1
804
805
806 /* Trampolines are a block of code followed by two pointers. */
807
808 #define TRAMPOLINE_CODE_SIZE 16
809 #define TRAMPOLINE_SIZE \
810 ((Pmode == SImode) \
811 ? TRAMPOLINE_CODE_SIZE \
812 : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
813 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
814
815 /* Addressing modes, and classification of registers for them. */
816
817 #define REGNO_OK_FOR_INDEX_P(REGNO) \
818 riscv_regno_ok_for_index_p (REGNO)
819
820 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
821 riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
822
823 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
824 and check its validity for a certain class.
825 We have two alternate definitions for each of them.
826 The usual definition accepts all pseudo regs; the other rejects them all.
827 The symbol REG_OK_STRICT causes the latter definition to be used.
828
829 Most source files want to accept pseudo regs in the hope that
830 they will get allocated to the class that the insn wants them to be in.
831 Some source files that are used after register allocation
832 need to be strict. */
833
834 #ifndef REG_OK_STRICT
835 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
836 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
837 #else
838 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
839 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
840 #endif
841
842 #define REG_OK_FOR_INDEX_P(X) 0
843
844 /* Maximum number of registers that can appear in a valid memory address. */
845
846 #define MAX_REGS_PER_ADDRESS 1
847
848 #define CONSTANT_ADDRESS_P(X) \
849 (CONSTANT_P (X) && memory_address_p (SImode, X))
850
851 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
852 'the start of the function that this code is output in'. */
853
854 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
855 do { \
856 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
857 asm_fprintf ((FILE), "%U%s", \
858 XSTR (XEXP (DECL_RTL (current_function_decl), \
859 0), 0)); \
860 else \
861 asm_fprintf ((FILE), "%U%s", (NAME)); \
862 } while (0)
863
864 #undef ASM_OUTPUT_OPCODE
865 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
866 (PTR) = riscv_asm_output_opcode(STREAM, PTR)
867
868 #define JUMP_TABLES_IN_TEXT_SECTION 0
869 #define CASE_VECTOR_MODE SImode
870 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
871
872 #define LOCAL_SYM_P(sym) \
873 ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \
874 || ((GET_CODE (sym) == CONST) \
875 && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \
876 && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))
877
878 /* The load-address macro is used for PC-relative addressing of symbols
879 that bind locally. Don't use it for symbols that should be addressed
880 via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing
881 currently results in more opportunities for linker relaxation. */
882 #define USE_LOAD_ADDRESS_MACRO(sym) \
883 (!TARGET_EXPLICIT_RELOCS && \
884 ((flag_pic && LOCAL_SYM_P (sym)) || riscv_cmodel == CM_MEDANY))
885
886 /* Define this as 1 if `char' should by default be signed; else as 0. */
887 #define DEFAULT_SIGNED_CHAR 0
888
889 #define MOVE_MAX UNITS_PER_WORD
890 #define MAX_MOVE_MAX 8
891
892 /* The SPARC port says:
893 Nonzero if access to memory by bytes is slow and undesirable.
894 For RISC chips, it means that access to memory by bytes is no
895 better than access by words when possible, so grab a whole word
896 and maybe make use of that. */
897 #define SLOW_BYTE_ACCESS 1
898
899 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
900 in the md file instead. */
901 #define SHIFT_COUNT_TRUNCATED 0
902
903 /* Specify the machine mode that pointers have.
904 After generation of rtl, the compiler makes no further distinction
905 between pointers and any other objects of this machine mode. */
906
907 #define Pmode word_mode
908
909 /* Specify the machine mode that registers have. */
910
911 #define Xmode (TARGET_64BIT ? DImode : SImode)
912
913 /* Give call MEMs SImode since it is the "most permissive" mode
914 for both 32-bit and 64-bit targets. */
915
916 #define FUNCTION_MODE SImode
917
918 /* A C expression for the cost of a branch instruction. A value of 2
919 seems to minimize code size. */
920
921 #define BRANCH_COST(speed_p, predictable_p) \
922 ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
923
924 /* True if the target optimizes short forward branches around integer
925 arithmetic instructions into predicated operations, e.g., for
926 conditional-move operations. The macro assumes that all branch
927 instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
928 support this feature. The macro further assumes that any integer
929 arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
930 SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
931 counterparts, including C.MV and C.LI) can be in the branch shadow. */
932
933 #define TARGET_SFB_ALU \
934 ((riscv_microarchitecture == sifive_7) \
935 || (riscv_microarchitecture == sifive_p400) \
936 || (riscv_microarchitecture == sifive_p600))
937
938 /* True if the target supports misaligned vector loads and stores. */
939 #define TARGET_VECTOR_MISALIGN_SUPPORTED \
940 riscv_vector_unaligned_access_p
941
942 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
943
944 /* Control the assembler format that we output. */
945
946 /* Output to assembler file text saying following lines
947 may contain character constants, extra white space, comments, etc. */
948
949 #ifndef ASM_APP_ON
950 #define ASM_APP_ON " #APP\n"
951 #endif
952
953 /* Output to assembler file text saying following lines
954 no longer contain unusual constructs. */
955
956 #ifndef ASM_APP_OFF
957 #define ASM_APP_OFF " #NO_APP\n"
958 #endif
959
960 #define REGISTER_NAMES \
961 { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \
962 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \
963 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \
964 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \
965 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \
966 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \
967 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \
968 "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \
969 "arg", "frame", "vl", "vtype", "vxrm", "frm", "vxsat", "N/A", \
970 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
971 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
972 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
973 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
974 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
975 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
976 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",}
977
978 #define ADDITIONAL_REGISTER_NAMES \
979 { \
980 { "x0", 0 + GP_REG_FIRST }, \
981 { "x1", 1 + GP_REG_FIRST }, \
982 { "x2", 2 + GP_REG_FIRST }, \
983 { "x3", 3 + GP_REG_FIRST }, \
984 { "x4", 4 + GP_REG_FIRST }, \
985 { "x5", 5 + GP_REG_FIRST }, \
986 { "x6", 6 + GP_REG_FIRST }, \
987 { "x7", 7 + GP_REG_FIRST }, \
988 { "x8", 8 + GP_REG_FIRST }, \
989 { "x9", 9 + GP_REG_FIRST }, \
990 { "x10", 10 + GP_REG_FIRST }, \
991 { "x11", 11 + GP_REG_FIRST }, \
992 { "x12", 12 + GP_REG_FIRST }, \
993 { "x13", 13 + GP_REG_FIRST }, \
994 { "x14", 14 + GP_REG_FIRST }, \
995 { "x15", 15 + GP_REG_FIRST }, \
996 { "x16", 16 + GP_REG_FIRST }, \
997 { "x17", 17 + GP_REG_FIRST }, \
998 { "x18", 18 + GP_REG_FIRST }, \
999 { "x19", 19 + GP_REG_FIRST }, \
1000 { "x20", 20 + GP_REG_FIRST }, \
1001 { "x21", 21 + GP_REG_FIRST }, \
1002 { "x22", 22 + GP_REG_FIRST }, \
1003 { "x23", 23 + GP_REG_FIRST }, \
1004 { "x24", 24 + GP_REG_FIRST }, \
1005 { "x25", 25 + GP_REG_FIRST }, \
1006 { "x26", 26 + GP_REG_FIRST }, \
1007 { "x27", 27 + GP_REG_FIRST }, \
1008 { "x28", 28 + GP_REG_FIRST }, \
1009 { "x29", 29 + GP_REG_FIRST }, \
1010 { "x30", 30 + GP_REG_FIRST }, \
1011 { "x31", 31 + GP_REG_FIRST }, \
1012 { "f0", 0 + FP_REG_FIRST }, \
1013 { "f1", 1 + FP_REG_FIRST }, \
1014 { "f2", 2 + FP_REG_FIRST }, \
1015 { "f3", 3 + FP_REG_FIRST }, \
1016 { "f4", 4 + FP_REG_FIRST }, \
1017 { "f5", 5 + FP_REG_FIRST }, \
1018 { "f6", 6 + FP_REG_FIRST }, \
1019 { "f7", 7 + FP_REG_FIRST }, \
1020 { "f8", 8 + FP_REG_FIRST }, \
1021 { "f9", 9 + FP_REG_FIRST }, \
1022 { "f10", 10 + FP_REG_FIRST }, \
1023 { "f11", 11 + FP_REG_FIRST }, \
1024 { "f12", 12 + FP_REG_FIRST }, \
1025 { "f13", 13 + FP_REG_FIRST }, \
1026 { "f14", 14 + FP_REG_FIRST }, \
1027 { "f15", 15 + FP_REG_FIRST }, \
1028 { "f16", 16 + FP_REG_FIRST }, \
1029 { "f17", 17 + FP_REG_FIRST }, \
1030 { "f18", 18 + FP_REG_FIRST }, \
1031 { "f19", 19 + FP_REG_FIRST }, \
1032 { "f20", 20 + FP_REG_FIRST }, \
1033 { "f21", 21 + FP_REG_FIRST }, \
1034 { "f22", 22 + FP_REG_FIRST }, \
1035 { "f23", 23 + FP_REG_FIRST }, \
1036 { "f24", 24 + FP_REG_FIRST }, \
1037 { "f25", 25 + FP_REG_FIRST }, \
1038 { "f26", 26 + FP_REG_FIRST }, \
1039 { "f27", 27 + FP_REG_FIRST }, \
1040 { "f28", 28 + FP_REG_FIRST }, \
1041 { "f29", 29 + FP_REG_FIRST }, \
1042 { "f30", 30 + FP_REG_FIRST }, \
1043 { "f31", 31 + FP_REG_FIRST }, \
1044 }
1045
1046 /* Globalizing directive for a label. */
1047 #define GLOBAL_ASM_OP "\t.globl\t"
1048
1049 /* This is how to store into the string LABEL
1050 the symbol_ref name of an internal numbered label where
1051 PREFIX is the class of label and NUM is the number within the class.
1052 This is suitable for output with `assemble_name'. */
1053
1054 #undef ASM_GENERATE_INTERNAL_LABEL
1055 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1056 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
1057
1058 /* This is how to output an element of a case-vector that is absolute. */
1059
1060 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1061 fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
1062
1063 /* This is how to output an element of a PIC case-vector. */
1064
1065 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1066 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
1067 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
1068
1069 /* This is how to output an assembler line
1070 that says to advance the location counter
1071 to a multiple of 2**LOG bytes. */
1072
1073 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
1074 fprintf (STREAM, "\t.align\t%d\n", (LOG))
1075
1076 /* Define the strings to put out for each section in the object file. */
1077 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
1078 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
1079 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata"
1080 #define BSS_SECTION_ASM_OP "\t.bss"
1081 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits"
1082 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits"
1083
1084 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1085 do \
1086 { \
1087 fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
1088 reg_names[STACK_POINTER_REGNUM], \
1089 reg_names[STACK_POINTER_REGNUM], \
1090 TARGET_64BIT ? "sd" : "sw", \
1091 reg_names[REGNO], \
1092 reg_names[STACK_POINTER_REGNUM]); \
1093 } \
1094 while (0)
1095
1096 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1097 do \
1098 { \
1099 fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \
1100 TARGET_64BIT ? "ld" : "lw", \
1101 reg_names[REGNO], \
1102 reg_names[STACK_POINTER_REGNUM], \
1103 reg_names[STACK_POINTER_REGNUM], \
1104 reg_names[STACK_POINTER_REGNUM]); \
1105 } \
1106 while (0)
1107
1108 #define ASM_COMMENT_START "#"
1109
1110 /* Add output .variant_cc directive for specific function definition. */
1111 #undef ASM_DECLARE_FUNCTION_NAME
1112 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \
1113 riscv_declare_function_name (STR, NAME, DECL)
1114
1115 #undef ASM_DECLARE_FUNCTION_SIZE
1116 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1117 riscv_declare_function_size (FILE, FNAME, DECL)
1118
1119 /* Add output .variant_cc directive for specific alias definition. */
1120 #undef ASM_OUTPUT_DEF_FROM_DECLS
1121 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \
1122 riscv_asm_output_alias (STR, DECL, TARGET)
1123
1124 /* Add output .variant_cc directive for specific extern function. */
1125 #undef ASM_OUTPUT_EXTERNAL
1126 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \
1127 riscv_asm_output_external (STR, DECL, NAME)
1128
1129 #undef SIZE_TYPE
1130 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
1131
1132 #undef PTRDIFF_TYPE
1133 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
1134
1135 /* The maximum number of bytes copied by one iteration of a cpymemsi loop. */
1136
1137 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
1138
1139 /* The maximum number of bytes that can be copied by a straight-line
1140 cpymemsi implementation. */
1141
1142 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
1143
1144 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1145 move-instruction pairs, we will do a cpymem or libcall instead.
1146 Do not use move_by_pieces at all when strict alignment is not
1147 in effect but the target has slow unaligned accesses; in this
1148 case, cpymem or libcall is more efficient. */
1149
1150 #define MOVE_RATIO(speed) \
1151 (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \
1152 (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \
1153 CLEAR_RATIO (speed) / 2)
1154
1155 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
1156 of the length of a memset call, but use the default otherwise. */
1157
1158 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
1159
1160 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
1161 optimizing for size adjust the ratio to account for the overhead of
1162 loading the constant and replicating it across the word. */
1163
1164 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
1165
1166 #ifndef USED_FOR_TARGET
1167 extern const enum reg_class riscv_regno_to_class[];
1168 extern bool riscv_slow_unaligned_access_p;
1169 extern bool riscv_vector_unaligned_access_p;
1170 extern bool riscv_user_wants_strict_align;
1171 extern unsigned riscv_stack_boundary;
1172 extern unsigned riscv_bytes_per_vector_chunk;
1173 extern poly_uint16 riscv_vector_chunks;
1174 extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int);
1175 extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int);
1176 extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
1177 extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
1178 /* The number of bits and bytes in a RVV vector. */
1179 #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8))
1180 #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))
1181 #endif
1182
1183 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1184 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
1185
1186 #define XLEN_SPEC \
1187 "%{march=rv32*:32}" \
1188 "%{march=rv64*:64}" \
1189
1190 #define ABI_SPEC \
1191 "%{mabi=ilp32:ilp32}" \
1192 "%{mabi=ilp32e:ilp32e}" \
1193 "%{mabi=ilp32f:ilp32f}" \
1194 "%{mabi=ilp32d:ilp32d}" \
1195 "%{mabi=lp64:lp64}" \
1196 "%{mabi=lp64e:lp64e}" \
1197 "%{mabi=lp64f:lp64f}" \
1198 "%{mabi=lp64d:lp64d}" \
1199
1200 /* ISA constants needed for code generation. */
1201 #define OPCODE_LW 0x2003
1202 #define OPCODE_LD 0x3003
1203 #define OPCODE_AUIPC 0x17
1204 #define OPCODE_JALR 0x67
1205 #define OPCODE_LUI 0x37
1206 #define OPCODE_ADDI 0x13
1207 #define SHIFT_RD 7
1208 #define SHIFT_RS1 15
1209 #define SHIFT_IMM 20
1210 #define IMM_BITS 12
1211 #define C_S_BITS 5
1212 #define C_SxSP_BITS 6
1213
1214 #define IMM_REACH (1LL << IMM_BITS)
1215 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
1216 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
1217
1218 #define SWSP_REACH (4LL << C_SxSP_BITS)
1219 #define SDSP_REACH (8LL << C_SxSP_BITS)
1220
1221 /* This is the maximum value that can be represented in a compressed load/store
1222 offset (an unsigned 5-bit value scaled by 4). */
1223 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)
1224
1225 /* Called from RISCV_REORG, this is defined in riscv-sr.cc. */
1226
1227 extern void riscv_remove_unneeded_save_restore_calls (void);
1228
1229 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
1230
1231 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1232 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1233 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1234 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1235
1236 #define TARGET_SUPPORTS_WIDE_INT 1
1237
1238 #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas ()
1239
1240 #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE)
1241
1242 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */)
1243
1244 #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \
1245 ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO)
1246
1247 /* Like s390, riscv also defined this macro for the vector comparision. Then
1248 the simplify-rtx relational_result will canonicalize the result to the
1249 CONST1_RTX for the simplification. */
1250 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE))
1251
1252 /* Mode switching (Lazy code motion) for RVV rounding mode instructions. */
1253 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
1254 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
1255
1256 /* The size difference between different RVV modes can be up to 64 times.
1257 e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64]. */
1258 #define MAX_POLY_VARIANT 64
1259
1260 #define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX
1261 #define HAVE_PRE_MODIFY_DISP TARGET_XTHEADMEMIDX
1262
1263 /* Check TLS Descriptors mechanism is selected. */
1264 #define TARGET_TLSDESC (riscv_tls_dialect == TLS_DESCRIPTORS)
1265
1266 /* This value is the amount of bytes a caller is allowed to drop the stack
1267 before probing has to be done for stack clash protection. */
1268 #define STACK_CLASH_CALLER_GUARD 1024
1269
1270 /* This value controls how many pages we manually unroll the loop for when
1271 generating stack clash probes. */
1272 #define STACK_CLASH_MAX_UNROLL_PAGES 4
1273
1274 /* This value represents the minimum amount of bytes we expect the function's
1275 outgoing arguments to be when stack-clash is enabled. */
1276 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8
1277
1278 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the
1279 outgoing arguments if stack clash protection is enabled. This is essential
1280 as the extra arg space allows us to skip a check in alloca. */
1281 #undef STACK_DYNAMIC_OFFSET
1282 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1283 ((flag_stack_clash_protection \
1284 && cfun->calls_alloca \
1285 && known_lt (crtl->outgoing_args_size, \
1286 STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \
1287 ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \
1288 STACK_BOUNDARY / BITS_PER_UNIT) \
1289 : (crtl->outgoing_args_size + STACK_POINTER_OFFSET))
1290
1291 #endif /* ! GCC_RISCV_H */
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