RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
	Add new function to add assembler insn code prefix/suffix.
	(th_asm_output_opcode):
	Add Thead function to add assembler insn code prefix/suffix.
	* config/riscv/riscv.cc (riscv_asm_output_opcode):
	Implement function to add assembler insn code prefix/suffix.
	* config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
	Add new function to add assembler insn code prefix/suffix.
	* config/riscv/thead.cc (th_asm_output_opcode):
	Implement Thead function to add assembler insn code
	prefix/suffix.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/prefix.c: New test.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>