?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Correct /is4 encoding for EVEX instructions
[nasm.git] / assemble.c
blob4c8415fde4b91aa6f224b645a1f1080285ef3783
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2016 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 000 0mm
85 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183 #include <inttypes.h>
184
185 #include "nasm.h"
186 #include "nasmlib.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191 #include "listing.h"
192
193 enum match_result {
194 /*
195 * Matching errors. These should be sorted so that more specific
196 * errors come later in the sequence.
197 */
198 MERR_INVALOP,
199 MERR_OPSIZEMISSING,
200 MERR_OPSIZEMISMATCH,
201 MERR_BRNUMMISMATCH,
202 MERR_BADCPU,
203 MERR_BADMODE,
204 MERR_BADHLE,
205 MERR_ENCMISMATCH,
206 MERR_BADBND,
207 MERR_BADREPNE,
208 /*
209 * Matching success; the conditional ones first
210 */
211 MOK_JUMP, /* Matching OK but needs jmp_match() */
212 MOK_GOOD /* Matching unconditionally OK */
213 };
214
215 typedef struct {
216 enum ea_type type; /* what kind of EA is this? */
217 int sib_present; /* is a SIB byte necessary? */
218 int bytes; /* # of bytes of offset needed */
219 int size; /* lazy - this is sib+bytes+1 */
220 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
221 int8_t disp8; /* compressed displacement for EVEX */
222 } ea;
223
224 #define GEN_SIB(scale, index, base) \
225 (((scale) << 6) | ((index) << 3) | ((base)))
226
227 #define GEN_MODRM(mod, reg, rm) \
228 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
229
230 static iflag_t cpu; /* cpu level received from nasm.c */
231
232 static int64_t calcsize(int32_t, int64_t, int, insn *,
233 const struct itemplate *);
234 static void gencode(int32_t segment, int64_t offset, int bits,
235 insn * ins, const struct itemplate *temp,
236 int64_t insn_end);
237 static enum match_result find_match(const struct itemplate **tempp,
238 insn *instruction,
239 int32_t segment, int64_t offset, int bits);
240 static enum match_result matches(const struct itemplate *, insn *, int bits);
241 static opflags_t regflag(const operand *);
242 static int32_t regval(const operand *);
243 static int rexflags(int, opflags_t, int);
244 static int op_rexflags(const operand *, int);
245 static int op_evexflags(const operand *, int, uint8_t);
246 static void add_asp(insn *, int);
247
248 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
249
250 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
251 {
252 return ins->prefixes[pos] == prefix;
253 }
254
255 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
256 {
257 if (ins->prefixes[pos])
258 nasm_error(ERR_NONFATAL, "invalid %s prefix",
259 prefix_name(ins->prefixes[pos]));
260 }
261
262 static const char *size_name(int size)
263 {
264 switch (size) {
265 case 1:
266 return "byte";
267 case 2:
268 return "word";
269 case 4:
270 return "dword";
271 case 8:
272 return "qword";
273 case 10:
274 return "tword";
275 case 16:
276 return "oword";
277 case 32:
278 return "yword";
279 case 64:
280 return "zword";
281 default:
282 return "???";
283 }
284 }
285
286 static void warn_overflow(int pass, int size)
287 {
288 nasm_error(ERR_WARNING | pass | ERR_WARN_NOV,
289 "%s data exceeds bounds", size_name(size));
290 }
291
292 static void warn_overflow_const(int64_t data, int size)
293 {
294 if (overflow_general(data, size))
295 warn_overflow(ERR_PASS1, size);
296 }
297
298 static void warn_overflow_opd(const struct operand *o, int size)
299 {
300 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
301 if (overflow_general(o->offset, size))
302 warn_overflow(ERR_PASS2, size);
303 }
304 }
305
306 /*
307 * Size of an address relocation, or zero if not an address
308 */
309 static int addrsize(enum out_type type, uint64_t size)
310 {
311 switch (type) {
312 case OUT_ADDRESS:
313 return abs((int)size);
314 case OUT_REL1ADR:
315 return 1;
316 case OUT_REL2ADR:
317 return 2;
318 case OUT_REL4ADR:
319 return 4;
320 case OUT_REL8ADR:
321 return 8;
322 default:
323 return 0;
324 }
325 }
326
327 /*
328 * This routine wrappers the real output format's output routine,
329 * in order to pass a copy of the data off to the listing file
330 * generator at the same time, flatten unnecessary relocations,
331 * and verify backend compatibility.
332 */
333 static void out(int64_t offset, int32_t segto, const void *data,
334 enum out_type type, uint64_t size,
335 int32_t segment, int32_t wrt)
336 {
337 static int32_t lineno = 0; /* static!!! */
338 static const char *lnfname = NULL;
339 uint8_t p[8];
340 int asize = addrsize(type, size); /* Address size in bytes */
341 const int amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
342
343 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
344 /*
345 * This is a non-relocated address, and we're going to
346 * convert it into RAWDATA format.
347 */
348 uint8_t *q = p;
349
350 if (asize > 8) {
351 nasm_panic(0, "OUT_ADDRESS with size > 8");
352 return;
353 }
354
355 WRITEADDR(q, *(int64_t *)data, asize);
356 data = p;
357 type = OUT_RAWDATA;
358 size = asize;
359 asize = 0; /* No longer an address */
360 }
361
362 lfmt->output(offset, data, type, size);
363
364 /*
365 * this call to src_get determines when we call the
366 * debug-format-specific "linenum" function
367 * it updates lineno and lnfname to the current values
368 * returning 0 if "same as last time", -2 if lnfname
369 * changed, and the amount by which lineno changed,
370 * if it did. thus, these variables must be static
371 */
372
373 if (src_get(&lineno, &lnfname))
374 dfmt->linenum(lnfname, lineno, segto);
375
376 if (asize && asize > amax) {
377 if (type != OUT_ADDRESS || (int)size < 0) {
378 nasm_error(ERR_NONFATAL,
379 "%d-bit signed relocation unsupported by output format %s\n",
380 asize << 3, ofmt->shortname);
381 size = asize;
382 } else {
383 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
384 "%d-bit unsigned relocation zero-extended from %d bits\n",
385 asize << 3, ofmt->maxbits);
386 ofmt->output(segto, data, type, amax, segment, wrt);
387 size = asize - amax;
388 }
389 data = zero_buffer;
390 type = OUT_RAWDATA;
391 segment = wrt = NO_SEG;
392 }
393
394 ofmt->output(segto, data, type, size, segment, wrt);
395 }
396
397 static void out_imm8(int64_t offset, int32_t segment,
398 struct operand *opx, int asize)
399 {
400 if (opx->segment != NO_SEG) {
401 uint64_t data = opx->offset;
402 out(offset, segment, &data, OUT_ADDRESS, asize, opx->segment, opx->wrt);
403 } else {
404 uint8_t byte = opx->offset;
405 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
406 }
407 }
408
409 static bool jmp_match(int32_t segment, int64_t offset, int bits,
410 insn * ins, const struct itemplate *temp)
411 {
412 int64_t isize;
413 const uint8_t *code = temp->code;
414 uint8_t c = code[0];
415 bool is_byte;
416
417 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
418 return false;
419 if (!optimizing)
420 return false;
421 if (optimizing < 0 && c == 0371)
422 return false;
423
424 isize = calcsize(segment, offset, bits, ins, temp);
425
426 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
427 /* Be optimistic in pass 1 */
428 return true;
429
430 if (ins->oprs[0].segment != segment)
431 return false;
432
433 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
434 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
435
436 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
437 /* jmp short (opcode eb) cannot be used with bnd prefix. */
438 ins->prefixes[PPS_REP] = P_none;
439 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
440 "jmp short does not init bnd regs - bnd prefix dropped.");
441 }
442
443 return is_byte;
444 }
445
446 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
447 insn * instruction)
448 {
449 const struct itemplate *temp;
450 int j;
451 enum match_result m;
452 int64_t insn_end;
453 int32_t itimes;
454 int64_t start = offset;
455 int64_t wsize; /* size for DB etc. */
456
457 cpu = cp;
458
459 wsize = idata_bytes(instruction->opcode);
460 if (wsize == -1)
461 return 0;
462
463 if (wsize) {
464 extop *e;
465 int32_t t = instruction->times;
466 if (t < 0)
467 nasm_panic(0, "instruction->times < 0 (%"PRId32") in assemble()", t);
468
469 while (t--) { /* repeat TIMES times */
470 list_for_each(e, instruction->eops) {
471 if (e->type == EOT_DB_NUMBER) {
472 if (wsize > 8) {
473 nasm_error(ERR_NONFATAL,
474 "integer supplied to a DT, DO or DY"
475 " instruction");
476 } else {
477 out(offset, segment, &e->offset,
478 OUT_ADDRESS, wsize, e->segment, e->wrt);
479 offset += wsize;
480 }
481 } else if (e->type == EOT_DB_STRING ||
482 e->type == EOT_DB_STRING_FREE) {
483 int align;
484
485 out(offset, segment, e->stringval,
486 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
487 align = e->stringlen % wsize;
488
489 if (align) {
490 align = wsize - align;
491 out(offset, segment, zero_buffer,
492 OUT_RAWDATA, align, NO_SEG, NO_SEG);
493 }
494 offset += e->stringlen + align;
495 }
496 }
497 if (t > 0 && t == instruction->times - 1) {
498 /*
499 * Dummy call to lfmt->output to give the offset to the
500 * listing module.
501 */
502 lfmt->output(offset, NULL, OUT_RAWDATA, 0);
503 lfmt->uplevel(LIST_TIMES);
504 }
505 }
506 if (instruction->times > 1)
507 lfmt->downlevel(LIST_TIMES);
508 return offset - start;
509 }
510
511 if (instruction->opcode == I_INCBIN) {
512 const char *fname = instruction->eops->stringval;
513 FILE *fp;
514
515 fp = fopen(fname, "rb");
516 if (!fp) {
517 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
518 fname);
519 } else if (fseek(fp, 0L, SEEK_END) < 0) {
520 nasm_error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
521 fname);
522 fclose(fp);
523 } else {
524 static char buf[4096];
525 size_t t = instruction->times;
526 size_t base = 0;
527 size_t len;
528
529 len = ftell(fp);
530 if (instruction->eops->next) {
531 base = instruction->eops->next->offset;
532 len -= base;
533 if (instruction->eops->next->next &&
534 len > (size_t)instruction->eops->next->next->offset)
535 len = (size_t)instruction->eops->next->next->offset;
536 }
537 /*
538 * Dummy call to lfmt->output to give the offset to the
539 * listing module.
540 */
541 lfmt->output(offset, NULL, OUT_RAWDATA, 0);
542 lfmt->uplevel(LIST_INCBIN);
543 while (t--) {
544 size_t l;
545
546 fseek(fp, base, SEEK_SET);
547 l = len;
548 while (l > 0) {
549 int32_t m;
550 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
551 if (!m) {
552 /*
553 * This shouldn't happen unless the file
554 * actually changes while we are reading
555 * it.
556 */
557 nasm_error(ERR_NONFATAL,
558 "`incbin': unexpected EOF while"
559 " reading file `%s'", fname);
560 t = 0; /* Try to exit cleanly */
561 break;
562 }
563 out(offset, segment, buf, OUT_RAWDATA, m,
564 NO_SEG, NO_SEG);
565 l -= m;
566 }
567 }
568 lfmt->downlevel(LIST_INCBIN);
569 if (instruction->times > 1) {
570 /*
571 * Dummy call to lfmt->output to give the offset to the
572 * listing module.
573 */
574 lfmt->output(offset, NULL, OUT_RAWDATA, 0);
575 lfmt->uplevel(LIST_TIMES);
576 lfmt->downlevel(LIST_TIMES);
577 }
578 fclose(fp);
579 return instruction->times * len;
580 }
581 return 0; /* if we're here, there's an error */
582 }
583
584 /* Check to see if we need an address-size prefix */
585 add_asp(instruction, bits);
586
587 m = find_match(&temp, instruction, segment, offset, bits);
588
589 if (m == MOK_GOOD) {
590 /* Matches! */
591 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
592 itimes = instruction->times;
593 if (insn_size < 0) /* shouldn't be, on pass two */
594 nasm_panic(0, "errors made it through from pass one");
595 else
596 while (itimes--) {
597 for (j = 0; j < MAXPREFIX; j++) {
598 uint8_t c = 0;
599 switch (instruction->prefixes[j]) {
600 case P_WAIT:
601 c = 0x9B;
602 break;
603 case P_LOCK:
604 c = 0xF0;
605 break;
606 case P_REPNE:
607 case P_REPNZ:
608 case P_XACQUIRE:
609 case P_BND:
610 c = 0xF2;
611 break;
612 case P_REPE:
613 case P_REPZ:
614 case P_REP:
615 case P_XRELEASE:
616 c = 0xF3;
617 break;
618 case R_CS:
619 if (bits == 64) {
620 nasm_error(ERR_WARNING | ERR_PASS2,
621 "cs segment base generated, but will be ignored in 64-bit mode");
622 }
623 c = 0x2E;
624 break;
625 case R_DS:
626 if (bits == 64) {
627 nasm_error(ERR_WARNING | ERR_PASS2,
628 "ds segment base generated, but will be ignored in 64-bit mode");
629 }
630 c = 0x3E;
631 break;
632 case R_ES:
633 if (bits == 64) {
634 nasm_error(ERR_WARNING | ERR_PASS2,
635 "es segment base generated, but will be ignored in 64-bit mode");
636 }
637 c = 0x26;
638 break;
639 case R_FS:
640 c = 0x64;
641 break;
642 case R_GS:
643 c = 0x65;
644 break;
645 case R_SS:
646 if (bits == 64) {
647 nasm_error(ERR_WARNING | ERR_PASS2,
648 "ss segment base generated, but will be ignored in 64-bit mode");
649 }
650 c = 0x36;
651 break;
652 case R_SEGR6:
653 case R_SEGR7:
654 nasm_error(ERR_NONFATAL,
655 "segr6 and segr7 cannot be used as prefixes");
656 break;
657 case P_A16:
658 if (bits == 64) {
659 nasm_error(ERR_NONFATAL,
660 "16-bit addressing is not supported "
661 "in 64-bit mode");
662 } else if (bits != 16)
663 c = 0x67;
664 break;
665 case P_A32:
666 if (bits != 32)
667 c = 0x67;
668 break;
669 case P_A64:
670 if (bits != 64) {
671 nasm_error(ERR_NONFATAL,
672 "64-bit addressing is only supported "
673 "in 64-bit mode");
674 }
675 break;
676 case P_ASP:
677 c = 0x67;
678 break;
679 case P_O16:
680 if (bits != 16)
681 c = 0x66;
682 break;
683 case P_O32:
684 if (bits == 16)
685 c = 0x66;
686 break;
687 case P_O64:
688 /* REX.W */
689 break;
690 case P_OSP:
691 c = 0x66;
692 break;
693 case P_EVEX:
694 case P_VEX3:
695 case P_VEX2:
696 case P_NOBND:
697 case P_none:
698 break;
699 default:
700 nasm_panic(0, "invalid instruction prefix");
701 }
702 if (c != 0) {
703 out(offset, segment, &c, OUT_RAWDATA, 1,
704 NO_SEG, NO_SEG);
705 offset++;
706 }
707 }
708 insn_end = offset + insn_size;
709 gencode(segment, offset, bits, instruction,
710 temp, insn_end);
711 offset += insn_size;
712 if (itimes > 0 && itimes == instruction->times - 1) {
713 /*
714 * Dummy call to lfmt->output to give the offset to the
715 * listing module.
716 */
717 lfmt->output(offset, NULL, OUT_RAWDATA, 0);
718 lfmt->uplevel(LIST_TIMES);
719 }
720 }
721 if (instruction->times > 1)
722 lfmt->downlevel(LIST_TIMES);
723 return offset - start;
724 } else {
725 /* No match */
726 switch (m) {
727 case MERR_OPSIZEMISSING:
728 nasm_error(ERR_NONFATAL, "operation size not specified");
729 break;
730 case MERR_OPSIZEMISMATCH:
731 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
732 break;
733 case MERR_BRNUMMISMATCH:
734 nasm_error(ERR_NONFATAL,
735 "mismatch in the number of broadcasting elements");
736 break;
737 case MERR_BADCPU:
738 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
739 break;
740 case MERR_BADMODE:
741 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
742 bits);
743 break;
744 case MERR_ENCMISMATCH:
745 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
746 break;
747 case MERR_BADBND:
748 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
749 break;
750 case MERR_BADREPNE:
751 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
752 (has_prefix(instruction, PPS_REP, P_REPNE) ?
753 "repne" : "repnz"));
754 break;
755 default:
756 nasm_error(ERR_NONFATAL,
757 "invalid combination of opcode and operands");
758 break;
759 }
760 }
761 return 0;
762 }
763
764 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
765 insn * instruction)
766 {
767 const struct itemplate *temp;
768 enum match_result m;
769
770 cpu = cp;
771
772 if (instruction->opcode == I_none)
773 return 0;
774
775 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
776 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
777 instruction->opcode == I_DT || instruction->opcode == I_DO ||
778 instruction->opcode == I_DY) {
779 extop *e;
780 int32_t isize, osize, wsize;
781
782 isize = 0;
783 wsize = idata_bytes(instruction->opcode);
784
785 list_for_each(e, instruction->eops) {
786 int32_t align;
787
788 osize = 0;
789 if (e->type == EOT_DB_NUMBER) {
790 osize = 1;
791 warn_overflow_const(e->offset, wsize);
792 } else if (e->type == EOT_DB_STRING ||
793 e->type == EOT_DB_STRING_FREE)
794 osize = e->stringlen;
795
796 align = (-osize) % wsize;
797 if (align < 0)
798 align += wsize;
799 isize += osize + align;
800 }
801 return isize * instruction->times;
802 }
803
804 if (instruction->opcode == I_INCBIN) {
805 const char *fname = instruction->eops->stringval;
806 FILE *fp;
807 int64_t val = 0;
808 size_t len;
809
810 fp = fopen(fname, "rb");
811 if (!fp)
812 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
813 fname);
814 else if (fseek(fp, 0L, SEEK_END) < 0)
815 nasm_error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
816 fname);
817 else {
818 len = ftell(fp);
819 if (instruction->eops->next) {
820 len -= instruction->eops->next->offset;
821 if (instruction->eops->next->next &&
822 len > (size_t)instruction->eops->next->next->offset) {
823 len = (size_t)instruction->eops->next->next->offset;
824 }
825 }
826 val = instruction->times * len;
827 }
828 if (fp)
829 fclose(fp);
830 return val;
831 }
832
833 /* Check to see if we need an address-size prefix */
834 add_asp(instruction, bits);
835
836 m = find_match(&temp, instruction, segment, offset, bits);
837 if (m == MOK_GOOD) {
838 /* we've matched an instruction. */
839 int64_t isize;
840 int j;
841
842 isize = calcsize(segment, offset, bits, instruction, temp);
843 if (isize < 0)
844 return -1;
845 for (j = 0; j < MAXPREFIX; j++) {
846 switch (instruction->prefixes[j]) {
847 case P_A16:
848 if (bits != 16)
849 isize++;
850 break;
851 case P_A32:
852 if (bits != 32)
853 isize++;
854 break;
855 case P_O16:
856 if (bits != 16)
857 isize++;
858 break;
859 case P_O32:
860 if (bits == 16)
861 isize++;
862 break;
863 case P_A64:
864 case P_O64:
865 case P_EVEX:
866 case P_VEX3:
867 case P_VEX2:
868 case P_NOBND:
869 case P_none:
870 break;
871 default:
872 isize++;
873 break;
874 }
875 }
876 return isize * instruction->times;
877 } else {
878 return -1; /* didn't match any instruction */
879 }
880 }
881
882 static void bad_hle_warn(const insn * ins, uint8_t hleok)
883 {
884 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
885 enum whatwarn { w_none, w_lock, w_inval } ww;
886 static const enum whatwarn warn[2][4] =
887 {
888 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
889 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
890 };
891 unsigned int n;
892
893 n = (unsigned int)rep_pfx - P_XACQUIRE;
894 if (n > 1)
895 return; /* Not XACQUIRE/XRELEASE */
896
897 ww = warn[n][hleok];
898 if (!is_class(MEMORY, ins->oprs[0].type))
899 ww = w_inval; /* HLE requires operand 0 to be memory */
900
901 switch (ww) {
902 case w_none:
903 break;
904
905 case w_lock:
906 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
907 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
908 "%s with this instruction requires lock",
909 prefix_name(rep_pfx));
910 }
911 break;
912
913 case w_inval:
914 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
915 "%s invalid with this instruction",
916 prefix_name(rep_pfx));
917 break;
918 }
919 }
920
921 /* Common construct */
922 #define case3(x) case (x): case (x)+1: case (x)+2
923 #define case4(x) case3(x): case (x)+3
924
925 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
926 insn * ins, const struct itemplate *temp)
927 {
928 const uint8_t *codes = temp->code;
929 int64_t length = 0;
930 uint8_t c;
931 int rex_mask = ~0;
932 int op1, op2;
933 struct operand *opx;
934 uint8_t opex = 0;
935 enum ea_type eat;
936 uint8_t hleok = 0;
937 bool lockcheck = true;
938 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
939
940 ins->rex = 0; /* Ensure REX is reset */
941 eat = EA_SCALAR; /* Expect a scalar EA */
942 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
943
944 if (ins->prefixes[PPS_OSIZE] == P_O64)
945 ins->rex |= REX_W;
946
947 (void)segment; /* Don't warn that this parameter is unused */
948 (void)offset; /* Don't warn that this parameter is unused */
949
950 while (*codes) {
951 c = *codes++;
952 op1 = (c & 3) + ((opex & 1) << 2);
953 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
954 opx = &ins->oprs[op1];
955 opex = 0; /* For the next iteration */
956
957 switch (c) {
958 case4(01):
959 codes += c, length += c;
960 break;
961
962 case3(05):
963 opex = c;
964 break;
965
966 case4(010):
967 ins->rex |=
968 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
969 codes++, length++;
970 break;
971
972 case4(014):
973 /* this is an index reg of MIB operand */
974 mib_index = opx->basereg;
975 break;
976
977 case4(020):
978 case4(024):
979 length++;
980 break;
981
982 case4(030):
983 length += 2;
984 break;
985
986 case4(034):
987 if (opx->type & (BITS16 | BITS32 | BITS64))
988 length += (opx->type & BITS16) ? 2 : 4;
989 else
990 length += (bits == 16) ? 2 : 4;
991 break;
992
993 case4(040):
994 length += 4;
995 break;
996
997 case4(044):
998 length += ins->addr_size >> 3;
999 break;
1000
1001 case4(050):
1002 length++;
1003 break;
1004
1005 case4(054):
1006 length += 8; /* MOV reg64/imm */
1007 break;
1008
1009 case4(060):
1010 length += 2;
1011 break;
1012
1013 case4(064):
1014 if (opx->type & (BITS16 | BITS32 | BITS64))
1015 length += (opx->type & BITS16) ? 2 : 4;
1016 else
1017 length += (bits == 16) ? 2 : 4;
1018 break;
1019
1020 case4(070):
1021 length += 4;
1022 break;
1023
1024 case4(074):
1025 length += 2;
1026 break;
1027
1028 case 0172:
1029 case 0173:
1030 codes++;
1031 length++;
1032 break;
1033
1034 case4(0174):
1035 length++;
1036 break;
1037
1038 case4(0240):
1039 ins->rex |= REX_EV;
1040 ins->vexreg = regval(opx);
1041 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1042 ins->vex_cm = *codes++;
1043 ins->vex_wlp = *codes++;
1044 ins->evex_tuple = (*codes++ - 0300);
1045 break;
1046
1047 case 0250:
1048 ins->rex |= REX_EV;
1049 ins->vexreg = 0;
1050 ins->vex_cm = *codes++;
1051 ins->vex_wlp = *codes++;
1052 ins->evex_tuple = (*codes++ - 0300);
1053 break;
1054
1055 case4(0254):
1056 length += 4;
1057 break;
1058
1059 case4(0260):
1060 ins->rex |= REX_V;
1061 ins->vexreg = regval(opx);
1062 ins->vex_cm = *codes++;
1063 ins->vex_wlp = *codes++;
1064 break;
1065
1066 case 0270:
1067 ins->rex |= REX_V;
1068 ins->vexreg = 0;
1069 ins->vex_cm = *codes++;
1070 ins->vex_wlp = *codes++;
1071 break;
1072
1073 case3(0271):
1074 hleok = c & 3;
1075 break;
1076
1077 case4(0274):
1078 length++;
1079 break;
1080
1081 case4(0300):
1082 break;
1083
1084 case 0310:
1085 if (bits == 64)
1086 return -1;
1087 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1088 break;
1089
1090 case 0311:
1091 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1092 break;
1093
1094 case 0312:
1095 break;
1096
1097 case 0313:
1098 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1099 has_prefix(ins, PPS_ASIZE, P_A32))
1100 return -1;
1101 break;
1102
1103 case4(0314):
1104 break;
1105
1106 case 0320:
1107 {
1108 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1109 if (pfx == P_O16)
1110 break;
1111 if (pfx != P_none)
1112 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1113 else
1114 ins->prefixes[PPS_OSIZE] = P_O16;
1115 break;
1116 }
1117
1118 case 0321:
1119 {
1120 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1121 if (pfx == P_O32)
1122 break;
1123 if (pfx != P_none)
1124 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1125 else
1126 ins->prefixes[PPS_OSIZE] = P_O32;
1127 break;
1128 }
1129
1130 case 0322:
1131 break;
1132
1133 case 0323:
1134 rex_mask &= ~REX_W;
1135 break;
1136
1137 case 0324:
1138 ins->rex |= REX_W;
1139 break;
1140
1141 case 0325:
1142 ins->rex |= REX_NH;
1143 break;
1144
1145 case 0326:
1146 break;
1147
1148 case 0330:
1149 codes++, length++;
1150 break;
1151
1152 case 0331:
1153 break;
1154
1155 case 0332:
1156 case 0333:
1157 length++;
1158 break;
1159
1160 case 0334:
1161 ins->rex |= REX_L;
1162 break;
1163
1164 case 0335:
1165 break;
1166
1167 case 0336:
1168 if (!ins->prefixes[PPS_REP])
1169 ins->prefixes[PPS_REP] = P_REP;
1170 break;
1171
1172 case 0337:
1173 if (!ins->prefixes[PPS_REP])
1174 ins->prefixes[PPS_REP] = P_REPNE;
1175 break;
1176
1177 case 0340:
1178 if (ins->oprs[0].segment != NO_SEG)
1179 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1180 " quantity of BSS space");
1181 else
1182 length += ins->oprs[0].offset;
1183 break;
1184
1185 case 0341:
1186 if (!ins->prefixes[PPS_WAIT])
1187 ins->prefixes[PPS_WAIT] = P_WAIT;
1188 break;
1189
1190 case 0360:
1191 break;
1192
1193 case 0361:
1194 length++;
1195 break;
1196
1197 case 0364:
1198 case 0365:
1199 break;
1200
1201 case 0366:
1202 case 0367:
1203 length++;
1204 break;
1205
1206 case 0370:
1207 case 0371:
1208 break;
1209
1210 case 0373:
1211 length++;
1212 break;
1213
1214 case 0374:
1215 eat = EA_XMMVSIB;
1216 break;
1217
1218 case 0375:
1219 eat = EA_YMMVSIB;
1220 break;
1221
1222 case 0376:
1223 eat = EA_ZMMVSIB;
1224 break;
1225
1226 case4(0100):
1227 case4(0110):
1228 case4(0120):
1229 case4(0130):
1230 case4(0200):
1231 case4(0204):
1232 case4(0210):
1233 case4(0214):
1234 case4(0220):
1235 case4(0224):
1236 case4(0230):
1237 case4(0234):
1238 {
1239 ea ea_data;
1240 int rfield;
1241 opflags_t rflags;
1242 struct operand *opy = &ins->oprs[op2];
1243 struct operand *op_er_sae;
1244
1245 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1246
1247 if (c <= 0177) {
1248 /* pick rfield from operand b (opx) */
1249 rflags = regflag(opx);
1250 rfield = nasm_regvals[opx->basereg];
1251 } else {
1252 rflags = 0;
1253 rfield = c & 7;
1254 }
1255
1256 /* EVEX.b1 : evex_brerop contains the operand position */
1257 op_er_sae = (ins->evex_brerop >= 0 ?
1258 &ins->oprs[ins->evex_brerop] : NULL);
1259
1260 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1261 /* set EVEX.b */
1262 ins->evex_p[2] |= EVEX_P2B;
1263 if (op_er_sae->decoflags & ER) {
1264 /* set EVEX.RC (rounding control) */
1265 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1266 & EVEX_P2RC;
1267 }
1268 } else {
1269 /* set EVEX.L'L (vector length) */
1270 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1271 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1272 if (opy->decoflags & BRDCAST_MASK) {
1273 /* set EVEX.b */
1274 ins->evex_p[2] |= EVEX_P2B;
1275 }
1276 }
1277
1278 if (itemp_has(temp, IF_MIB)) {
1279 opy->eaflags |= EAF_MIB;
1280 /*
1281 * if a separate form of MIB (ICC style) is used,
1282 * the index reg info is merged into mem operand
1283 */
1284 if (mib_index != R_none) {
1285 opy->indexreg = mib_index;
1286 opy->scale = 1;
1287 opy->hintbase = mib_index;
1288 opy->hinttype = EAH_NOTBASE;
1289 }
1290 }
1291
1292 if (process_ea(opy, &ea_data, bits,
1293 rfield, rflags, ins) != eat) {
1294 nasm_error(ERR_NONFATAL, "invalid effective address");
1295 return -1;
1296 } else {
1297 ins->rex |= ea_data.rex;
1298 length += ea_data.size;
1299 }
1300 }
1301 break;
1302
1303 default:
1304 nasm_panic(0, "internal instruction table corrupt"
1305 ": instruction code \\%o (0x%02X) given", c, c);
1306 break;
1307 }
1308 }
1309
1310 ins->rex &= rex_mask;
1311
1312 if (ins->rex & REX_NH) {
1313 if (ins->rex & REX_H) {
1314 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1315 return -1;
1316 }
1317 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1318 }
1319
1320 switch (ins->prefixes[PPS_VEX]) {
1321 case P_EVEX:
1322 if (!(ins->rex & REX_EV))
1323 return -1;
1324 break;
1325 case P_VEX3:
1326 case P_VEX2:
1327 if (!(ins->rex & REX_V))
1328 return -1;
1329 break;
1330 default:
1331 break;
1332 }
1333
1334 if (ins->rex & (REX_V | REX_EV)) {
1335 int bad32 = REX_R|REX_W|REX_X|REX_B;
1336
1337 if (ins->rex & REX_H) {
1338 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1339 return -1;
1340 }
1341 switch (ins->vex_wlp & 060) {
1342 case 000:
1343 case 040:
1344 ins->rex &= ~REX_W;
1345 break;
1346 case 020:
1347 ins->rex |= REX_W;
1348 bad32 &= ~REX_W;
1349 break;
1350 case 060:
1351 /* Follow REX_W */
1352 break;
1353 }
1354
1355 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1356 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1357 return -1;
1358 } else if (!(ins->rex & REX_EV) &&
1359 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1360 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1361 return -1;
1362 }
1363 if (ins->rex & REX_EV)
1364 length += 4;
1365 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1366 ins->prefixes[PPS_VEX] == P_VEX3)
1367 length += 3;
1368 else
1369 length += 2;
1370 } else if (ins->rex & REX_MASK) {
1371 if (ins->rex & REX_H) {
1372 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1373 return -1;
1374 } else if (bits == 64) {
1375 length++;
1376 } else if ((ins->rex & REX_L) &&
1377 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1378 iflag_ffs(&cpu) >= IF_X86_64) {
1379 /* LOCK-as-REX.R */
1380 assert_no_prefix(ins, PPS_LOCK);
1381 lockcheck = false; /* Already errored, no need for warning */
1382 length++;
1383 } else {
1384 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1385 return -1;
1386 }
1387 }
1388
1389 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1390 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1391 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1392 "instruction is not lockable");
1393 }
1394
1395 bad_hle_warn(ins, hleok);
1396
1397 /*
1398 * when BND prefix is set by DEFAULT directive,
1399 * BND prefix is added to every appropriate instruction line
1400 * unless it is overridden by NOBND prefix.
1401 */
1402 if (globalbnd &&
1403 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1404 ins->prefixes[PPS_REP] = P_BND;
1405
1406 return length;
1407 }
1408
1409 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1410 {
1411 if (bits == 64) {
1412 if ((ins->rex & REX_MASK) &&
1413 !(ins->rex & (REX_V | REX_EV)) &&
1414 !ins->rex_done) {
1415 int rex = (ins->rex & REX_MASK) | REX_P;
1416 out(offset, segment, &rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1417 ins->rex_done = true;
1418 return 1;
1419 }
1420 }
1421
1422 return 0;
1423 }
1424
1425 static void gencode(int32_t segment, int64_t offset, int bits,
1426 insn * ins, const struct itemplate *temp,
1427 int64_t insn_end)
1428 {
1429 uint8_t c;
1430 uint8_t bytes[4];
1431 int64_t size;
1432 int64_t data;
1433 int op1, op2;
1434 struct operand *opx;
1435 const uint8_t *codes = temp->code;
1436 uint8_t opex = 0;
1437 enum ea_type eat = EA_SCALAR;
1438 int r;
1439
1440 ins->rex_done = false;
1441
1442 while (*codes) {
1443 c = *codes++;
1444 op1 = (c & 3) + ((opex & 1) << 2);
1445 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1446 opx = &ins->oprs[op1];
1447 opex = 0; /* For the next iteration */
1448
1449 switch (c) {
1450 case 01:
1451 case 02:
1452 case 03:
1453 case 04:
1454 offset += emit_rex(ins, segment, offset, bits);
1455 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1456 codes += c;
1457 offset += c;
1458 break;
1459
1460 case 05:
1461 case 06:
1462 case 07:
1463 opex = c;
1464 break;
1465
1466 case4(010):
1467 offset += emit_rex(ins, segment, offset, bits);
1468 bytes[0] = *codes++ + (regval(opx) & 7);
1469 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1470 offset += 1;
1471 break;
1472
1473 case4(014):
1474 break;
1475
1476 case4(020):
1477 if (opx->offset < -256 || opx->offset > 255) {
1478 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1479 "byte value exceeds bounds");
1480 }
1481 out_imm8(offset, segment, opx, -1);
1482 offset += 1;
1483 break;
1484
1485 case4(024):
1486 if (opx->offset < 0 || opx->offset > 255)
1487 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1488 "unsigned byte value exceeds bounds");
1489 out_imm8(offset, segment, opx, 1);
1490 offset += 1;
1491 break;
1492
1493 case4(030):
1494 warn_overflow_opd(opx, 2);
1495 data = opx->offset;
1496 out(offset, segment, &data, OUT_ADDRESS, 2,
1497 opx->segment, opx->wrt);
1498 offset += 2;
1499 break;
1500
1501 case4(034):
1502 if (opx->type & (BITS16 | BITS32))
1503 size = (opx->type & BITS16) ? 2 : 4;
1504 else
1505 size = (bits == 16) ? 2 : 4;
1506 warn_overflow_opd(opx, size);
1507 data = opx->offset;
1508 out(offset, segment, &data, OUT_ADDRESS, size,
1509 opx->segment, opx->wrt);
1510 offset += size;
1511 break;
1512
1513 case4(040):
1514 warn_overflow_opd(opx, 4);
1515 data = opx->offset;
1516 out(offset, segment, &data, OUT_ADDRESS, 4,
1517 opx->segment, opx->wrt);
1518 offset += 4;
1519 break;
1520
1521 case4(044):
1522 data = opx->offset;
1523 size = ins->addr_size >> 3;
1524 warn_overflow_opd(opx, size);
1525 out(offset, segment, &data, OUT_ADDRESS, size,
1526 opx->segment, opx->wrt);
1527 offset += size;
1528 break;
1529
1530 case4(050):
1531 if (opx->segment != segment) {
1532 data = opx->offset;
1533 out(offset, segment, &data,
1534 OUT_REL1ADR, insn_end - offset,
1535 opx->segment, opx->wrt);
1536 } else {
1537 data = opx->offset - insn_end;
1538 if (data > 127 || data < -128)
1539 nasm_error(ERR_NONFATAL, "short jump is out of range");
1540 out(offset, segment, &data,
1541 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1542 }
1543 offset += 1;
1544 break;
1545
1546 case4(054):
1547 data = (int64_t)opx->offset;
1548 out(offset, segment, &data, OUT_ADDRESS, 8,
1549 opx->segment, opx->wrt);
1550 offset += 8;
1551 break;
1552
1553 case4(060):
1554 if (opx->segment != segment) {
1555 data = opx->offset;
1556 out(offset, segment, &data,
1557 OUT_REL2ADR, insn_end - offset,
1558 opx->segment, opx->wrt);
1559 } else {
1560 data = opx->offset - insn_end;
1561 out(offset, segment, &data,
1562 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1563 }
1564 offset += 2;
1565 break;
1566
1567 case4(064):
1568 if (opx->type & (BITS16 | BITS32 | BITS64))
1569 size = (opx->type & BITS16) ? 2 : 4;
1570 else
1571 size = (bits == 16) ? 2 : 4;
1572 if (opx->segment != segment) {
1573 data = opx->offset;
1574 out(offset, segment, &data,
1575 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1576 insn_end - offset, opx->segment, opx->wrt);
1577 } else {
1578 data = opx->offset - insn_end;
1579 out(offset, segment, &data,
1580 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1581 }
1582 offset += size;
1583 break;
1584
1585 case4(070):
1586 if (opx->segment != segment) {
1587 data = opx->offset;
1588 out(offset, segment, &data,
1589 OUT_REL4ADR, insn_end - offset,
1590 opx->segment, opx->wrt);
1591 } else {
1592 data = opx->offset - insn_end;
1593 out(offset, segment, &data,
1594 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1595 }
1596 offset += 4;
1597 break;
1598
1599 case4(074):
1600 if (opx->segment == NO_SEG)
1601 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1602 " relocatable");
1603 data = 0;
1604 out(offset, segment, &data, OUT_ADDRESS, 2,
1605 ofmt->segbase(1 + opx->segment),
1606 opx->wrt);
1607 offset += 2;
1608 break;
1609
1610 case 0172:
1611 {
1612 int mask = ins->prefixes[PPS_VEX] == P_EVEX ? 7 : 15;
1613 const struct operand *opy;
1614
1615 c = *codes++;
1616 opx = &ins->oprs[c >> 3];
1617 opy = &ins->oprs[c & 7];
1618 if (opy->segment != NO_SEG || opy->wrt != NO_SEG) {
1619 nasm_error(ERR_NONFATAL,
1620 "non-absolute expression not permitted as argument %d",
1621 c & 7);
1622 } else if (opy->offset & ~mask) {
1623 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1624 "is4 argument exceeds bounds");
1625 }
1626 c = opy->offset & mask;
1627 goto emit_is4;
1628 }
1629
1630 case 0173:
1631 c = *codes++;
1632 opx = &ins->oprs[c >> 4];
1633 c &= 15;
1634 goto emit_is4;
1635
1636 case4(0174):
1637 c = 0;
1638 emit_is4:
1639 r = nasm_regvals[opx->basereg];
1640 bytes[0] = (r << 4) | ((r & 0x10) >> 1) | c;
1641 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1642 offset++;
1643 break;
1644
1645 case4(0254):
1646 data = opx->offset;
1647 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1648 (int32_t)data != (int64_t)data) {
1649 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1650 "signed dword immediate exceeds bounds");
1651 }
1652 out(offset, segment, &data, OUT_ADDRESS, -4,
1653 opx->segment, opx->wrt);
1654 offset += 4;
1655 break;
1656
1657 case4(0240):
1658 case 0250:
1659 codes += 3;
1660 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1661 EVEX_P2Z | EVEX_P2AAA, 2);
1662 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1663 bytes[0] = 0x62;
1664 /* EVEX.X can be set by either REX or EVEX for different reasons */
1665 bytes[1] = ((((ins->rex & 7) << 5) |
1666 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1667 (ins->vex_cm & 3);
1668 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1669 ((~ins->vexreg & 15) << 3) |
1670 (1 << 2) | (ins->vex_wlp & 3);
1671 bytes[3] = ins->evex_p[2];
1672 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1673 offset += 4;
1674 break;
1675
1676 case4(0260):
1677 case 0270:
1678 codes += 2;
1679 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1680 ins->prefixes[PPS_VEX] == P_VEX3) {
1681 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1682 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1683 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1684 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1685 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1686 offset += 3;
1687 } else {
1688 bytes[0] = 0xc5;
1689 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1690 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1691 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1692 offset += 2;
1693 }
1694 break;
1695
1696 case 0271:
1697 case 0272:
1698 case 0273:
1699 break;
1700
1701 case4(0274):
1702 {
1703 uint64_t uv, um;
1704 int s;
1705
1706 if (ins->rex & REX_W)
1707 s = 64;
1708 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1709 s = 16;
1710 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1711 s = 32;
1712 else
1713 s = bits;
1714
1715 um = (uint64_t)2 << (s-1);
1716 uv = opx->offset;
1717
1718 if (uv > 127 && uv < (uint64_t)-128 &&
1719 (uv < um-128 || uv > um-1)) {
1720 /* If this wasn't explicitly byte-sized, warn as though we
1721 * had fallen through to the imm16/32/64 case.
1722 */
1723 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1724 "%s value exceeds bounds",
1725 (opx->type & BITS8) ? "signed byte" :
1726 s == 16 ? "word" :
1727 s == 32 ? "dword" :
1728 "signed dword");
1729 }
1730 if (opx->segment != NO_SEG) {
1731 data = uv;
1732 out(offset, segment, &data, OUT_ADDRESS, 1,
1733 opx->segment, opx->wrt);
1734 } else {
1735 bytes[0] = uv;
1736 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1737 NO_SEG);
1738 }
1739 offset += 1;
1740 break;
1741 }
1742
1743 case4(0300):
1744 break;
1745
1746 case 0310:
1747 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1748 *bytes = 0x67;
1749 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1750 offset += 1;
1751 } else
1752 offset += 0;
1753 break;
1754
1755 case 0311:
1756 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1757 *bytes = 0x67;
1758 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1759 offset += 1;
1760 } else
1761 offset += 0;
1762 break;
1763
1764 case 0312:
1765 break;
1766
1767 case 0313:
1768 ins->rex = 0;
1769 break;
1770
1771 case4(0314):
1772 break;
1773
1774 case 0320:
1775 case 0321:
1776 break;
1777
1778 case 0322:
1779 case 0323:
1780 break;
1781
1782 case 0324:
1783 ins->rex |= REX_W;
1784 break;
1785
1786 case 0325:
1787 break;
1788
1789 case 0326:
1790 break;
1791
1792 case 0330:
1793 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1794 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1795 offset += 1;
1796 break;
1797
1798 case 0331:
1799 break;
1800
1801 case 0332:
1802 case 0333:
1803 *bytes = c - 0332 + 0xF2;
1804 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1805 offset += 1;
1806 break;
1807
1808 case 0334:
1809 if (ins->rex & REX_R) {
1810 *bytes = 0xF0;
1811 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1812 offset += 1;
1813 }
1814 ins->rex &= ~(REX_L|REX_R);
1815 break;
1816
1817 case 0335:
1818 break;
1819
1820 case 0336:
1821 case 0337:
1822 break;
1823
1824 case 0340:
1825 if (ins->oprs[0].segment != NO_SEG)
1826 nasm_panic(0, "non-constant BSS size in pass two");
1827 else {
1828 int64_t size = ins->oprs[0].offset;
1829 if (size > 0)
1830 out(offset, segment, NULL,
1831 OUT_RESERVE, size, NO_SEG, NO_SEG);
1832 offset += size;
1833 }
1834 break;
1835
1836 case 0341:
1837 break;
1838
1839 case 0360:
1840 break;
1841
1842 case 0361:
1843 bytes[0] = 0x66;
1844 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1845 offset += 1;
1846 break;
1847
1848 case 0364:
1849 case 0365:
1850 break;
1851
1852 case 0366:
1853 case 0367:
1854 *bytes = c - 0366 + 0x66;
1855 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1856 offset += 1;
1857 break;
1858
1859 case3(0370):
1860 break;
1861
1862 case 0373:
1863 *bytes = bits == 16 ? 3 : 5;
1864 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1865 offset += 1;
1866 break;
1867
1868 case 0374:
1869 eat = EA_XMMVSIB;
1870 break;
1871
1872 case 0375:
1873 eat = EA_YMMVSIB;
1874 break;
1875
1876 case 0376:
1877 eat = EA_ZMMVSIB;
1878 break;
1879
1880 case4(0100):
1881 case4(0110):
1882 case4(0120):
1883 case4(0130):
1884 case4(0200):
1885 case4(0204):
1886 case4(0210):
1887 case4(0214):
1888 case4(0220):
1889 case4(0224):
1890 case4(0230):
1891 case4(0234):
1892 {
1893 ea ea_data;
1894 int rfield;
1895 opflags_t rflags;
1896 uint8_t *p;
1897 int32_t s;
1898 struct operand *opy = &ins->oprs[op2];
1899
1900 if (c <= 0177) {
1901 /* pick rfield from operand b (opx) */
1902 rflags = regflag(opx);
1903 rfield = nasm_regvals[opx->basereg];
1904 } else {
1905 /* rfield is constant */
1906 rflags = 0;
1907 rfield = c & 7;
1908 }
1909
1910 if (process_ea(opy, &ea_data, bits,
1911 rfield, rflags, ins) != eat)
1912 nasm_error(ERR_NONFATAL, "invalid effective address");
1913
1914 p = bytes;
1915 *p++ = ea_data.modrm;
1916 if (ea_data.sib_present)
1917 *p++ = ea_data.sib;
1918
1919 s = p - bytes;
1920 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1921
1922 /*
1923 * Make sure the address gets the right offset in case
1924 * the line breaks in the .lst file (BR 1197827)
1925 */
1926 offset += s;
1927 s = 0;
1928
1929 if (ea_data.bytes) {
1930 /* use compressed displacement, if available */
1931 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1932 s += ea_data.bytes;
1933 if (ea_data.rip) {
1934 if (opy->segment == segment) {
1935 data -= insn_end;
1936 if (overflow_signed(data, ea_data.bytes))
1937 warn_overflow(ERR_PASS2, ea_data.bytes);
1938 out(offset, segment, &data, OUT_ADDRESS,
1939 ea_data.bytes, NO_SEG, NO_SEG);
1940 } else {
1941 /* overflow check in output/linker? */
1942 out(offset, segment, &data, OUT_REL4ADR,
1943 insn_end - offset, opy->segment, opy->wrt);
1944 }
1945 } else {
1946 int asize = ins->addr_size >> 3;
1947 int atype = ea_data.bytes;
1948
1949 if (overflow_general(data, asize) ||
1950 signed_bits(data, ins->addr_size) !=
1951 signed_bits(data, ea_data.bytes << 3))
1952 warn_overflow(ERR_PASS2, ea_data.bytes);
1953
1954 if (asize > ea_data.bytes) {
1955 /*
1956 * If the address isn't the full width of
1957 * the address size, treat is as signed...
1958 */
1959 atype = -atype;
1960 }
1961
1962 out(offset, segment, &data, OUT_ADDRESS,
1963 atype, opy->segment, opy->wrt);
1964 }
1965 }
1966 offset += s;
1967 }
1968 break;
1969
1970 default:
1971 nasm_panic(0, "internal instruction table corrupt"
1972 ": instruction code \\%o (0x%02X) given", c, c);
1973 break;
1974 }
1975 }
1976 }
1977
1978 static opflags_t regflag(const operand * o)
1979 {
1980 if (!is_register(o->basereg))
1981 nasm_panic(0, "invalid operand passed to regflag()");
1982 return nasm_reg_flags[o->basereg];
1983 }
1984
1985 static int32_t regval(const operand * o)
1986 {
1987 if (!is_register(o->basereg))
1988 nasm_panic(0, "invalid operand passed to regval()");
1989 return nasm_regvals[o->basereg];
1990 }
1991
1992 static int op_rexflags(const operand * o, int mask)
1993 {
1994 opflags_t flags;
1995 int val;
1996
1997 if (!is_register(o->basereg))
1998 nasm_panic(0, "invalid operand passed to op_rexflags()");
1999
2000 flags = nasm_reg_flags[o->basereg];
2001 val = nasm_regvals[o->basereg];
2002
2003 return rexflags(val, flags, mask);
2004 }
2005
2006 static int rexflags(int val, opflags_t flags, int mask)
2007 {
2008 int rex = 0;
2009
2010 if (val >= 0 && (val & 8))
2011 rex |= REX_B|REX_X|REX_R;
2012 if (flags & BITS64)
2013 rex |= REX_W;
2014 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
2015 rex |= REX_H;
2016 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
2017 rex |= REX_P;
2018
2019 return rex & mask;
2020 }
2021
2022 static int evexflags(int val, decoflags_t deco,
2023 int mask, uint8_t byte)
2024 {
2025 int evex = 0;
2026
2027 switch (byte) {
2028 case 0:
2029 if (val >= 0 && (val & 16))
2030 evex |= (EVEX_P0RP | EVEX_P0X);
2031 break;
2032 case 2:
2033 if (val >= 0 && (val & 16))
2034 evex |= EVEX_P2VP;
2035 if (deco & Z)
2036 evex |= EVEX_P2Z;
2037 if (deco & OPMASK_MASK)
2038 evex |= deco & EVEX_P2AAA;
2039 break;
2040 }
2041 return evex & mask;
2042 }
2043
2044 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2045 {
2046 int val;
2047
2048 val = nasm_regvals[o->basereg];
2049
2050 return evexflags(val, o->decoflags, mask, byte);
2051 }
2052
2053 static enum match_result find_match(const struct itemplate **tempp,
2054 insn *instruction,
2055 int32_t segment, int64_t offset, int bits)
2056 {
2057 const struct itemplate *temp;
2058 enum match_result m, merr;
2059 opflags_t xsizeflags[MAX_OPERANDS];
2060 bool opsizemissing = false;
2061 int8_t broadcast = instruction->evex_brerop;
2062 int i;
2063
2064 /* broadcasting uses a different data element size */
2065 for (i = 0; i < instruction->operands; i++)
2066 if (i == broadcast)
2067 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2068 else
2069 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2070
2071 merr = MERR_INVALOP;
2072
2073 for (temp = nasm_instructions[instruction->opcode];
2074 temp->opcode != I_none; temp++) {
2075 m = matches(temp, instruction, bits);
2076 if (m == MOK_JUMP) {
2077 if (jmp_match(segment, offset, bits, instruction, temp))
2078 m = MOK_GOOD;
2079 else
2080 m = MERR_INVALOP;
2081 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2082 /*
2083 * Missing operand size and a candidate for fuzzy matching...
2084 */
2085 for (i = 0; i < temp->operands; i++)
2086 if (i == broadcast)
2087 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2088 else
2089 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2090 opsizemissing = true;
2091 }
2092 if (m > merr)
2093 merr = m;
2094 if (merr == MOK_GOOD)
2095 goto done;
2096 }
2097
2098 /* No match, but see if we can get a fuzzy operand size match... */
2099 if (!opsizemissing)
2100 goto done;
2101
2102 for (i = 0; i < instruction->operands; i++) {
2103 /*
2104 * We ignore extrinsic operand sizes on registers, so we should
2105 * never try to fuzzy-match on them. This also resolves the case
2106 * when we have e.g. "xmmrm128" in two different positions.
2107 */
2108 if (is_class(REGISTER, instruction->oprs[i].type))
2109 continue;
2110
2111 /* This tests if xsizeflags[i] has more than one bit set */
2112 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2113 goto done; /* No luck */
2114
2115 if (i == broadcast) {
2116 instruction->oprs[i].decoflags |= xsizeflags[i];
2117 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2118 BITS32 : BITS64);
2119 } else {
2120 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2121 }
2122 }
2123
2124 /* Try matching again... */
2125 for (temp = nasm_instructions[instruction->opcode];
2126 temp->opcode != I_none; temp++) {
2127 m = matches(temp, instruction, bits);
2128 if (m == MOK_JUMP) {
2129 if (jmp_match(segment, offset, bits, instruction, temp))
2130 m = MOK_GOOD;
2131 else
2132 m = MERR_INVALOP;
2133 }
2134 if (m > merr)
2135 merr = m;
2136 if (merr == MOK_GOOD)
2137 goto done;
2138 }
2139
2140 done:
2141 *tempp = temp;
2142 return merr;
2143 }
2144
2145 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2146 {
2147 opflags_t opsize = opflags & SIZE_MASK;
2148 uint8_t brcast_num;
2149
2150 /*
2151 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2152 * this cannot be a simple arithmetic calculation.
2153 */
2154 if (brsize > BITS64)
2155 nasm_error(ERR_FATAL,
2156 "size of broadcasting element is greater than 64 bits");
2157
2158 switch (opsize) {
2159 case BITS64:
2160 brcast_num = BITS64 / brsize;
2161 break;
2162 default:
2163 brcast_num = (opsize / BITS128) * (BITS64 / brsize) * 2;
2164 break;
2165 }
2166
2167 return brcast_num;
2168 }
2169
2170 static enum match_result matches(const struct itemplate *itemp,
2171 insn *instruction, int bits)
2172 {
2173 opflags_t size[MAX_OPERANDS], asize;
2174 bool opsizemissing = false;
2175 int i, oprs;
2176
2177 /*
2178 * Check the opcode
2179 */
2180 if (itemp->opcode != instruction->opcode)
2181 return MERR_INVALOP;
2182
2183 /*
2184 * Count the operands
2185 */
2186 if (itemp->operands != instruction->operands)
2187 return MERR_INVALOP;
2188
2189 /*
2190 * Is it legal?
2191 */
2192 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2193 return MERR_INVALOP;
2194
2195 /*
2196 * {evex} available?
2197 */
2198 switch (instruction->prefixes[PPS_VEX]) {
2199 case P_EVEX:
2200 if (!itemp_has(itemp, IF_EVEX))
2201 return MERR_ENCMISMATCH;
2202 break;
2203 case P_VEX3:
2204 case P_VEX2:
2205 if (!itemp_has(itemp, IF_VEX))
2206 return MERR_ENCMISMATCH;
2207 break;
2208 default:
2209 break;
2210 }
2211
2212 /*
2213 * Check that no spurious colons or TOs are present
2214 */
2215 for (i = 0; i < itemp->operands; i++)
2216 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2217 return MERR_INVALOP;
2218
2219 /*
2220 * Process size flags
2221 */
2222 switch (itemp_smask(itemp)) {
2223 case IF_GENBIT(IF_SB):
2224 asize = BITS8;
2225 break;
2226 case IF_GENBIT(IF_SW):
2227 asize = BITS16;
2228 break;
2229 case IF_GENBIT(IF_SD):
2230 asize = BITS32;
2231 break;
2232 case IF_GENBIT(IF_SQ):
2233 asize = BITS64;
2234 break;
2235 case IF_GENBIT(IF_SO):
2236 asize = BITS128;
2237 break;
2238 case IF_GENBIT(IF_SY):
2239 asize = BITS256;
2240 break;
2241 case IF_GENBIT(IF_SZ):
2242 asize = BITS512;
2243 break;
2244 case IF_GENBIT(IF_SIZE):
2245 switch (bits) {
2246 case 16:
2247 asize = BITS16;
2248 break;
2249 case 32:
2250 asize = BITS32;
2251 break;
2252 case 64:
2253 asize = BITS64;
2254 break;
2255 default:
2256 asize = 0;
2257 break;
2258 }
2259 break;
2260 default:
2261 asize = 0;
2262 break;
2263 }
2264
2265 if (itemp_armask(itemp)) {
2266 /* S- flags only apply to a specific operand */
2267 i = itemp_arg(itemp);
2268 memset(size, 0, sizeof size);
2269 size[i] = asize;
2270 } else {
2271 /* S- flags apply to all operands */
2272 for (i = 0; i < MAX_OPERANDS; i++)
2273 size[i] = asize;
2274 }
2275
2276 /*
2277 * Check that the operand flags all match up,
2278 * it's a bit tricky so lets be verbose:
2279 *
2280 * 1) Find out the size of operand. If instruction
2281 * doesn't have one specified -- we're trying to
2282 * guess it either from template (IF_S* flag) or
2283 * from code bits.
2284 *
2285 * 2) If template operand do not match the instruction OR
2286 * template has an operand size specified AND this size differ
2287 * from which instruction has (perhaps we got it from code bits)
2288 * we are:
2289 * a) Check that only size of instruction and operand is differ
2290 * other characteristics do match
2291 * b) Perhaps it's a register specified in instruction so
2292 * for such a case we just mark that operand as "size
2293 * missing" and this will turn on fuzzy operand size
2294 * logic facility (handled by a caller)
2295 */
2296 for (i = 0; i < itemp->operands; i++) {
2297 opflags_t type = instruction->oprs[i].type;
2298 decoflags_t deco = instruction->oprs[i].decoflags;
2299 bool is_broadcast = deco & BRDCAST_MASK;
2300 uint8_t brcast_num = 0;
2301 opflags_t template_opsize, insn_opsize;
2302
2303 if (!(type & SIZE_MASK))
2304 type |= size[i];
2305
2306 insn_opsize = type & SIZE_MASK;
2307 if (!is_broadcast) {
2308 template_opsize = itemp->opd[i] & SIZE_MASK;
2309 } else {
2310 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2311 /*
2312 * when broadcasting, the element size depends on
2313 * the instruction type. decorator flag should match.
2314 */
2315
2316 if (deco_brsize) {
2317 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2318 /* calculate the proper number : {1to<brcast_num>} */
2319 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2320 } else {
2321 template_opsize = 0;
2322 }
2323 }
2324
2325 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2326 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2327 return MERR_INVALOP;
2328 } else if (template_opsize) {
2329 if (template_opsize != insn_opsize) {
2330 if (insn_opsize) {
2331 return MERR_INVALOP;
2332 } else if (!is_class(REGISTER, type)) {
2333 /*
2334 * Note: we don't honor extrinsic operand sizes for registers,
2335 * so "missing operand size" for a register should be
2336 * considered a wildcard match rather than an error.
2337 */
2338 opsizemissing = true;
2339 }
2340 } else if (is_broadcast &&
2341 (brcast_num !=
2342 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2343 /*
2344 * broadcasting opsize matches but the number of repeated memory
2345 * element does not match.
2346 * if 64b double precision float is broadcasted to ymm (256b),
2347 * broadcasting decorator must be {1to4}.
2348 */
2349 return MERR_BRNUMMISMATCH;
2350 }
2351 }
2352 }
2353
2354 if (opsizemissing)
2355 return MERR_OPSIZEMISSING;
2356
2357 /*
2358 * Check operand sizes
2359 */
2360 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2361 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2362 for (i = 0; i < oprs; i++) {
2363 asize = itemp->opd[i] & SIZE_MASK;
2364 if (asize) {
2365 for (i = 0; i < oprs; i++)
2366 size[i] = asize;
2367 break;
2368 }
2369 }
2370 } else {
2371 oprs = itemp->operands;
2372 }
2373
2374 for (i = 0; i < itemp->operands; i++) {
2375 if (!(itemp->opd[i] & SIZE_MASK) &&
2376 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2377 return MERR_OPSIZEMISMATCH;
2378 }
2379
2380 /*
2381 * Check template is okay at the set cpu level
2382 */
2383 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2384 return MERR_BADCPU;
2385
2386 /*
2387 * Verify the appropriate long mode flag.
2388 */
2389 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2390 return MERR_BADMODE;
2391
2392 /*
2393 * If we have a HLE prefix, look for the NOHLE flag
2394 */
2395 if (itemp_has(itemp, IF_NOHLE) &&
2396 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2397 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2398 return MERR_BADHLE;
2399
2400 /*
2401 * Check if special handling needed for Jumps
2402 */
2403 if ((itemp->code[0] & ~1) == 0370)
2404 return MOK_JUMP;
2405
2406 /*
2407 * Check if BND prefix is allowed.
2408 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2409 */
2410 if (!itemp_has(itemp, IF_BND) &&
2411 (has_prefix(instruction, PPS_REP, P_BND) ||
2412 has_prefix(instruction, PPS_REP, P_NOBND)))
2413 return MERR_BADBND;
2414 else if (itemp_has(itemp, IF_BND) &&
2415 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2416 has_prefix(instruction, PPS_REP, P_REPNZ)))
2417 return MERR_BADREPNE;
2418
2419 return MOK_GOOD;
2420 }
2421
2422 /*
2423 * Check if ModR/M.mod should/can be 01.
2424 * - EAF_BYTEOFFS is set
2425 * - offset can fit in a byte when EVEX is not used
2426 * - offset can be compressed when EVEX is used
2427 */
2428 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2429 (o >= -128 && o <= 127 && \
2430 seg == NO_SEG && !forw_ref && \
2431 !(input->eaflags & EAF_WORDOFFS) && \
2432 !(ins->rex & REX_EV)) || \
2433 (ins->rex & REX_EV && \
2434 is_disp8n(input, ins, &output->disp8)))
2435
2436 static enum ea_type process_ea(operand *input, ea *output, int bits,
2437 int rfield, opflags_t rflags, insn *ins)
2438 {
2439 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2440 int addrbits = ins->addr_size;
2441 int eaflags = input->eaflags;
2442
2443 output->type = EA_SCALAR;
2444 output->rip = false;
2445 output->disp8 = 0;
2446
2447 /* REX flags for the rfield operand */
2448 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2449 /* EVEX.R' flag for the REG operand */
2450 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2451
2452 if (is_class(REGISTER, input->type)) {
2453 /*
2454 * It's a direct register.
2455 */
2456 if (!is_register(input->basereg))
2457 goto err;
2458
2459 if (!is_reg_class(REG_EA, input->basereg))
2460 goto err;
2461
2462 /* broadcasting is not available with a direct register operand. */
2463 if (input->decoflags & BRDCAST_MASK) {
2464 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2465 goto err;
2466 }
2467
2468 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2469 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2470 output->sib_present = false; /* no SIB necessary */
2471 output->bytes = 0; /* no offset necessary either */
2472 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2473 } else {
2474 /*
2475 * It's a memory reference.
2476 */
2477
2478 /* Embedded rounding or SAE is not available with a mem ref operand. */
2479 if (input->decoflags & (ER | SAE)) {
2480 nasm_error(ERR_NONFATAL,
2481 "Embedded rounding is available only with reg-reg op.");
2482 return -1;
2483 }
2484
2485 if (input->basereg == -1 &&
2486 (input->indexreg == -1 || input->scale == 0)) {
2487 /*
2488 * It's a pure offset.
2489 */
2490 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2491 input->segment == NO_SEG) {
2492 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2493 input->type &= ~IP_REL;
2494 input->type |= MEMORY;
2495 }
2496
2497 if (bits == 64 &&
2498 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2499 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2500 return -1;
2501 }
2502
2503 if (eaflags & EAF_BYTEOFFS ||
2504 (eaflags & EAF_WORDOFFS &&
2505 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2506 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2507 }
2508
2509 if (bits == 64 && (~input->type & IP_REL)) {
2510 output->sib_present = true;
2511 output->sib = GEN_SIB(0, 4, 5);
2512 output->bytes = 4;
2513 output->modrm = GEN_MODRM(0, rfield, 4);
2514 output->rip = false;
2515 } else {
2516 output->sib_present = false;
2517 output->bytes = (addrbits != 16 ? 4 : 2);
2518 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2519 output->rip = bits == 64;
2520 }
2521 } else {
2522 /*
2523 * It's an indirection.
2524 */
2525 int i = input->indexreg, b = input->basereg, s = input->scale;
2526 int32_t seg = input->segment;
2527 int hb = input->hintbase, ht = input->hinttype;
2528 int t, it, bt; /* register numbers */
2529 opflags_t x, ix, bx; /* register flags */
2530
2531 if (s == 0)
2532 i = -1; /* make this easy, at least */
2533
2534 if (is_register(i)) {
2535 it = nasm_regvals[i];
2536 ix = nasm_reg_flags[i];
2537 } else {
2538 it = -1;
2539 ix = 0;
2540 }
2541
2542 if (is_register(b)) {
2543 bt = nasm_regvals[b];
2544 bx = nasm_reg_flags[b];
2545 } else {
2546 bt = -1;
2547 bx = 0;
2548 }
2549
2550 /* if either one are a vector register... */
2551 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2552 opflags_t sok = BITS32 | BITS64;
2553 int32_t o = input->offset;
2554 int mod, scale, index, base;
2555
2556 /*
2557 * For a vector SIB, one has to be a vector and the other,
2558 * if present, a GPR. The vector must be the index operand.
2559 */
2560 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2561 if (s == 0)
2562 s = 1;
2563 else if (s != 1)
2564 goto err;
2565
2566 t = bt, bt = it, it = t;
2567 x = bx, bx = ix, ix = x;
2568 }
2569
2570 if (bt != -1) {
2571 if (REG_GPR & ~bx)
2572 goto err;
2573 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2574 sok &= bx;
2575 else
2576 goto err;
2577 }
2578
2579 /*
2580 * While we're here, ensure the user didn't specify
2581 * WORD or QWORD
2582 */
2583 if (input->disp_size == 16 || input->disp_size == 64)
2584 goto err;
2585
2586 if (addrbits == 16 ||
2587 (addrbits == 32 && !(sok & BITS32)) ||
2588 (addrbits == 64 && !(sok & BITS64)))
2589 goto err;
2590
2591 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2592 : ((ix & YMMREG & ~REG_EA)
2593 ? EA_YMMVSIB : EA_XMMVSIB));
2594
2595 output->rex |= rexflags(it, ix, REX_X);
2596 output->rex |= rexflags(bt, bx, REX_B);
2597 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2598
2599 index = it & 7; /* it is known to be != -1 */
2600
2601 switch (s) {
2602 case 1:
2603 scale = 0;
2604 break;
2605 case 2:
2606 scale = 1;
2607 break;
2608 case 4:
2609 scale = 2;
2610 break;
2611 case 8:
2612 scale = 3;
2613 break;
2614 default: /* then what the smeg is it? */
2615 goto err; /* panic */
2616 }
2617
2618 if (bt == -1) {
2619 base = 5;
2620 mod = 0;
2621 } else {
2622 base = (bt & 7);
2623 if (base != REG_NUM_EBP && o == 0 &&
2624 seg == NO_SEG && !forw_ref &&
2625 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2626 mod = 0;
2627 else if (IS_MOD_01())
2628 mod = 1;
2629 else
2630 mod = 2;
2631 }
2632
2633 output->sib_present = true;
2634 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2635 output->modrm = GEN_MODRM(mod, rfield, 4);
2636 output->sib = GEN_SIB(scale, index, base);
2637 } else if ((ix|bx) & (BITS32|BITS64)) {
2638 /*
2639 * it must be a 32/64-bit memory reference. Firstly we have
2640 * to check that all registers involved are type E/Rxx.
2641 */
2642 opflags_t sok = BITS32 | BITS64;
2643 int32_t o = input->offset;
2644
2645 if (it != -1) {
2646 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2647 sok &= ix;
2648 else
2649 goto err;
2650 }
2651
2652 if (bt != -1) {
2653 if (REG_GPR & ~bx)
2654 goto err; /* Invalid register */
2655 if (~sok & bx & SIZE_MASK)
2656 goto err; /* Invalid size */
2657 sok &= bx;
2658 }
2659
2660 /*
2661 * While we're here, ensure the user didn't specify
2662 * WORD or QWORD
2663 */
2664 if (input->disp_size == 16 || input->disp_size == 64)
2665 goto err;
2666
2667 if (addrbits == 16 ||
2668 (addrbits == 32 && !(sok & BITS32)) ||
2669 (addrbits == 64 && !(sok & BITS64)))
2670 goto err;
2671
2672 /* now reorganize base/index */
2673 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2674 ((hb == b && ht == EAH_NOTBASE) ||
2675 (hb == i && ht == EAH_MAKEBASE))) {
2676 /* swap if hints say so */
2677 t = bt, bt = it, it = t;
2678 x = bx, bx = ix, ix = x;
2679 }
2680
2681 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2682 /* make single reg base, unless hint */
2683 bt = it, bx = ix, it = -1, ix = 0;
2684 }
2685 if (eaflags & EAF_MIB) {
2686 /* only for mib operands */
2687 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2688 /*
2689 * make a single reg index [reg*1].
2690 * gas uses this form for an explicit index register.
2691 */
2692 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2693 }
2694 if ((ht == EAH_SUMMED) && bt == -1) {
2695 /* separate once summed index into [base, index] */
2696 bt = it, bx = ix, s--;
2697 }
2698 } else {
2699 if (((s == 2 && it != REG_NUM_ESP &&
2700 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2701 s == 3 || s == 5 || s == 9) && bt == -1) {
2702 /* convert 3*EAX to EAX+2*EAX */
2703 bt = it, bx = ix, s--;
2704 }
2705 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2706 (eaflags & EAF_TIMESTWO) &&
2707 (hb == b && ht == EAH_NOTBASE)) {
2708 /*
2709 * convert [NOSPLIT EAX*1]
2710 * to sib format with 0x0 displacement - [EAX*1+0].
2711 */
2712 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2713 }
2714 }
2715 if (s == 1 && it == REG_NUM_ESP) {
2716 /* swap ESP into base if scale is 1 */
2717 t = it, it = bt, bt = t;
2718 x = ix, ix = bx, bx = x;
2719 }
2720 if (it == REG_NUM_ESP ||
2721 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2722 goto err; /* wrong, for various reasons */
2723
2724 output->rex |= rexflags(it, ix, REX_X);
2725 output->rex |= rexflags(bt, bx, REX_B);
2726
2727 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2728 /* no SIB needed */
2729 int mod, rm;
2730
2731 if (bt == -1) {
2732 rm = 5;
2733 mod = 0;
2734 } else {
2735 rm = (bt & 7);
2736 if (rm != REG_NUM_EBP && o == 0 &&
2737 seg == NO_SEG && !forw_ref &&
2738 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2739 mod = 0;
2740 else if (IS_MOD_01())
2741 mod = 1;
2742 else
2743 mod = 2;
2744 }
2745
2746 output->sib_present = false;
2747 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2748 output->modrm = GEN_MODRM(mod, rfield, rm);
2749 } else {
2750 /* we need a SIB */
2751 int mod, scale, index, base;
2752
2753 if (it == -1)
2754 index = 4, s = 1;
2755 else
2756 index = (it & 7);
2757
2758 switch (s) {
2759 case 1:
2760 scale = 0;
2761 break;
2762 case 2:
2763 scale = 1;
2764 break;
2765 case 4:
2766 scale = 2;
2767 break;
2768 case 8:
2769 scale = 3;
2770 break;
2771 default: /* then what the smeg is it? */
2772 goto err; /* panic */
2773 }
2774
2775 if (bt == -1) {
2776 base = 5;
2777 mod = 0;
2778 } else {
2779 base = (bt & 7);
2780 if (base != REG_NUM_EBP && o == 0 &&
2781 seg == NO_SEG && !forw_ref &&
2782 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2783 mod = 0;
2784 else if (IS_MOD_01())
2785 mod = 1;
2786 else
2787 mod = 2;
2788 }
2789
2790 output->sib_present = true;
2791 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2792 output->modrm = GEN_MODRM(mod, rfield, 4);
2793 output->sib = GEN_SIB(scale, index, base);
2794 }
2795 } else { /* it's 16-bit */
2796 int mod, rm;
2797 int16_t o = input->offset;
2798
2799 /* check for 64-bit long mode */
2800 if (addrbits == 64)
2801 goto err;
2802
2803 /* check all registers are BX, BP, SI or DI */
2804 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2805 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2806 goto err;
2807
2808 /* ensure the user didn't specify DWORD/QWORD */
2809 if (input->disp_size == 32 || input->disp_size == 64)
2810 goto err;
2811
2812 if (s != 1 && i != -1)
2813 goto err; /* no can do, in 16-bit EA */
2814 if (b == -1 && i != -1) {
2815 int tmp = b;
2816 b = i;
2817 i = tmp;
2818 } /* swap */
2819 if ((b == R_SI || b == R_DI) && i != -1) {
2820 int tmp = b;
2821 b = i;
2822 i = tmp;
2823 }
2824 /* have BX/BP as base, SI/DI index */
2825 if (b == i)
2826 goto err; /* shouldn't ever happen, in theory */
2827 if (i != -1 && b != -1 &&
2828 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2829 goto err; /* invalid combinations */
2830 if (b == -1) /* pure offset: handled above */
2831 goto err; /* so if it gets to here, panic! */
2832
2833 rm = -1;
2834 if (i != -1)
2835 switch (i * 256 + b) {
2836 case R_SI * 256 + R_BX:
2837 rm = 0;
2838 break;
2839 case R_DI * 256 + R_BX:
2840 rm = 1;
2841 break;
2842 case R_SI * 256 + R_BP:
2843 rm = 2;
2844 break;
2845 case R_DI * 256 + R_BP:
2846 rm = 3;
2847 break;
2848 } else
2849 switch (b) {
2850 case R_SI:
2851 rm = 4;
2852 break;
2853 case R_DI:
2854 rm = 5;
2855 break;
2856 case R_BP:
2857 rm = 6;
2858 break;
2859 case R_BX:
2860 rm = 7;
2861 break;
2862 }
2863 if (rm == -1) /* can't happen, in theory */
2864 goto err; /* so panic if it does */
2865
2866 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2867 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2868 mod = 0;
2869 else if (IS_MOD_01())
2870 mod = 1;
2871 else
2872 mod = 2;
2873
2874 output->sib_present = false; /* no SIB - it's 16-bit */
2875 output->bytes = mod; /* bytes of offset needed */
2876 output->modrm = GEN_MODRM(mod, rfield, rm);
2877 }
2878 }
2879 }
2880
2881 output->size = 1 + output->sib_present + output->bytes;
2882 return output->type;
2883
2884 err:
2885 return output->type = EA_INVALID;
2886 }
2887
2888 static void add_asp(insn *ins, int addrbits)
2889 {
2890 int j, valid;
2891 int defdisp;
2892
2893 valid = (addrbits == 64) ? 64|32 : 32|16;
2894
2895 switch (ins->prefixes[PPS_ASIZE]) {
2896 case P_A16:
2897 valid &= 16;
2898 break;
2899 case P_A32:
2900 valid &= 32;
2901 break;
2902 case P_A64:
2903 valid &= 64;
2904 break;
2905 case P_ASP:
2906 valid &= (addrbits == 32) ? 16 : 32;
2907 break;
2908 default:
2909 break;
2910 }
2911
2912 for (j = 0; j < ins->operands; j++) {
2913 if (is_class(MEMORY, ins->oprs[j].type)) {
2914 opflags_t i, b;
2915
2916 /* Verify as Register */
2917 if (!is_register(ins->oprs[j].indexreg))
2918 i = 0;
2919 else
2920 i = nasm_reg_flags[ins->oprs[j].indexreg];
2921
2922 /* Verify as Register */
2923 if (!is_register(ins->oprs[j].basereg))
2924 b = 0;
2925 else
2926 b = nasm_reg_flags[ins->oprs[j].basereg];
2927
2928 if (ins->oprs[j].scale == 0)
2929 i = 0;
2930
2931 if (!i && !b) {
2932 int ds = ins->oprs[j].disp_size;
2933 if ((addrbits != 64 && ds > 8) ||
2934 (addrbits == 64 && ds == 16))
2935 valid &= ds;
2936 } else {
2937 if (!(REG16 & ~b))
2938 valid &= 16;
2939 if (!(REG32 & ~b))
2940 valid &= 32;
2941 if (!(REG64 & ~b))
2942 valid &= 64;
2943
2944 if (!(REG16 & ~i))
2945 valid &= 16;
2946 if (!(REG32 & ~i))
2947 valid &= 32;
2948 if (!(REG64 & ~i))
2949 valid &= 64;
2950 }
2951 }
2952 }
2953
2954 if (valid & addrbits) {
2955 ins->addr_size = addrbits;
2956 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2957 /* Add an address size prefix */
2958 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2959 ins->addr_size = (addrbits == 32) ? 16 : 32;
2960 } else {
2961 /* Impossible... */
2962 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2963 ins->addr_size = addrbits; /* Error recovery */
2964 }
2965
2966 defdisp = ins->addr_size == 16 ? 16 : 32;
2967
2968 for (j = 0; j < ins->operands; j++) {
2969 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2970 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2971 /*
2972 * mem_offs sizes must match the address size; if not,
2973 * strip the MEM_OFFS bit and match only EA instructions
2974 */
2975 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2976 }
2977 }
2978 }
The Netwide Assembler