firmware/export/pp5020.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2004 by Thom Johansen
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __PP5020_H__
  22 #define __PP5020_H__
  23
  24 /* All info gleaned and/or copied from the iPodLinux project. */
  25
  26 #define QHARRAY_ATTR   __attribute__((section(".qharray"),nocommon))
  27
  28 /* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */
  29 #define DRAM_START       0x10000000
  30
  31 /* Processor ID */
  32 #define PROCESSOR_ID     (*(volatile unsigned long *)(0x60000000))
  33
  34 #define PROC_ID_CPU      0x55
  35 #define PROC_ID_COP      0xaa
  36
  37 /* Mailboxes */
  38 #define MBX_BASE            (0x60001000)
  39 /* Read bits in the mailbox */
  40 #define MBX_MSG_STAT        (*(volatile unsigned long *)(0x60001000))
  41 /* Set bits in the mailbox */
  42 #define MBX_MSG_SET         (*(volatile unsigned long *)(0x60001004))
  43 /* Clear bits in the mailbox */
  44 #define MBX_MSG_CLR         (*(volatile unsigned long *)(0x60001008))
  45 /* Doesn't seem to be COP_REPLY at all :) */
  46 #define MBX_UNKNOWN1        (*(volatile unsigned long *)(0x6000100c))
  47 /* COP can set bit 29 - only CPU read clears it */
  48 #define CPU_QUEUE           (*(volatile unsigned long *)(0x60001010))
  49 /* CPU can set bit 29 - only COP read clears it */
  50 #define COP_QUEUE           (*(volatile unsigned long *)(0x60001020))
  51
  52 #define PROC_QUEUE(core)    ((&CPU_QUEUE)[(core)*4])
  53
  54 /* Interrupts */
  55 #define CPU_INT_STAT        (*(volatile unsigned long*)(0x60004000))
  56 #define COP_INT_STAT        (*(volatile unsigned long*)(0x60004004))
  57 #define CPU_FIQ_STAT        (*(volatile unsigned long*)(0x60004008))
  58 #define COP_FIQ_STAT        (*(volatile unsigned long*)(0x6000400c))
  59
  60 #define INT_STAT            (*(volatile unsigned long*)(0x60004010))
  61 #define INT_FORCED_STAT     (*(volatile unsigned long*)(0x60004014))
  62 #define INT_FORCED_SET      (*(volatile unsigned long*)(0x60004018))
  63 #define INT_FORCED_CLR      (*(volatile unsigned long*)(0x6000401c))
  64
  65 #define CPU_INT_EN_STAT     (*(volatile unsigned long*)(0x60004020))
  66 #define CPU_INT_EN          (*(volatile unsigned long*)(0x60004024))
  67 #define CPU_INT_DIS         (*(volatile unsigned long*)(0x60004028))
  68 #define CPU_INT_PRIORITY    (*(volatile unsigned long*)(0x6000402c))
  69
  70 #define COP_INT_EN_STAT     (*(volatile unsigned long*)(0x60004030))
  71 #define COP_INT_EN          (*(volatile unsigned long*)(0x60004034))
  72 #define COP_INT_DIS         (*(volatile unsigned long*)(0x60004038))
  73 #define COP_INT_PRIORITY    (*(volatile unsigned long*)(0x6000403c))
  74
  75 #define CPU_HI_INT_STAT     (*(volatile unsigned long*)(0x60004100))
  76 #define COP_HI_INT_STAT     (*(volatile unsigned long*)(0x60004104))
  77 #define CPU_HI_FIQ_STAT     (*(volatile unsigned long*)(0x60004108))
  78 #define COP_HI_FIQ_STAT     (*(volatile unsigned long*)(0x6000410c))
  79
  80 #define HI_INT_STAT         (*(volatile unsigned long*)(0x60004110))
  81 #define HI_INT_FORCED_STAT  (*(volatile unsigned long*)(0x60004114))
  82 #define HI_INT_FORCED_SET   (*(volatile unsigned long*)(0x60004118))
  83 #define HI_INT_FORCED_CLR   (*(volatile unsigned long*)(0x6000411c))
  84
  85 #define CPU_HI_INT_EN_STAT  (*(volatile unsigned long*)(0x60004120))
  86 #define CPU_HI_INT_EN       (*(volatile unsigned long*)(0x60004124))
  87 #define CPU_HI_INT_DIS      (*(volatile unsigned long*)(0x60004128))
  88 #define CPU_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000412c))
  89
  90 #define COP_HI_INT_EN_STAT  (*(volatile unsigned long*)(0x60004130))
  91 #define COP_HI_INT_EN       (*(volatile unsigned long*)(0x60004134))
  92 #define COP_HI_INT_DIS      (*(volatile unsigned long*)(0x60004138))
  93 #define COP_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000413c))
  94
  95 #define TIMER1_IRQ   0
  96 #define TIMER2_IRQ   1
  97 #define MAILBOX_IRQ  4
  98 #define IIS_IRQ      10
  99 #define USB_IRQ      20
 100 #define IDE_IRQ      23
 101 #define FIREWIRE_IRQ 25
 102 #define HI_IRQ       30
 103 #define GPIO0_IRQ    (32+0) /* Ports A..D */
 104 #define GPIO1_IRQ    (32+1) /* Ports E..H */
 105 #define GPIO2_IRQ    (32+2) /* Ports I..L */
 106 #define SER0_IRQ     (32+4)
 107 #define SER1_IRQ     (32+5)
 108 #define I2C_IRQ      (32+8)
 109
 110 #define TIMER1_MASK   (1 << TIMER1_IRQ)
 111 #define TIMER2_MASK   (1 << TIMER2_IRQ)
 112 #define MAILBOX_MASK  (1 << MAILBOX_IRQ)
 113 #define IIS_MASK      (1 << IIS_IRQ)
 114 #define IDE_MASK      (1 << IDE_IRQ)
 115 #define USB_MASK      (1 << USB_IRQ)
 116 #define FIREWIRE_MASK (1 << FIREWIRE_IRQ)
 117 #define HI_MASK       (1 << HI_IRQ)
 118 #define GPIO0_MASK    (1 << (GPIO0_IRQ-32))
 119 #define GPIO1_MASK    (1 << (GPIO1_IRQ-32))
 120 #define GPIO2_MASK    (1 << (GPIO2_IRQ-32))
 121 #define SER0_MASK     (1 << (SER0_IRQ-32))
 122 #define SER1_MASK     (1 << (SER1_IRQ-32))
 123 #define I2C_MASK      (1 << (I2C_IRQ-32))
 124
 125 /* Timers */
 126 #define TIMER1_CFG   (*(volatile unsigned long *)(0x60005000))
 127 #define TIMER1_VAL   (*(volatile unsigned long *)(0x60005004))
 128 #define TIMER2_CFG   (*(volatile unsigned long *)(0x60005008))
 129 #define TIMER2_VAL   (*(volatile unsigned long *)(0x6000500c))
 130 #define USEC_TIMER   (*(volatile unsigned long *)(0x60005010))
 131 #define RTC          (*(volatile unsigned long *)(0x60005014))
 132
 133 /* Device Controller */
 134 #define DEV_RS       (*(volatile unsigned long *)(0x60006004))
 135 #define DEV_RS2      (*(volatile unsigned long *)(0x60006008))
 136 #define DEV_EN       (*(volatile unsigned long *)(0x6000600c))
 137 #define DEV_EN2      (*(volatile unsigned long *)(0x60006010))
 138
 139 #define DEV_EXTCLOCKS   0x00000002
 140 #define DEV_SYSTEM      0x00000004
 141 #define DEV_USB0        0x00000008
 142 #define DEV_SER0        0x00000040
 143 #define DEV_SER1        0x00000080
 144 #define DEV_I2S         0x00000800
 145 #define DEV_I2C         0x00001000
 146 #define DEV_ATA         0x00004000
 147 #define DEV_OPTO        0x00010000
 148 #define DEV_PIEZO       0x00010000
 149 #define DEV_PWM         0x00020000
 150 #define DEV_USB1        0x00400000
 151 #define DEV_FIREWIRE    0x00800000
 152 #define DEV_IDE0        0x02000000
 153 #define DEV_LCD         0x04000000
 154
 155 /* clock control */
 156 #define CLOCK_SOURCE    (*(volatile unsigned long *)(0x60006020))
 157 #define MLCD_SCLK_DIV   (*(volatile unsigned long *)(0x6000602c))
 158         /* bits 0..1: Mono LCD bridge serial clock divider: 1 / (n+1) */
 159 #define PLL_CONTROL     (*(volatile unsigned long *)(0x60006034))
 160 #define PLL_STATUS      (*(volatile unsigned long *)(0x6000603c))
 161 #define ADC_CLOCK_SRC   (*(volatile unsigned long *)(0x60006094))
 162 #define CLCD_CLOCK_SRC  (*(volatile unsigned long *)(0x600060a0))
 163
 164 /* Processors Control */
 165 #define CPU_CTL          (*(volatile unsigned long *)(0x60007000))
 166 #define COP_CTL          (*(volatile unsigned long *)(0x60007004))
 167 #define PROC_CTL(core)   ((&CPU_CTL)[core])
 168
 169 /* Control flags, can be ORed together */
 170 #define PROC_SLEEP     0x80000000  /* Sleep until an interrupt occurs */
 171 #define PROC_WAIT_CNT  0x40000000  /* Sleep until end of countdown */
 172 #define PROC_WAKE_INT  0x20000000  /* Fire interrupt on wake-up. Auto-clears. */
 173
 174 /* Counter source, select one */
 175 #define PROC_CNT_CLKS  0x08000000  /* Clock cycles */
 176 #define PROC_CNT_USEC  0x02000000  /* Microseconds */
 177 #define PROC_CNT_MSEC  0x01000000  /* Milliseconds */
 178 #define PROC_CNT_SEC   0x00800000  /* Seconds. Works on PP5022+ only! */
 179
 180 #define PROC_WAKE      0x00000000
 181
 182 /**
 183  * [22:8] - Semaphore flags for core communication? No execution effect observed
 184  *          [11:8] seem to often be set to the core's own ID
 185  *                 nybble when sleeping - 0x5 or 0xa.
 186  *  [7:0] - W: number of cycles to skip on next instruction
 187  *          R: cycles remaining
 188  * Executing on CPU
 189  *   CPU_CTL = 0x68000080
 190  *   nop
 191  * stalls the nop for 128 cycles
 192  * Reading CPU_CTL after the nop will return 0x48000000
 193  */
 194
 195
 196 /* Cache Control */
 197 #define CACHE_PRIORITY   (*(volatile unsigned long *)(0x60006044))
 198 #define CACHE_CTL        (*(volatile unsigned long *)(0x6000c000))
 199 #define CACHE_MASK       (*(volatile unsigned long *)(0xf000f040))
 200 #define CACHE_OPERATION  (*(volatile unsigned long *)(0xf000f044))
 201 #define CACHE_FLUSH_MASK (*(volatile unsigned long *)(0xf000f048))
 202
 203 /* CACHE_CTL bits */
 204 #define CACHE_CTL_DISABLE    0x0000
 205 #define CACHE_CTL_ENABLE     0x0001
 206 #define CACHE_CTL_RUN        0x0002
 207 #define CACHE_CTL_INIT       0x0004
 208 #define CACHE_CTL_VECT_REMAP 0x0010
 209 #define CACHE_CTL_READY      0x4000
 210 #define CACHE_CTL_BUSY       0x8000
 211 /* CACHE_OPERATION bits */
 212 #define CACHE_OP_FLUSH       0x0002
 213 #define CACHE_OP_INVALIDATE  0x0004
 214
 215 /* GPIO Ports */
 216 #define GPIOA_ENABLE     (*(volatile unsigned long *)(0x6000d000))
 217 #define GPIOB_ENABLE     (*(volatile unsigned long *)(0x6000d004))
 218 #define GPIOC_ENABLE     (*(volatile unsigned long *)(0x6000d008))
 219 #define GPIOD_ENABLE     (*(volatile unsigned long *)(0x6000d00c))
 220 #define GPIOA_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d010))
 221 #define GPIOB_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d014))
 222 #define GPIOC_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d018))
 223 #define GPIOD_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d01c))
 224 #define GPIOA_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d020))
 225 #define GPIOB_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d024))
 226 #define GPIOC_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d028))
 227 #define GPIOD_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d02c))
 228 #define GPIOA_INPUT_VAL  (*(volatile unsigned long *)(0x6000d030))
 229 #define GPIOB_INPUT_VAL  (*(volatile unsigned long *)(0x6000d034))
 230 #define GPIOC_INPUT_VAL  (*(volatile unsigned long *)(0x6000d038))
 231 #define GPIOD_INPUT_VAL  (*(volatile unsigned long *)(0x6000d03c))
 232 #define GPIOA_INT_STAT   (*(volatile unsigned long *)(0x6000d040))
 233 #define GPIOB_INT_STAT   (*(volatile unsigned long *)(0x6000d044))
 234 #define GPIOC_INT_STAT   (*(volatile unsigned long *)(0x6000d048))
 235 #define GPIOD_INT_STAT   (*(volatile unsigned long *)(0x6000d04c))
 236 #define GPIOA_INT_EN     (*(volatile unsigned long *)(0x6000d050))
 237 #define GPIOB_INT_EN     (*(volatile unsigned long *)(0x6000d054))
 238 #define GPIOC_INT_EN     (*(volatile unsigned long *)(0x6000d058))
 239 #define GPIOD_INT_EN     (*(volatile unsigned long *)(0x6000d05c))
 240 #define GPIOA_INT_LEV    (*(volatile unsigned long *)(0x6000d060))
 241 #define GPIOB_INT_LEV    (*(volatile unsigned long *)(0x6000d064))
 242 #define GPIOC_INT_LEV    (*(volatile unsigned long *)(0x6000d068))
 243 #define GPIOD_INT_LEV    (*(volatile unsigned long *)(0x6000d06c))
 244 #define GPIOA_INT_CLR    (*(volatile unsigned long *)(0x6000d070))
 245 #define GPIOB_INT_CLR    (*(volatile unsigned long *)(0x6000d074))
 246 #define GPIOC_INT_CLR    (*(volatile unsigned long *)(0x6000d078))
 247 #define GPIOD_INT_CLR    (*(volatile unsigned long *)(0x6000d07c))
 248
 249 #define GPIOE_ENABLE     (*(volatile unsigned long *)(0x6000d080))
 250 #define GPIOF_ENABLE     (*(volatile unsigned long *)(0x6000d084))
 251 #define GPIOG_ENABLE     (*(volatile unsigned long *)(0x6000d088))
 252 #define GPIOH_ENABLE     (*(volatile unsigned long *)(0x6000d08c))
 253 #define GPIOE_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d090))
 254 #define GPIOF_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d094))
 255 #define GPIOG_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d098))
 256 #define GPIOH_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d09c))
 257 #define GPIOE_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a0))
 258 #define GPIOF_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a4))
 259 #define GPIOG_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a8))
 260 #define GPIOH_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0ac))
 261 #define GPIOE_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b0))
 262 #define GPIOF_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b4))
 263 #define GPIOG_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b8))
 264 #define GPIOH_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0bc))
 265 #define GPIOE_INT_STAT   (*(volatile unsigned long *)(0x6000d0c0))
 266 #define GPIOF_INT_STAT   (*(volatile unsigned long *)(0x6000d0c4))
 267 #define GPIOG_INT_STAT   (*(volatile unsigned long *)(0x6000d0c8))
 268 #define GPIOH_INT_STAT   (*(volatile unsigned long *)(0x6000d0cc))
 269 #define GPIOE_INT_EN     (*(volatile unsigned long *)(0x6000d0d0))
 270 #define GPIOF_INT_EN     (*(volatile unsigned long *)(0x6000d0d4))
 271 #define GPIOG_INT_EN     (*(volatile unsigned long *)(0x6000d0d8))
 272 #define GPIOH_INT_EN     (*(volatile unsigned long *)(0x6000d0dc))
 273 #define GPIOE_INT_LEV    (*(volatile unsigned long *)(0x6000d0e0))
 274 #define GPIOF_INT_LEV    (*(volatile unsigned long *)(0x6000d0e4))
 275 #define GPIOG_INT_LEV    (*(volatile unsigned long *)(0x6000d0e8))
 276 #define GPIOH_INT_LEV    (*(volatile unsigned long *)(0x6000d0ec))
 277 #define GPIOE_INT_CLR    (*(volatile unsigned long *)(0x6000d0f0))
 278 #define GPIOF_INT_CLR    (*(volatile unsigned long *)(0x6000d0f4))
 279 #define GPIOG_INT_CLR    (*(volatile unsigned long *)(0x6000d0f8))
 280 #define GPIOH_INT_CLR    (*(volatile unsigned long *)(0x6000d0fc))
 281
 282 #define GPIOI_ENABLE     (*(volatile unsigned long *)(0x6000d100))
 283 #define GPIOJ_ENABLE     (*(volatile unsigned long *)(0x6000d104))
 284 #define GPIOK_ENABLE     (*(volatile unsigned long *)(0x6000d108))
 285 #define GPIOL_ENABLE     (*(volatile unsigned long *)(0x6000d10c))
 286 #define GPIOI_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d110))
 287 #define GPIOJ_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d114))
 288 #define GPIOK_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d118))
 289 #define GPIOL_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d11c))
 290 #define GPIOI_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d120))
 291 #define GPIOJ_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d124))
 292 #define GPIOK_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d128))
 293 #define GPIOL_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d12c))
 294 #define GPIOI_INPUT_VAL  (*(volatile unsigned long *)(0x6000d130))
 295 #define GPIOJ_INPUT_VAL  (*(volatile unsigned long *)(0x6000d134))
 296 #define GPIOK_INPUT_VAL  (*(volatile unsigned long *)(0x6000d138))
 297 #define GPIOL_INPUT_VAL  (*(volatile unsigned long *)(0x6000d13c))
 298 #define GPIOI_INT_STAT   (*(volatile unsigned long *)(0x6000d140))
 299 #define GPIOJ_INT_STAT   (*(volatile unsigned long *)(0x6000d144))
 300 #define GPIOK_INT_STAT   (*(volatile unsigned long *)(0x6000d148))
 301 #define GPIOL_INT_STAT   (*(volatile unsigned long *)(0x6000d14c))
 302 #define GPIOI_INT_EN     (*(volatile unsigned long *)(0x6000d150))
 303 #define GPIOJ_INT_EN     (*(volatile unsigned long *)(0x6000d154))
 304 #define GPIOK_INT_EN     (*(volatile unsigned long *)(0x6000d158))
 305 #define GPIOL_INT_EN     (*(volatile unsigned long *)(0x6000d15c))
 306 #define GPIOI_INT_LEV    (*(volatile unsigned long *)(0x6000d160))
 307 #define GPIOJ_INT_LEV    (*(volatile unsigned long *)(0x6000d164))
 308 #define GPIOK_INT_LEV    (*(volatile unsigned long *)(0x6000d168))
 309 #define GPIOL_INT_LEV    (*(volatile unsigned long *)(0x6000d16c))
 310 #define GPIOI_INT_CLR    (*(volatile unsigned long *)(0x6000d170))
 311 #define GPIOJ_INT_CLR    (*(volatile unsigned long *)(0x6000d174))
 312 #define GPIOK_INT_CLR    (*(volatile unsigned long *)(0x6000d178))
 313 #define GPIOL_INT_CLR    (*(volatile unsigned long *)(0x6000d17c))
 314
 315 /* Standard GPIO addresses + 0x800 allow atomic port manipulation on PP502x.
 316  * Bits 8..15 of the written word define which bits are changed, bits 0..7
 317  * define the value of those bits. */
 318
 319 #define GPIO_SET_BITWISE(port, mask) \
 320         do { *(&port + (0x800/sizeof(long))) = (mask << 8) | mask; } while(0)
 321
 322 #define GPIO_CLEAR_BITWISE(port, mask) \
 323         do { *(&port + (0x800/sizeof(long))) = mask << 8; } while(0)
 324
 325 /* Device initialization */
 326 #define PP_VER1          (*(volatile unsigned long *)(0x70000000))
 327 #define PP_VER2          (*(volatile unsigned long *)(0x70000004))
 328 #define STRAP_OPT_A      (*(volatile unsigned long *)(0x70000008))
 329 #define STRAP_OPT_B      (*(volatile unsigned long *)(0x7000000c))
 330 #define BUS_WIDTH_MASK   0x00000010
 331 #define RAM_TYPE_MASK    0x000000c0
 332 #define ROM_TYPE_MASK    0x00000008
 333
 334 #define DEV_INIT1        (*(volatile unsigned long *)(0x70000010))
 335 #define DEV_INIT2        (*(volatile unsigned long *)(0x70000020))
 336 /* some timing that needs to be handled during clock setup */
 337 #define DEV_TIMING1      (*(volatile unsigned long *)(0x70000034))
 338 #define XMB_NOR_CFG      (*(volatile unsigned long *)(0x70000038))
 339 #define XMB_RAM_CFG      (*(volatile unsigned long *)(0x7000003c))
 340
 341 #define INIT_BUTTONS     0x00040000
 342 #define INIT_PLL         0x40000000
 343 #define INIT_USB         0x80000000
 344
 345 /* 32 bit GPO port */
 346 #define GPO32_VAL        (*(volatile unsigned long *)(0x70000080))
 347 #define GPO32_ENABLE     (*(volatile unsigned long *)(0x70000084))
 348
 349 /* IIS */
 350 #define IISDIV              (*(volatile unsigned long*)(0x60006080))
 351 #define IISCONFIG           (*(volatile unsigned long*)(0x70002800))
 352 #define IISCLK              (*(volatile unsigned long*)(0x70002808))
 353 #define IISFIFO_CFG         (*(volatile unsigned long*)(0x7000280c))
 354 #define IISFIFO_WR          (*(volatile unsigned long*)(0x70002840))
 355 #define IISFIFO_WRH         (*(volatile unsigned short*)(0x70002840))
 356 #define IISFIFO_RD          (*(volatile unsigned long*)(0x70002880))
 357 #define IISFIFO_RDH         (*(volatile unsigned short*)(0x70002880))
 358
 359 /**
 360  * IISCONFIG bits:
 361  * |   31   |   30   |   29   |   28   |   27   |   26   |   25   |   24   |
 362  * | RESET  |        |TXFIFOEN|RXFIFOEN|        |  ????  |   MS   |  ????  |
 363  * |   23   |   22   |   21   |   20   |   19   |   18   |   17   |   16   |
 364  * |        |        |        |        |        |        |        |        |
 365  * |   15   |   14   |   13   |   12   |   11   |   10   |    9   |    8   |
 366  * |        |        |        |        | Bus Format[1:0] |     Size[1:0]   |
 367  * |    7   |    6   |    5   |    4   |    3   |    2   |    1   |    0   |
 368  * |        |     Size Format[2:0]     |  ????  |  ????  | IRQTX  | IRQRX  |
 369  */
 370
 371 /* All IIS formats send MSB first */
 372 #define IIS_RESET    (1 << 31)
 373 #define IIS_TXFIFOEN (1 << 29)
 374 #define IIS_RXFIFOEN (1 << 28)
 375 #define IIS_MASTER   (1 << 25)
 376 #define IIS_IRQTX    (1 << 1)
 377 #define IIS_IRQRX    (1 << 0)
 378
 379 #define IIS_IRQTX_REG  IISCONFIG
 380 #define IIS_IRQRX_REG  IISCONFIG
 381
 382 /* Data format on the IIS bus */
 383 #define IIS_FORMAT_MASK  (0x3 << 10)
 384 #define IIS_FORMAT_IIS   (0x0 << 10) /* Standard IIS - leading dummy bit */
 385 #define IIS_FORMAT_1     (0x1 << 10)
 386 #define IIS_FORMAT_LJUST (0x2 << 10) /* Left justified - no dummy bit */
 387 #define IIS_FORMAT_3     (0x3 << 10)
 388 /* Other formats not yet known  */
 389
 390 /* Data size on IIS bus */
 391 #define IIS_SIZE_MASK   (0x3 << 8)
 392 #define IIS_SIZE_16BIT  (0x0 << 8)
 393 /* Other sizes not yet known */
 394
 395 /* Data size/format on IIS FIFO */
 396 #define IIS_FIFO_FORMAT_MASK        (0x7 << 4)
 397 #define IIS_FIFO_FORMAT_LE_HALFWORD (0x0 << 4)
 398 /* Big-endian formats - data sent to the FIFO must be big endian.
 399  * I forgot which is which size but did test them. */
 400 #define IIS_FIFO_FORMAT_1           (0x1 << 4)
 401 #define IIS_FIFO_FORMAT_2           (0x2 << 4)
 402 /* 32bit-MSB-little endian */
 403 #define IIS_FIFO_FORMAT_LE32        (0x3 << 4)
 404 /* 16bit-MSB-little endian */
 405 #define IIS_FIFO_FORMAT_LE16        (0x4 << 4)
 406 #define IIS_FIFO_FORMAT_5           (0x5 << 4)
 407 #define IIS_FIFO_FORMAT_6           (0x6 << 4)
 408 /* A second one like IIS_FIFO_FORMAT_LE16? PP5020 only? */
 409 #define IIS_FIFO_FORMAT_LE16_2      (0x7 << 4)
 410
 411 /* FIFO formats 0x5 and above seem equivalent to 0x4 ?? */
 412
 413 /**
 414  * IISFIFO_CFG bits:
 415  * |   31   |   30   |   29   |   28   |   27   |   26   |   25   |   24   |
 416  * |        |        |                      RXFull[5:0]                    |
 417  * |   23   |   22   |   21   |   20   |   19   |   18   |   17   |   16   |
 418  * |        |        |                      TXFree[5:0]                    |
 419  * |   15   |   14   |   13   |   12   |   11   |   10   |    9   |    8   |
 420  * |        |        |        | RXCLR  |        |        |        | TXCLR  |
 421  * |    7   |    6   |    5   |    4   |    3   |    2   |    1   |    0   |
 422  * |        |        |   RX_FULL_LVL   |        |        |  TX_EMPTY_LVL   |
 423  */
 424
 425 /* handy macros to extract the FIFO counts */
 426 #define IIS_RX_FULL_MASK (0x3f << 24)
 427 #define IIS_RX_FULL_COUNT \
 428     ((IISFIFO_CFG & IIS_RX_FULL_MASK) >> 24)
 429
 430 #define IIS_TX_FREE_MASK (0x3f << 16)
 431 #define IIS_TX_FREE_COUNT \
 432     ((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 16)
 433
 434 #define IIS_RXCLR (1 << 12)
 435 #define IIS_TXCLR (1 << 8)
 436 /* Number of slots */
 437 #define IIS_RX_FULL_LVL_4  (0x1 << 4)
 438 #define IIS_RX_FULL_LVL_8  (0x2 << 4)
 439 #define IIS_RX_FULL_LVL_12 (0x3 << 4)
 440
 441 #define IIS_TX_EMPTY_LVL_4  (0x1 << 0)
 442 #define IIS_TX_EMPTY_LVL_8  (0x2 << 0)
 443 #define IIS_TX_EMPTY_LVL_12 (0x3 << 0)
 444
 445 /* Note: didn't bother to see of levels 0 and 16 actually work */
 446
 447 /* First ("mono") LCD bridge */
 448 #define LCD1_BASE           0x70003000
 449
 450 #define LCD1_CONTROL        (*(volatile unsigned long *)(0x70003000))
 451 #define LCD1_CMD            (*(volatile unsigned long *)(0x70003008))
 452 #define LCD1_DATA           (*(volatile unsigned long *)(0x70003010))
 453
 454 #define LCD1_BUSY_MASK      0x8000
 455
 456 /* Serial Controller */
 457 #define SER0_BASE           (*(volatile unsigned long*)(0x70006000))
 458
 459 #define SER0_RBR            (*(volatile unsigned long*)(0x70006000))
 460 #define SER0_THR            (*(volatile unsigned long*)(0x70006000))
 461 #define SER0_IER            (*(volatile unsigned long*)(0x70006004))
 462 #define SER0_FCR            (*(volatile unsigned long*)(0x70006008))
 463 #define SER0_IIR            (*(volatile unsigned long*)(0x70006008))
 464 #define SER0_LCR            (*(volatile unsigned long*)(0x7000600c))
 465 #define SER0_MCR            (*(volatile unsigned long*)(0x70006010))
 466 #define SER0_LSR            (*(volatile unsigned long*)(0x70006014))
 467 #define SER0_MSR            (*(volatile unsigned long*)(0x70006018))
 468 #define SER0_SPR            (*(volatile unsigned long*)(0x7000601c))
 469
 470 #define SER0_DLL            (*(volatile unsigned long*)(0x70006000))
 471 #define SER0_DLM            (*(volatile unsigned long*)(0x70006004))
 472
 473 #define SER1_BASE           (*(volatile unsigned long*)(0x70006040))
 474
 475 #define SER1_RBR            (*(volatile unsigned long*)(0x70006040))
 476 #define SER1_THR            (*(volatile unsigned long*)(0x70006040))
 477 #define SER1_IER            (*(volatile unsigned long*)(0x70006044))
 478 #define SER1_FCR            (*(volatile unsigned long*)(0x70006048))
 479 #define SER1_IIR            (*(volatile unsigned long*)(0x70006048))
 480 #define SER1_LCR            (*(volatile unsigned long*)(0x7000604c))
 481 #define SER1_MCR            (*(volatile unsigned long*)(0x70006050))
 482 #define SER1_LSR            (*(volatile unsigned long*)(0x70006054))
 483 #define SER1_MSR            (*(volatile unsigned long*)(0x70006058))
 484 #define SER1_SPR            (*(volatile unsigned long*)(0x7000605c))
 485
 486 #define SER1_DLL            (*(volatile unsigned long*)(0x70006040))
 487 #define SER1_DLM            (*(volatile unsigned long*)(0x70006044))
 488
 489 /* Second ("color") LCD bridge */
 490 #define LCD2_BASE           0x70008a00
 491
 492 #define LCD2_PORT           (*(volatile unsigned long*)(0x70008a0c))
 493 #define LCD2_BLOCK_CTRL     (*(volatile unsigned long*)(0x70008a20))
 494 #define LCD2_BLOCK_CONFIG   (*(volatile unsigned long*)(0x70008a24))
 495 #define LCD2_BLOCK_DATA     (*(volatile unsigned long*)(0x70008b00))
 496
 497 #define LCD2_BUSY_MASK      0x80000000
 498 #define LCD2_CMD_MASK       0x80000000
 499 #define LCD2_DATA_MASK      0x81000000
 500
 501 #define LCD2_BLOCK_READY    0x04000000
 502 #define LCD2_BLOCK_TXOK     0x01000000
 503
 504 /* I2C */
 505 #define I2C_BASE            0x7000c000
 506
 507 /* EIDE Controller */
 508 #define IDE_BASE            0xc3000000
 509
 510 #define IDE0_PRI_TIMING0    (*(volatile unsigned long*)(0xc3000000))
 511 #define IDE0_PRI_TIMING1    (*(volatile unsigned long*)(0xc3000004))
 512 #define IDE0_SEC_TIMING0    (*(volatile unsigned long*)(0xc3000008))
 513 #define IDE0_SEC_TIMING1    (*(volatile unsigned long*)(0xc300000c))
 514
 515 #define IDE1_PRI_TIMING0    (*(volatile unsigned long*)(0xc3000010))
 516 #define IDE1_PRI_TIMING1    (*(volatile unsigned long*)(0xc3000014))
 517 #define IDE1_SEC_TIMING0    (*(volatile unsigned long*)(0xc3000018))
 518 #define IDE1_SEC_TIMING1    (*(volatile unsigned long*)(0xc300001c))
 519
 520 #define IDE0_CFG            (*(volatile unsigned long*)(0xc3000028))
 521 #define IDE1_CFG            (*(volatile unsigned long*)(0xc300002c))
 522
 523 #define IDE0_CNTRLR_STAT    (*(volatile unsigned long*)(0xc30001e0))
 524
 525 /* USB controller */
 526 #define USB_BASE            0xc5000000
 527
 528 /* Firewire Controller */
 529 #define FIREWIRE_BASE       0xc6000000
 530
 531 /* Memory controller */
 532 #define CACHE_BASE              (*(volatile unsigned long*)(0xf0000000))
 533 /* 0xf0000000-0xf0001fff */
 534 #define CACHE_DATA_BASE         (*(volatile unsigned long*)(0xf0000000))
 535 /* 0xf0002000-0xf0003fff */
 536 #define CACHE_DATA_MIRROR_BASE  (*(volatile unsigned long*)(0xf0002000))
 537 /* 0xf0004000-0xf0007fff */
 538 #define CACHE_STATUS_BASE       (*(volatile unsigned long*)(0xf0004000))
 539 #define CACHE_FLUSH_BASE        (*(volatile unsigned long*)(0xf0008000))
 540 #define CACHE_INVALID_BASE      (*(volatile unsigned long*)(0xf000c000))
 541 #define MMAP_PHYS_READ_MASK     0x0100
 542 #define MMAP_PHYS_WRITE_MASK    0x0200
 543 #define MMAP_PHYS_DATA_MASK     0x0400
 544 #define MMAP_PHYS_CODE_MASK     0x0800
 545 #define MMAP_FIRST              (*(volatile unsigned long*)(0xf000f000))
 546 #define MMAP_LAST               (*(volatile unsigned long*)(0xf000f03c))
 547 #define MMAP0_LOGICAL           (*(volatile unsigned long*)(0xf000f000))
 548 #define MMAP0_PHYSICAL          (*(volatile unsigned long*)(0xf000f004))
 549 #define MMAP1_LOGICAL           (*(volatile unsigned long*)(0xf000f008))
 550 #define MMAP1_PHYSICAL          (*(volatile unsigned long*)(0xf000f00c))
 551 #define MMAP2_LOGICAL           (*(volatile unsigned long*)(0xf000f010))
 552 #define MMAP2_PHYSICAL          (*(volatile unsigned long*)(0xf000f014))
 553 #define MMAP3_LOGICAL           (*(volatile unsigned long*)(0xf000f018))
 554 #define MMAP3_PHYSICAL          (*(volatile unsigned long*)(0xf000f01c))
 555 #define MMAP4_LOGICAL           (*(volatile unsigned long*)(0xf000f020))
 556 #define MMAP4_PHYSICAL          (*(volatile unsigned long*)(0xf000f024))
 557 #define MMAP5_LOGICAL           (*(volatile unsigned long*)(0xf000f028))
 558 #define MMAP5_PHYSICAL          (*(volatile unsigned long*)(0xf000f02c))
 559 #define MMAP6_LOGICAL           (*(volatile unsigned long*)(0xf000f030))
 560 #define MMAP6_PHYSICAL          (*(volatile unsigned long*)(0xf000f034))
 561 #define MMAP7_LOGICAL           (*(volatile unsigned long*)(0xf000f038))
 562 #define MMAP7_PHYSICAL          (*(volatile unsigned long*)(0xf000f03c))
 563
 564 #endif /* __PP5020_H__ */