FS#8961 - Anti-Aliased Fonts.
[kugel-rb.git] / firmware / export / pp5020.h
blob2d8d0e1802a21e3472035b66ba52203d93b1e0fd
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2004 by Thom Johansen
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
21 #ifndef __PP5020_H__
22 #define __PP5020_H__
24 /* All info gleaned and/or copied from the iPodLinux project. */
26 /* PCM addresses for obtaining buffers will be what DMA is using (physical) */
27 #define HAVE_PCM_DMA_ADDRESS
29 /* USBOTG */
30 #define USB_NUM_ENDPOINTS 3
31 /* This needs to be 2048 byte aligned, but USB_QHARRAY_ATTR should take care
32 * of that */
33 #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(4)))
34 #define USB_DEVBSS_ATTR IBSS_ATTR
36 /* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */
37 #define DRAM_START 0x10000000
39 /* Processor ID */
40 #define PROCESSOR_ID (*(volatile unsigned long *)(0x60000000))
42 #define PROC_ID_CPU 0x55
43 #define PROC_ID_COP 0xaa
45 /* Mailboxes */
46 #define MBX_BASE (0x60001000)
47 /* Read bits in the mailbox */
48 #define MBX_MSG_STAT (*(volatile unsigned long *)(0x60001000))
49 /* Set bits in the mailbox */
50 #define MBX_MSG_SET (*(volatile unsigned long *)(0x60001004))
51 /* Clear bits in the mailbox */
52 #define MBX_MSG_CLR (*(volatile unsigned long *)(0x60001008))
53 /* Doesn't seem to be COP_REPLY at all :) */
54 #define MBX_UNKNOWN1 (*(volatile unsigned long *)(0x6000100c))
55 /* COP can set bit 29 - only CPU read clears it */
56 #define CPU_QUEUE (*(volatile unsigned long *)(0x60001010))
57 /* CPU can set bit 29 - only COP read clears it */
58 #define COP_QUEUE (*(volatile unsigned long *)(0x60001020))
60 #define PROC_QUEUE(core) ((&CPU_QUEUE)[(core)*4])
62 /* Interrupts */
63 #define CPU_INT_STAT (*(volatile unsigned long*)(0x60004000))
64 #define COP_INT_STAT (*(volatile unsigned long*)(0x60004004))
65 #define CPU_FIQ_STAT (*(volatile unsigned long*)(0x60004008))
66 #define COP_FIQ_STAT (*(volatile unsigned long*)(0x6000400c))
68 #define INT_STAT (*(volatile unsigned long*)(0x60004010))
69 #define INT_FORCED_STAT (*(volatile unsigned long*)(0x60004014))
70 #define INT_FORCED_SET (*(volatile unsigned long*)(0x60004018))
71 #define INT_FORCED_CLR (*(volatile unsigned long*)(0x6000401c))
73 #define CPU_INT_EN_STAT (*(volatile unsigned long*)(0x60004020))
74 #define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
75 #define CPU_INT_DIS (*(volatile unsigned long*)(0x60004028))
76 #define CPU_INT_PRIORITY (*(volatile unsigned long*)(0x6000402c))
78 #define COP_INT_EN_STAT (*(volatile unsigned long*)(0x60004030))
79 #define COP_INT_EN (*(volatile unsigned long*)(0x60004034))
80 #define COP_INT_DIS (*(volatile unsigned long*)(0x60004038))
81 #define COP_INT_PRIORITY (*(volatile unsigned long*)(0x6000403c))
83 #define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x60004100))
84 #define COP_HI_INT_STAT (*(volatile unsigned long*)(0x60004104))
85 #define CPU_HI_FIQ_STAT (*(volatile unsigned long*)(0x60004108))
86 #define COP_HI_FIQ_STAT (*(volatile unsigned long*)(0x6000410c))
88 #define HI_INT_STAT (*(volatile unsigned long*)(0x60004110))
89 #define HI_INT_FORCED_STAT (*(volatile unsigned long*)(0x60004114))
90 #define HI_INT_FORCED_SET (*(volatile unsigned long*)(0x60004118))
91 #define HI_INT_FORCED_CLR (*(volatile unsigned long*)(0x6000411c))
93 #define CPU_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004120))
94 #define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124))
95 #define CPU_HI_INT_DIS (*(volatile unsigned long*)(0x60004128))
96 #define CPU_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000412c))
98 #define COP_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004130))
99 #define COP_HI_INT_EN (*(volatile unsigned long*)(0x60004134))
100 #define COP_HI_INT_DIS (*(volatile unsigned long*)(0x60004138))
101 #define COP_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000413c))
103 #define TIMER1_IRQ 0
104 #define TIMER2_IRQ 1
105 #define MAILBOX_IRQ 4
106 #define IIS_IRQ 10
107 #define USB_IRQ 20
108 #define IDE_IRQ 23
109 #define FIREWIRE_IRQ 25
110 #define DMA_IRQ 26
111 #define HI_IRQ 30
112 #define GPIO0_IRQ (32+0) /* Ports A..D */
113 #define GPIO1_IRQ (32+1) /* Ports E..H */
114 #define GPIO2_IRQ (32+2) /* Ports I..L */
115 #define SER0_IRQ (32+4)
116 #define SER1_IRQ (32+5)
117 #define I2C_IRQ (32+8)
119 #define TIMER1_MASK (1 << TIMER1_IRQ)
120 #define TIMER2_MASK (1 << TIMER2_IRQ)
121 #define MAILBOX_MASK (1 << MAILBOX_IRQ)
122 #define IIS_MASK (1 << IIS_IRQ)
123 #define IDE_MASK (1 << IDE_IRQ)
124 #define USB_MASK (1 << USB_IRQ)
125 #define FIREWIRE_MASK (1 << FIREWIRE_IRQ)
126 #define DMA_MASK (1 << DMA_IRQ)
127 #define HI_MASK (1 << HI_IRQ)
128 #define GPIO0_MASK (1 << (GPIO0_IRQ-32))
129 #define GPIO1_MASK (1 << (GPIO1_IRQ-32))
130 #define GPIO2_MASK (1 << (GPIO2_IRQ-32))
131 #define SER0_MASK (1 << (SER0_IRQ-32))
132 #define SER1_MASK (1 << (SER1_IRQ-32))
133 #define I2C_MASK (1 << (I2C_IRQ-32))
135 /* Timers */
136 #define TIMER1_CFG (*(volatile unsigned long *)(0x60005000))
137 #define TIMER1_VAL (*(volatile unsigned long *)(0x60005004))
138 #define TIMER2_CFG (*(volatile unsigned long *)(0x60005008))
139 #define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c))
140 #define USEC_TIMER (*(volatile unsigned long *)(0x60005010))
141 #define RTC (*(volatile unsigned long *)(0x60005014))
143 /* Device Controller */
144 #define DEV_RS (*(volatile unsigned long *)(0x60006004))
145 #define DEV_RS2 (*(volatile unsigned long *)(0x60006008))
146 #define DEV_EN (*(volatile unsigned long *)(0x6000600c))
147 #define DEV_EN2 (*(volatile unsigned long *)(0x60006010))
149 #define DEV_EXTCLOCKS 0x00000002
150 #define DEV_SYSTEM 0x00000004
151 #define DEV_USB0 0x00000008
152 #define DEV_SER0 0x00000040
153 #define DEV_SER1 0x00000080
154 #define DEV_I2S 0x00000800
155 #define DEV_I2C 0x00001000
156 #define DEV_ATA 0x00004000
157 #define DEV_OPTO 0x00010000
158 #define DEV_PIEZO 0x00010000
159 #define DEV_PWM 0x00020000
160 #define DEV_USB1 0x00400000
161 #define DEV_FIREWIRE 0x00800000
162 #define DEV_IDE0 0x02000000
163 #define DEV_LCD 0x04000000
165 /* clock control */
166 #define CLOCK_SOURCE (*(volatile unsigned long *)(0x60006020))
167 #define MLCD_SCLK_DIV (*(volatile unsigned long *)(0x6000602c))
168 /* bits 0..1: Mono LCD bridge serial clock divider: 1 / (n+1) */
169 #define PLL_CONTROL (*(volatile unsigned long *)(0x60006034))
170 #define PLL_STATUS (*(volatile unsigned long *)(0x6000603c))
171 #define ADC_CLOCK_SRC (*(volatile unsigned long *)(0x60006094))
172 #define CLCD_CLOCK_SRC (*(volatile unsigned long *)(0x600060a0))
174 /* Processors Control */
175 #define CPU_CTL (*(volatile unsigned long *)(0x60007000))
176 #define COP_CTL (*(volatile unsigned long *)(0x60007004))
177 #define PROC_CTL(core) ((&CPU_CTL)[core])
179 /* Control flags, can be ORed together */
180 #define PROC_SLEEP 0x80000000 /* Sleep until an interrupt occurs */
181 #define PROC_WAIT_CNT 0x40000000 /* Sleep until end of countdown */
182 #define PROC_WAKE_INT 0x20000000 /* Fire interrupt on wake-up. Auto-clears. */
184 /* Counter source, select one */
185 #define PROC_CNT_CLKS 0x08000000 /* Clock cycles */
186 #define PROC_CNT_USEC 0x02000000 /* Microseconds */
187 #define PROC_CNT_MSEC 0x01000000 /* Milliseconds */
188 #define PROC_CNT_SEC 0x00800000 /* Seconds. Works on PP5022+ only! */
190 #define PROC_WAKE 0x00000000
193 * [22:8] - Semaphore flags for core communication? No execution effect observed
194 * [11:8] seem to often be set to the core's own ID
195 * nybble when sleeping - 0x5 or 0xa.
196 * [7:0] - W: number of cycles to skip on next instruction
197 * R: cycles remaining
198 * Executing on CPU
199 * CPU_CTL = 0x68000080
200 * nop
201 * stalls the nop for 128 cycles
202 * Reading CPU_CTL after the nop will return 0x48000000
206 /* Cache Control */
207 #define CACHE_PRIORITY (*(volatile unsigned long *)(0x60006044))
208 #define CACHE_CTL (*(volatile unsigned long *)(0x6000c000))
209 #define CACHE_MASK (*(volatile unsigned long *)(0xf000f040))
210 #define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f044))
211 #define CACHE_FLUSH_MASK (*(volatile unsigned long *)(0xf000f048))
213 /* CACHE_CTL bits */
214 #define CACHE_CTL_DISABLE 0x0000
215 #define CACHE_CTL_ENABLE 0x0001
216 #define CACHE_CTL_RUN 0x0002
217 #define CACHE_CTL_INIT 0x0004
218 #define CACHE_CTL_VECT_REMAP 0x0010
219 #define CACHE_CTL_READY 0x4000
220 #define CACHE_CTL_BUSY 0x8000
221 /* CACHE_OPERATION bits */
222 #define CACHE_OP_FLUSH 0x0002
223 #define CACHE_OP_INVALIDATE 0x0004
225 /* GPIO Ports */
226 #define GPIO_BASE_ADDR 0x6000d000
227 #define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000))
228 #define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004))
229 #define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008))
230 #define GPIOD_ENABLE (*(volatile unsigned long *)(0x6000d00c))
231 #define GPIOA_OUTPUT_EN (*(volatile unsigned long *)(0x6000d010))
232 #define GPIOB_OUTPUT_EN (*(volatile unsigned long *)(0x6000d014))
233 #define GPIOC_OUTPUT_EN (*(volatile unsigned long *)(0x6000d018))
234 #define GPIOD_OUTPUT_EN (*(volatile unsigned long *)(0x6000d01c))
235 #define GPIOA_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d020))
236 #define GPIOB_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d024))
237 #define GPIOC_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d028))
238 #define GPIOD_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d02c))
239 #define GPIOA_INPUT_VAL (*(volatile unsigned long *)(0x6000d030))
240 #define GPIOB_INPUT_VAL (*(volatile unsigned long *)(0x6000d034))
241 #define GPIOC_INPUT_VAL (*(volatile unsigned long *)(0x6000d038))
242 #define GPIOD_INPUT_VAL (*(volatile unsigned long *)(0x6000d03c))
243 #define GPIOA_INT_STAT (*(volatile unsigned long *)(0x6000d040))
244 #define GPIOB_INT_STAT (*(volatile unsigned long *)(0x6000d044))
245 #define GPIOC_INT_STAT (*(volatile unsigned long *)(0x6000d048))
246 #define GPIOD_INT_STAT (*(volatile unsigned long *)(0x6000d04c))
247 #define GPIOA_INT_EN (*(volatile unsigned long *)(0x6000d050))
248 #define GPIOB_INT_EN (*(volatile unsigned long *)(0x6000d054))
249 #define GPIOC_INT_EN (*(volatile unsigned long *)(0x6000d058))
250 #define GPIOD_INT_EN (*(volatile unsigned long *)(0x6000d05c))
251 #define GPIOA_INT_LEV (*(volatile unsigned long *)(0x6000d060))
252 #define GPIOB_INT_LEV (*(volatile unsigned long *)(0x6000d064))
253 #define GPIOC_INT_LEV (*(volatile unsigned long *)(0x6000d068))
254 #define GPIOD_INT_LEV (*(volatile unsigned long *)(0x6000d06c))
255 #define GPIOA_INT_CLR (*(volatile unsigned long *)(0x6000d070))
256 #define GPIOB_INT_CLR (*(volatile unsigned long *)(0x6000d074))
257 #define GPIOC_INT_CLR (*(volatile unsigned long *)(0x6000d078))
258 #define GPIOD_INT_CLR (*(volatile unsigned long *)(0x6000d07c))
260 #define GPIOE_ENABLE (*(volatile unsigned long *)(0x6000d080))
261 #define GPIOF_ENABLE (*(volatile unsigned long *)(0x6000d084))
262 #define GPIOG_ENABLE (*(volatile unsigned long *)(0x6000d088))
263 #define GPIOH_ENABLE (*(volatile unsigned long *)(0x6000d08c))
264 #define GPIOE_OUTPUT_EN (*(volatile unsigned long *)(0x6000d090))
265 #define GPIOF_OUTPUT_EN (*(volatile unsigned long *)(0x6000d094))
266 #define GPIOG_OUTPUT_EN (*(volatile unsigned long *)(0x6000d098))
267 #define GPIOH_OUTPUT_EN (*(volatile unsigned long *)(0x6000d09c))
268 #define GPIOE_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a0))
269 #define GPIOF_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a4))
270 #define GPIOG_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a8))
271 #define GPIOH_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0ac))
272 #define GPIOE_INPUT_VAL (*(volatile unsigned long *)(0x6000d0b0))
273 #define GPIOF_INPUT_VAL (*(volatile unsigned long *)(0x6000d0b4))
274 #define GPIOG_INPUT_VAL (*(volatile unsigned long *)(0x6000d0b8))
275 #define GPIOH_INPUT_VAL (*(volatile unsigned long *)(0x6000d0bc))
276 #define GPIOE_INT_STAT (*(volatile unsigned long *)(0x6000d0c0))
277 #define GPIOF_INT_STAT (*(volatile unsigned long *)(0x6000d0c4))
278 #define GPIOG_INT_STAT (*(volatile unsigned long *)(0x6000d0c8))
279 #define GPIOH_INT_STAT (*(volatile unsigned long *)(0x6000d0cc))
280 #define GPIOE_INT_EN (*(volatile unsigned long *)(0x6000d0d0))
281 #define GPIOF_INT_EN (*(volatile unsigned long *)(0x6000d0d4))
282 #define GPIOG_INT_EN (*(volatile unsigned long *)(0x6000d0d8))
283 #define GPIOH_INT_EN (*(volatile unsigned long *)(0x6000d0dc))
284 #define GPIOE_INT_LEV (*(volatile unsigned long *)(0x6000d0e0))
285 #define GPIOF_INT_LEV (*(volatile unsigned long *)(0x6000d0e4))
286 #define GPIOG_INT_LEV (*(volatile unsigned long *)(0x6000d0e8))
287 #define GPIOH_INT_LEV (*(volatile unsigned long *)(0x6000d0ec))
288 #define GPIOE_INT_CLR (*(volatile unsigned long *)(0x6000d0f0))
289 #define GPIOF_INT_CLR (*(volatile unsigned long *)(0x6000d0f4))
290 #define GPIOG_INT_CLR (*(volatile unsigned long *)(0x6000d0f8))
291 #define GPIOH_INT_CLR (*(volatile unsigned long *)(0x6000d0fc))
293 #define GPIOI_ENABLE (*(volatile unsigned long *)(0x6000d100))
294 #define GPIOJ_ENABLE (*(volatile unsigned long *)(0x6000d104))
295 #define GPIOK_ENABLE (*(volatile unsigned long *)(0x6000d108))
296 #define GPIOL_ENABLE (*(volatile unsigned long *)(0x6000d10c))
297 #define GPIOI_OUTPUT_EN (*(volatile unsigned long *)(0x6000d110))
298 #define GPIOJ_OUTPUT_EN (*(volatile unsigned long *)(0x6000d114))
299 #define GPIOK_OUTPUT_EN (*(volatile unsigned long *)(0x6000d118))
300 #define GPIOL_OUTPUT_EN (*(volatile unsigned long *)(0x6000d11c))
301 #define GPIOI_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d120))
302 #define GPIOJ_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d124))
303 #define GPIOK_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d128))
304 #define GPIOL_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d12c))
305 #define GPIOI_INPUT_VAL (*(volatile unsigned long *)(0x6000d130))
306 #define GPIOJ_INPUT_VAL (*(volatile unsigned long *)(0x6000d134))
307 #define GPIOK_INPUT_VAL (*(volatile unsigned long *)(0x6000d138))
308 #define GPIOL_INPUT_VAL (*(volatile unsigned long *)(0x6000d13c))
309 #define GPIOI_INT_STAT (*(volatile unsigned long *)(0x6000d140))
310 #define GPIOJ_INT_STAT (*(volatile unsigned long *)(0x6000d144))
311 #define GPIOK_INT_STAT (*(volatile unsigned long *)(0x6000d148))
312 #define GPIOL_INT_STAT (*(volatile unsigned long *)(0x6000d14c))
313 #define GPIOI_INT_EN (*(volatile unsigned long *)(0x6000d150))
314 #define GPIOJ_INT_EN (*(volatile unsigned long *)(0x6000d154))
315 #define GPIOK_INT_EN (*(volatile unsigned long *)(0x6000d158))
316 #define GPIOL_INT_EN (*(volatile unsigned long *)(0x6000d15c))
317 #define GPIOI_INT_LEV (*(volatile unsigned long *)(0x6000d160))
318 #define GPIOJ_INT_LEV (*(volatile unsigned long *)(0x6000d164))
319 #define GPIOK_INT_LEV (*(volatile unsigned long *)(0x6000d168))
320 #define GPIOL_INT_LEV (*(volatile unsigned long *)(0x6000d16c))
321 #define GPIOI_INT_CLR (*(volatile unsigned long *)(0x6000d170))
322 #define GPIOJ_INT_CLR (*(volatile unsigned long *)(0x6000d174))
323 #define GPIOK_INT_CLR (*(volatile unsigned long *)(0x6000d178))
324 #define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c))
326 /* Standard GPIO addresses + 0x800 allow atomic port manipulation on PP502x.
327 * Bits 8..15 of the written word define which bits are changed, bits 0..7
328 * define the value of those bits. */
330 #define GPIO_SET_BITWISE(port, mask) \
331 do { *(&(port) + (0x800/sizeof(long))) = ((mask) << 8) | (mask); } while(0)
333 #define GPIO_CLEAR_BITWISE(port, mask) \
334 do { *(&(port) + (0x800/sizeof(long))) = (mask) << 8; } while(0)
336 #define GPIO_WRITE_BITWISE(port, val, mask) \
337 do { *(&(port) + (0x800/sizeof(long))) = ((mask) << 8) | (val); } while(0)
339 /* GPIO Module 0 */
340 #define GPIOA 0
341 #define GPIOB 1
342 #define GPIOC 2
343 #define GPIOD 3
344 /* GPIO Module 1 */
345 #define GPIOE 4
346 #define GPIOF 5
347 #define GPIOG 6
348 #define GPIOH 7
349 /* GPIO Module 2 */
350 #define GPIOI 8
351 #define GPIOJ 9
352 #define GPIOK 10
353 #define GPIOL 11
355 #define GPIO_MODULE_NUM(gpio) ((gpio)>>2)
356 #define GPIO_MAP_ADDR(gpio) (GPIO_BASE_ADDR+(GPIO_MODULE_NUM(gpio)<<7)+(((gpio)&3)<<2))
357 #define GPIO_ENABLE(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x00))
358 #define GPIO_OUTPUT_EN(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x10))
359 #define GPIO_OUTPUT_VAL(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x20))
360 #define GPIO_INPUT_VAL(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x30))
361 #define GPIO_INT_STAT(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x40))
362 #define GPIO_INT_EN(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x50))
363 #define GPIO_INT_LEV(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x60))
364 #define GPIO_INT_CLR(gpio) (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x70))
365 #define GPIO_HI_INT_MASK(gpio) (1ul << GPIO_MODULE_NUM(gpio))
367 /* Device initialization */
368 #define PP_VER1 (*(volatile unsigned long *)(0x70000000))
369 #define PP_VER2 (*(volatile unsigned long *)(0x70000004))
370 #define STRAP_OPT_A (*(volatile unsigned long *)(0x70000008))
371 #define STRAP_OPT_B (*(volatile unsigned long *)(0x7000000c))
372 #define BUS_WIDTH_MASK 0x00000010
373 #define RAM_TYPE_MASK 0x000000c0
374 #define ROM_TYPE_MASK 0x00000008
376 #define DEV_INIT1 (*(volatile unsigned long *)(0x70000010))
377 #define DEV_INIT2 (*(volatile unsigned long *)(0x70000020))
378 /* some timing that needs to be handled during clock setup */
379 #define DEV_TIMING1 (*(volatile unsigned long *)(0x70000034))
380 #define XMB_NOR_CFG (*(volatile unsigned long *)(0x70000038))
381 #define XMB_RAM_CFG (*(volatile unsigned long *)(0x7000003c))
383 #define INIT_BUTTONS 0x00040000
384 #define INIT_PLL 0x40000000
385 #define INIT_USB 0x80000000
387 /* 32 bit GPO port */
388 #define GPO32_VAL (*(volatile unsigned long *)(0x70000080))
389 #define GPO32_ENABLE (*(volatile unsigned long *)(0x70000084))
391 /* IIS */
392 #define IISDIV (*(volatile unsigned long*)(0x60006080))
393 #define IISCONFIG (*(volatile unsigned long*)(0x70002800))
394 #define IISCLK (*(volatile unsigned long*)(0x70002808))
395 #define IISFIFO_CFG (*(volatile unsigned long*)(0x7000280c))
396 #define IISFIFO_WR (*(volatile unsigned long*)(0x70002840))
397 #define IISFIFO_WRH (*(volatile unsigned short*)(0x70002840))
398 #define IISFIFO_RD (*(volatile unsigned long*)(0x70002880))
399 #define IISFIFO_RDH (*(volatile unsigned short*)(0x70002880))
402 * IISCONFIG bits:
403 * | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
404 * | RESET | |TXFIFOEN|RXFIFOEN| | ???? | MS | ???? |
405 * | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
406 * | | | | | | | | |
407 * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
408 * | | | | | Bus Format[1:0] | Size[1:0] |
409 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
410 * | | Size Format[2:0] | ???? | ???? | IRQTX | IRQRX |
413 /* All IIS formats send MSB first */
414 #define IIS_RESET (1 << 31)
415 #define IIS_TXFIFOEN (1 << 29)
416 #define IIS_RXFIFOEN (1 << 28)
417 #define IIS_MASTER (1 << 25)
418 #define IIS_IRQTX (1 << 1)
419 #define IIS_IRQRX (1 << 0)
421 #define IIS_IRQTX_REG IISCONFIG
422 #define IIS_IRQRX_REG IISCONFIG
424 /* Data format on the IIS bus */
425 #define IIS_FORMAT_MASK (0x3 << 10)
426 #define IIS_FORMAT_IIS (0x0 << 10) /* Standard IIS - leading dummy bit */
427 #define IIS_FORMAT_1 (0x1 << 10)
428 #define IIS_FORMAT_LJUST (0x2 << 10) /* Left justified - no dummy bit */
429 #define IIS_FORMAT_3 (0x3 << 10)
430 /* Other formats not yet known */
432 /* Data size on IIS bus */
433 #define IIS_SIZE_MASK (0x3 << 8)
434 #define IIS_SIZE_16BIT (0x0 << 8)
435 /* Other sizes not yet known */
437 /* Data size/format on IIS FIFO */
438 #define IIS_FIFO_FORMAT_MASK (0x7 << 4)
439 #define IIS_FIFO_FORMAT_LE_HALFWORD (0x0 << 4)
440 /* Big-endian formats - data sent to the FIFO must be big endian.
441 * I forgot which is which size but did test them. */
442 #define IIS_FIFO_FORMAT_1 (0x1 << 4)
443 #define IIS_FIFO_FORMAT_2 (0x2 << 4)
444 /* 32bit-MSB-little endian */
445 #define IIS_FIFO_FORMAT_LE32 (0x3 << 4)
446 /* 16bit-MSB-little endian */
447 #define IIS_FIFO_FORMAT_LE16 (0x4 << 4)
448 #define IIS_FIFO_FORMAT_5 (0x5 << 4)
449 #define IIS_FIFO_FORMAT_6 (0x6 << 4)
450 /* A second one like IIS_FIFO_FORMAT_LE16? PP5020 only? */
451 #define IIS_FIFO_FORMAT_LE16_2 (0x7 << 4)
453 /* FIFO formats 0x5 and above seem equivalent to 0x4 ?? */
456 * IISFIFO_CFG bits:
457 * | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
458 * | | | RXFull[5:0] |
459 * | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
460 * | | | TXFree[5:0] |
461 * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
462 * | | | | RXCLR | | | | TXCLR |
463 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
464 * | | | RX_FULL_LVL | | | TX_EMPTY_LVL |
467 /* handy macros to extract the FIFO counts */
468 #define IIS_RX_FULL_MASK (0x3f << 24)
469 #define IIS_RX_FULL_COUNT \
470 ((IISFIFO_CFG & IIS_RX_FULL_MASK) >> 24)
472 #define IIS_TX_FREE_MASK (0x3f << 16)
473 #define IIS_TX_FREE_COUNT \
474 ((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 16)
476 #define IIS_TX_IS_EMPTY \
477 ((IISFIFO_CFG & IIS_TX_FREE_MASK) >= (16 << 16))
479 #define IIS_RXCLR (1 << 12)
480 #define IIS_TXCLR (1 << 8)
481 /* Number of slots */
482 #define IIS_RX_FULL_LVL_4 (0x1 << 4)
483 #define IIS_RX_FULL_LVL_8 (0x2 << 4)
484 #define IIS_RX_FULL_LVL_12 (0x3 << 4)
486 #define IIS_TX_EMPTY_LVL_4 (0x1 << 0)
487 #define IIS_TX_EMPTY_LVL_8 (0x2 << 0)
488 #define IIS_TX_EMPTY_LVL_12 (0x3 << 0)
490 /* Note: didn't bother to see of levels 0 and 16 actually work */
492 /* First ("mono") LCD bridge */
493 #define LCD1_BASE 0x70003000
495 #define LCD1_CONTROL (*(volatile unsigned long *)(0x70003000))
496 #define LCD1_CMD (*(volatile unsigned long *)(0x70003008))
497 #define LCD1_DATA (*(volatile unsigned long *)(0x70003010))
499 #define LCD1_BUSY_MASK 0x8000
501 /* Serial Controller */
502 #define SER0_BASE (*(volatile unsigned long*)(0x70006000))
504 #define SER0_RBR (*(volatile unsigned long*)(0x70006000))
505 #define SER0_THR (*(volatile unsigned long*)(0x70006000))
506 #define SER0_IER (*(volatile unsigned long*)(0x70006004))
507 #define SER0_FCR (*(volatile unsigned long*)(0x70006008))
508 #define SER0_IIR (*(volatile unsigned long*)(0x70006008))
509 #define SER0_LCR (*(volatile unsigned long*)(0x7000600c))
510 #define SER0_MCR (*(volatile unsigned long*)(0x70006010))
511 #define SER0_LSR (*(volatile unsigned long*)(0x70006014))
512 #define SER0_MSR (*(volatile unsigned long*)(0x70006018))
513 #define SER0_SPR (*(volatile unsigned long*)(0x7000601c))
515 #define SER0_DLL (*(volatile unsigned long*)(0x70006000))
516 #define SER0_DLM (*(volatile unsigned long*)(0x70006004))
518 #define SER1_BASE (*(volatile unsigned long*)(0x70006040))
520 #define SER1_RBR (*(volatile unsigned long*)(0x70006040))
521 #define SER1_THR (*(volatile unsigned long*)(0x70006040))
522 #define SER1_IER (*(volatile unsigned long*)(0x70006044))
523 #define SER1_FCR (*(volatile unsigned long*)(0x70006048))
524 #define SER1_IIR (*(volatile unsigned long*)(0x70006048))
525 #define SER1_LCR (*(volatile unsigned long*)(0x7000604c))
526 #define SER1_MCR (*(volatile unsigned long*)(0x70006050))
527 #define SER1_LSR (*(volatile unsigned long*)(0x70006054))
528 #define SER1_MSR (*(volatile unsigned long*)(0x70006058))
529 #define SER1_SPR (*(volatile unsigned long*)(0x7000605c))
531 #define SER1_DLL (*(volatile unsigned long*)(0x70006040))
532 #define SER1_DLM (*(volatile unsigned long*)(0x70006044))
534 /* Second ("color") LCD bridge */
535 #define LCD2_BASE 0x70008a00
537 #define LCD2_PORT (*(volatile unsigned long*)(0x70008a0c))
538 #define LCD2_BLOCK_CTRL (*(volatile unsigned long*)(0x70008a20))
539 #define LCD2_BLOCK_CONFIG (*(volatile unsigned long*)(0x70008a24))
540 #define LCD2_BLOCK_DATA (*(volatile unsigned long*)(0x70008b00))
542 #define LCD2_BUSY_MASK 0x80000000
543 #define LCD2_CMD_MASK 0x80000000
544 #define LCD2_DATA_MASK 0x81000000
546 #define LCD2_BLOCK_READY 0x04000000
547 #define LCD2_BLOCK_TXOK 0x01000000
549 /* I2C */
550 #define I2C_BASE 0x7000c000
552 /* EIDE Controller */
553 #define IDE_BASE 0xc3000000
555 #define IDE0_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000000))
556 #define IDE0_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000004))
557 #define IDE0_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000008))
558 #define IDE0_SEC_TIMING1 (*(volatile unsigned long*)(0xc300000c))
560 #define IDE1_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000010))
561 #define IDE1_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000014))
562 #define IDE1_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000018))
563 #define IDE1_SEC_TIMING1 (*(volatile unsigned long*)(0xc300001c))
565 #define IDE0_CFG (*(volatile unsigned long*)(0xc3000028))
566 #define IDE1_CFG (*(volatile unsigned long*)(0xc300002c))
568 #define IDE0_CNTRLR_STAT (*(volatile unsigned long*)(0xc30001e0))
570 /* USB controller */
571 #define USB_BASE 0xc5000000
573 /* Firewire Controller */
574 #define FIREWIRE_BASE 0xc6000000
576 /* Memory controller */
577 #define CACHE_BASE (*(volatile unsigned long*)(0xf0000000))
578 /* 0xf0000000-0xf0001fff */
579 #define CACHE_DATA_BASE (*(volatile unsigned long*)(0xf0000000))
580 /* 0xf0002000-0xf0003fff */
581 #define CACHE_DATA_MIRROR_BASE (*(volatile unsigned long*)(0xf0002000))
582 /* 0xf0004000-0xf0007fff */
583 #define CACHE_STATUS_BASE (*(volatile unsigned long*)(0xf0004000))
584 #define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
585 #define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
586 #define MMAP_PHYS_READ_MASK 0x0100
587 #define MMAP_PHYS_WRITE_MASK 0x0200
588 #define MMAP_PHYS_DATA_MASK 0x0400
589 #define MMAP_PHYS_CODE_MASK 0x0800
590 #define MMAP_FIRST (*(volatile unsigned long*)(0xf000f000))
591 #define MMAP_LAST (*(volatile unsigned long*)(0xf000f03c))
592 #define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
593 #define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
594 #define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
595 #define MMAP1_PHYSICAL (*(volatile unsigned long*)(0xf000f00c))
596 #define MMAP2_LOGICAL (*(volatile unsigned long*)(0xf000f010))
597 #define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014))
598 #define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
599 #define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
600 #define MMAP4_LOGICAL (*(volatile unsigned long*)(0xf000f020))
601 #define MMAP4_PHYSICAL (*(volatile unsigned long*)(0xf000f024))
602 #define MMAP5_LOGICAL (*(volatile unsigned long*)(0xf000f028))
603 #define MMAP5_PHYSICAL (*(volatile unsigned long*)(0xf000f02c))
604 #define MMAP6_LOGICAL (*(volatile unsigned long*)(0xf000f030))
605 #define MMAP6_PHYSICAL (*(volatile unsigned long*)(0xf000f034))
606 #define MMAP7_LOGICAL (*(volatile unsigned long*)(0xf000f038))
607 #define MMAP7_PHYSICAL (*(volatile unsigned long*)(0xf000f03c))
609 /** DMA engine **/
610 #define DMA0_BASE_ADDR 0x6000b000
611 #define DMA1_BASE_ADDR 0x6000b020
612 #define DMA2_BASE_ADDR 0x6000b040
613 #define DMA3_BASE_ADDR 0x6000b060
615 /* DMA request IDs */
616 #define DMA_REQ_IIS 2
617 #define DMA_REQ_SDHC 13
619 #define DMA_MASTER_CONTROL (*(volatile unsigned long*)(0x6000a000))
620 #define DMA_MASTER_STATUS (*(volatile unsigned long*)(0x6000a004))
621 /* 1ul << DMA_REQ_xxx to set bit */
622 #define DMA_REQ_STATUS (*(volatile unsigned long*)(0x6000a008))
624 #define DMA_MASTER_CONTROL_EN (1 << 31)
626 #define DMA_MASTER_STATUS_CH0 (0x1 << 24)
627 #define DMA_MASTER_STATUS_CH1 (0x1 << 25)
628 #define DMA_MASTER_STATUS_CH2 (0x1 << 26)
629 #define DMA_MASTER_STATUS_CH3 (0x1 << 27)
631 #define DMA0_CMD (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x00))
632 #define DMA0_STATUS (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x04))
633 #define DMA0_RAM_ADDR (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x10))
634 #define DMA0_FLAGS (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x14))
635 #define DMA0_PER_ADDR (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x18))
636 #define DMA0_INCR (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x1c))
638 #define DMA1_CMD (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x00))
639 #define DMA1_STATUS (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x04))
640 #define DMA1_RAM_ADDR (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x10))
641 #define DMA1_FLAGS (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x14))
642 #define DMA1_PER_ADDR (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x18))
643 #define DMA1_INCR (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x1c))
645 #define DMA2_CMD (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x00))
646 #define DMA2_STATUS (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x04))
647 #define DMA2_RAM_ADDR (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x10))
648 #define DMA2_FLAGS (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x14))
649 #define DMA2_PER_ADDR (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x18))
650 #define DMA2_INCR (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x1c))
652 #define DMA3_CMD (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x00))
653 #define DMA3_STATUS (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x04))
654 #define DMA3_RAM_ADDR (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x10))
655 #define DMA3_FLAGS (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x14))
656 #define DMA3_PER_ADDR (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x18))
657 #define DMA3_INCR (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x1c))
659 #define DMA_CMD_SIZE (0xffff)
660 #define DMA_CMD_REQ_ID (0xf << 16)
661 #define DMA_CMD_REQ_ID_POS 16
662 #define DMA_CMD_WAIT_REQ (0x1 << 24)
663 #define DMA_CMD_UNK25 (0x1 << 25)
664 #define DMA_CMD_SINGLE (0x1 << 26) /* stop on complete, no auto reload */
665 #define DMA_CMD_RAM_TO_PER (0x1 << 27) /* otherwise per to ram */
666 #define DMA_CMD_SLEEP_WAIT (0x1 << 28)
667 #define DMA_CMD_INTR (0x1 << 30)
668 #define DMA_CMD_START (0x1 << 31)
670 #define DMA_STATUS_SIZE_REMAIN (0xffff)
671 #define DMA_STATUS_INTR (0x1 << 30)
672 #define DMA_STATUS_BUSY (0x1 << 31)
674 #define DMA_FLAGS_ALIGNED (0x1 << 24)
675 #define DMA_FLAGS_UNK26 (0x1 << 26)
677 #define DMA_INCR_RANGE (0x7 << 16)
678 #define DMA_INCR_RANGE_UNL (0x0 << 16)
679 #define DMA_INCR_RANGE_FIXED (0x1 << 16)
680 #define DMA_INCR_RANGE_ALTR (0x2 << 16)
681 #define DMA_INCR_RANGE_4 (0x3 << 16)
682 #define DMA_INCR_RANGE_8 (0x4 << 16)
683 #define DMA_INCR_RANGE_16 (0x5 << 16)
684 #define DMA_INCR_RANGE_32 (0x6 << 16)
685 #define DMA_INCR_RANGE_64 (0x7 << 16)
687 #define DMA_INCR_WIDTH (0x7 << 28)
688 #define DMA_INCR_WIDTH_8BIT (0x0 << 28)
689 #define DMA_INCR_WIDTH_16BIT (0x1 << 28)
690 #define DMA_INCR_WIDTH_32BIT (0x2 << 28)
691 /* All other values reserved? */
693 /* Timer frequency */
694 /* Portalplayer chips use a microsecond timer. */
695 #define TIMER_FREQ 1000000
697 #endif /* __PP5020_H__ */