Trim down peak calculation a bit.
[kugel-rb.git] / firmware / target / arm / s5l8700 / system-s5l8700.c
blob68ec3826a82711b1ed5d335cb39feab4f042e855
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2007 by Rob Purchase
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
22 #include "kernel.h"
23 #include "system.h"
24 #include "panic.h"
25 #ifdef IPOD_NANO2G
26 #include "storage.h"
27 #include "pmu-target.h"
28 #endif
30 #define default_interrupt(name) \
31 extern __attribute__((weak,alias("UIRQ"))) void name (void)
33 void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
34 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked, \
35 weak, alias("fiq_dummy")));
37 default_interrupt(EXT0);
38 default_interrupt(EXT1);
39 default_interrupt(EXT2);
40 default_interrupt(EINT_VBUS);
41 default_interrupt(EINTG);
42 default_interrupt(INT_TIMERA);
43 default_interrupt(INT_WDT);
44 default_interrupt(INT_TIMERB);
45 default_interrupt(INT_TIMERC);
46 default_interrupt(INT_TIMERD);
47 default_interrupt(INT_DMA);
48 default_interrupt(INT_ALARM_RTC);
49 default_interrupt(INT_PRI_RTC);
50 default_interrupt(RESERVED1);
51 default_interrupt(INT_UART);
52 default_interrupt(INT_USB_HOST);
53 default_interrupt(INT_USB_FUNC);
54 default_interrupt(INT_LCDC_0);
55 default_interrupt(INT_LCDC_1);
56 default_interrupt(INT_ECC);
57 default_interrupt(INT_CALM);
58 default_interrupt(INT_ATA);
59 default_interrupt(INT_UART0);
60 default_interrupt(INT_SPDIF_OUT);
61 default_interrupt(INT_SDCI);
62 default_interrupt(INT_LCD);
63 default_interrupt(INT_SPI);
64 default_interrupt(INT_IIC);
65 default_interrupt(RESERVED2);
66 default_interrupt(INT_MSTICK);
67 default_interrupt(INT_ADC_WAKEUP);
68 default_interrupt(INT_ADC);
69 default_interrupt(INT_UNK1);
70 default_interrupt(INT_UNK2);
71 default_interrupt(INT_UNK3);
74 void INT_TIMER(void)
76 if (TACON & 0x00038000) INT_TIMERA();
77 if (TBCON & 0x00038000) INT_TIMERB();
78 if (TCCON & 0x00038000) INT_TIMERC();
79 if (TDCON & 0x00038000) INT_TIMERD();
83 #if CONFIG_CPU==S5L8701
84 static void (* const irqvector[])(void) =
85 { /* still 90% unverified and probably incorrect */
86 EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMER,INT_WDT,INT_UNK1,
87 INT_UNK2,INT_UNK3,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
88 INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,INT_ECC,
89 INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
91 #else
92 static void (* const irqvector[])(void) =
94 EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB,
95 INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
96 INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
97 INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
99 #endif
101 #if CONFIG_CPU==S5L8701
102 static const char * const irqname[] =
103 { /* still 90% unverified and probably incorrect */
104 "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMER","INT_WDT","INT_UNK1",
105 "INT_UNK2","INT_UNK3","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
106 "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT","INT_ECC",
107 "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
109 #else
110 static const char * const irqname[] =
112 "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB",
113 "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
114 "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
115 "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
117 #endif
119 static void UIRQ(void)
121 unsigned int offset = INTOFFSET;
122 panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
125 void irq_handler(void)
128 * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
131 asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
132 "sub sp, sp, #8 \n"); /* Reserve stack */
134 int irq_no = INTOFFSET;
136 irqvector[irq_no]();
138 /* clear interrupt */
139 SRCPND = (1 << irq_no);
140 INTPND = INTPND;
142 asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
143 "ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
144 "subs pc, lr, #4 \n"); /* Return from IRQ */
147 void fiq_dummy(void)
149 asm volatile (
150 "subs pc, lr, #4 \r\n"
155 void system_init(void)
157 pmu_init();
160 void system_reboot(void)
162 #ifdef IPOD_NANO2G
163 #ifdef HAVE_STORAGE_FLUSH
164 storage_flush();
165 #endif
167 /* Reset the SoC */
168 asm volatile("msr CPSR_c, #0xd3 \n"
169 "mov r5, #0x110000 \n"
170 "add r5, r5, #0xff \n"
171 "add r6, r5, #0xa00 \n"
172 "mov r10, #0x3c800000 \n"
173 "str r6, [r10] \n"
174 "mov r6, #0xff0 \n"
175 "str r6, [r10,#4] \n"
176 "str r5, [r10] \n");
178 /* Wait for reboot to kick in */
179 while(1);
180 #endif
183 void system_exception_wait(void)
185 while(1);
188 int system_memory_guard(int newmode)
190 (void)newmode;
191 return 0;
194 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
196 void set_cpu_frequency(long frequency)
198 if (cpu_frequency == frequency)
199 return;
201 int oldlevel = disable_irq_save();
203 #if 1
204 if (frequency == CPUFREQ_MAX)
206 /* FCLK_CPU = PLL0, HCLK = PLL0 / 2 */
207 CLKCON = (CLKCON & ~0xFF00FF00) | 0x20003100;
208 /* PCLK = HCLK / 2 */
209 CLKCON2 |= 0x200;
210 /* Switch to ASYNCHRONOUS mode */
211 asm volatile(
212 "mrc p15, 0, r0,c1,c0 \n\t"
213 "orr r0, r0, #0xc0000000 \n\t"
214 "mcr p15, 0, r0,c1,c0 \n\t"
215 ::: "r0"
218 else
220 /* Switch to FASTBUS mode */
221 asm volatile(
222 "mrc p15, 0, r0,c1,c0 \n\t"
223 "bic r0, r0, #0xc0000000 \n\t"
224 "mcr p15, 0, r0,c1,c0 \n\t"
225 ::: "r0"
227 /* PCLK = HCLK */
228 CLKCON2 &= ~0x200;
229 /* FCLK_CPU = OFF, HCLK = PLL0 / 4 */
230 CLKCON = (CLKCON & ~0xFF00FF00) | 0x80003300;
233 #else /* Alternative: Also clock down the PLL. Doesn't seem to save much
234 current, but results in high switching latency. */
236 if (frequency == CPUFREQ_MAX)
238 CLKCON &= ~0xFF00FF00; /* Everything back to the OSC */
239 PLLCON &= ~1; /* Power down PLL0 */
240 PLL0PMS = 0x021200; /* 192 MHz */
241 PLL0LCNT = 8100;
242 PLLCON |= 1; /* Power up PLL0 */
243 while (!(PLLLOCK & 1)); /* Wait for PLL to lock */
244 CLKCON2 |= 0x200; /* PCLK = HCLK / 2 */
245 CLKCON |= 0x20003100; /* FCLK_CPU = PLL0, PCLK = PLL0 / 2 */
247 else
249 CLKCON &= ~0xFF00FF00; /* Everything back to the OSC */
250 CLKCON2 &= ~0x200; /* PCLK = HCLK */
251 PLLCON &= ~1; /* Power down PLL0 */
252 PLL0PMS = 0x000500; /* 48 MHz */
253 PLL0LCNT = 8100;
254 PLLCON |= 1; /* Power up PLL0 */
255 while (!(PLLLOCK & 1)); /* Wait for PLL to lock */
256 CLKCON |= 0x20002000; /* FCLK_CPU = PLL0, PCLK = PLL0 */
258 #endif
260 cpu_frequency = frequency;
261 restore_irq(oldlevel);
264 #endif