firmware/target/arm/s5l8700/pcm-s5l8700.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2009 Bertrik Sikken
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include <string.h>
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "audio.h"
  26 #include "s5l8700.h"
  27 #include "panic.h"
  28 #include "audiohw.h"
  29 #include "pcm.h"
  30 #include "pcm_sampr.h"
  31 #include "dma-target.h"
  32 #include "mmu-arm.h"
  33
  34 /*  Driver for the IIS/PCM part of the s5l8700 using DMA
  35
  36     Notes:
  37     - not all possible PCM sample rates are enabled (no support in codec driver)
  38     - pcm_play_dma_pause is untested, not sure if implemented the right way
  39     - pcm_play_dma_stop is untested, not sure if implemented the right way
  40     - recording is not implemented
  41 */
  42
  43 static volatile int locked = 0;
  44 size_t nextsize;
  45 size_t dblbufsize;
  46 int dmamode;
  47 const unsigned char* dblbuf;
  48
  49 /* table of recommended PLL/MCLK dividers for mode 256Fs from the datasheet */
  50 static const struct div_entry {
  51     int             pdiv, mdiv, sdiv, cdiv;
  52 } div_table[HW_NUM_FREQ] = {
  53 #ifdef IPOD_NANO2G
  54     [HW_FREQ_11] = {   2,   41,    5,    4},
  55     [HW_FREQ_22] = {   2,   41,    4,    4},
  56     [HW_FREQ_44] = {   2,   41,    3,    4},
  57     [HW_FREQ_88] = {   2,   41,    2,    4},
  58 #if 0   /* disabled because the codec driver does not support it (yet) */
  59     [HW_FREQ_8 ] = {   2,   12,    3,    9},
  60     [HW_FREQ_16] = {   2,   12,    2,    9},
  61     [HW_FREQ_32] = {   2,   12,    1,    9},
  62     [HW_FREQ_12] = {   2,   12,    4,    3},
  63     [HW_FREQ_24] = {   2,   12,    3,    3},
  64     [HW_FREQ_48] = {   2,   12,    2,    3},
  65     [HW_FREQ_96] = {   2,   12,    1,    3},
  66 #endif
  67 #else
  68     [HW_FREQ_11] = {  26,  189,    3,    8},
  69     [HW_FREQ_22] = {  50,   98,    2,    8},
  70     [HW_FREQ_44] = {  37,  151,    1,    9},
  71     [HW_FREQ_88] = {  50,   98,    1,    4},
  72 #if 0   /* disabled because the codec driver does not support it (yet) */
  73     [HW_FREQ_8 ] = {  28,  192,    3,   12},
  74     [HW_FREQ_16] = {  28,  192,    3,    6},
  75     [HW_FREQ_32] = {  28,  192,    2,    6},
  76     [HW_FREQ_12] = {  28,  192,    3,    8},
  77     [HW_FREQ_24] = {  28,  192,    2,    8},
  78     [HW_FREQ_48] = {  28,  192,    2,    4},
  79     [HW_FREQ_96] = {  28,  192,    1,    4},
  80 #endif
  81 #endif
  82 };
  83
  84 /* Mask the DMA interrupt */
  85 void pcm_play_lock(void)
  86 {
  87     if (locked++ == 0) {
  88         INTMSK &= ~(1 << 10);
  89     }
  90 }
  91
  92 /* Unmask the DMA interrupt if enabled */
  93 void pcm_play_unlock(void)
  94 {
  95     if (--locked == 0) {
  96         INTMSK |= (1 << 10);
  97     }
  98 }
  99
 100 static const void* dma_callback(void) ICODE_ATTR __attribute__((used));
 101 static const void* dma_callback(void)
 102 {
 103     if (dmamode)
 104     {
 105         unsigned char *dma_start_addr;
 106         register pcm_more_callback_type get_more = pcm_callback_for_more;
 107         if (get_more)
 108         {
 109             get_more(&dma_start_addr, &nextsize);
 110             if (nextsize >= 4096)
 111             {
 112                 dblbufsize = (nextsize >> 4) & ~3;
 113                 nextsize = nextsize - dblbufsize;
 114                 dblbuf = dma_start_addr + nextsize;
 115                 dmamode = 0;
 116             }
 117             nextsize = (nextsize >> 1) - 1;
 118             clean_dcache();
 119             return dma_start_addr;
 120         }
 121         else
 122         {
 123             nextsize = -1;
 124             return 0;
 125         }
 126     }
 127     else
 128     {
 129         dmamode = 1;
 130         nextsize = (dblbufsize >> 1) - 1;
 131         return dblbuf;
 132     }
 133 }
 134
 135 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked)) ICODE_ATTR;
 136 void fiq_handler(void)
 137 {
 138     asm volatile (
 139         "cmn    r11, #1                            \n"
 140         "strne  r10, [r8]                          \n"  /* DMABASE0 */
 141         "strne  r11, [r8,#0x08]                    \n"  /* DMATCNT0 */
 142         "strne  r9, [r8,#0x14]                     \n"  /* DMACOM0 */
 143         "moveq  r10, #5                            \n"  /* STOP DMA */
 144         "streq  r10, [r8,#0x14]                    \n"  /* DMACOM0 */
 145         "mov    r10, #7                            \n"  /* CLEAR IRQ */
 146         "str    r10, [r8,#0x14]                    \n"  /* DMACOM0 */
 147         "mov    r11, #0x39C00000                   \n"  /* SRCPND */
 148         "mov    r10, #0x00000400                   \n"  /* INT_DMA */
 149         "str    r10, [r11]                         \n"  /* ACK FIQ */
 150         "stmfd  sp!, {r0-r3,lr}                    \n"
 151         "ldreq  r0, =pcm_play_dma_stopped_callback \n"
 152         "ldrne  r0, =dma_callback                  \n"
 153         "mov    lr, pc                             \n"
 154         "bx     r0                                 \n"
 155         "mov    r10, r0                            \n"
 156         "ldmfd  sp!, {r0-r3,lr}                    \n"
 157         "ldr    r11, =nextsize                     \n"
 158         "ldr    r11, [r11]                         \n"
 159         "subs   pc, lr, #4                         \n"
 160     );
 161 }
 162
 163 void bootstrap_fiq(const void* addr, size_t tcnt) __attribute__((naked,noinline));
 164 void bootstrap_fiq(const void* addr, size_t tcnt)
 165 {
 166     (void)addr;
 167     (void)tcnt;
 168     asm volatile (
 169         "add    r2, lr, #4        \n"
 170         "mrs    r3, cpsr          \n"
 171         "msr    cpsr_c, #0xD1     \n"  /* FIQ mode, IRQ/FIQ disabled */
 172         "mov    r8, #0x38400000   \n"  /* DMA BASE */
 173         "mov    r9, #4            \n"  /* START DMA */
 174         "mov    r10, r0           \n"
 175         "mov    r11, r1           \n"
 176         "mov    r0, #0            \n"
 177         "ldr    r12, =fiq_handler \n"
 178         "ldr    sp, =_fiqstackend \n"
 179         "mov    lr, r2            \n"
 180         "msr    spsr_all, r3      \n"
 181         "bx     r12               \n"
 182     );
 183 }
 184
 185 void pcm_play_dma_start(const void *addr_in, size_t size)
 186 {
 187     unsigned char* addr = (unsigned char*)addr_in;
 188
 189     /* S1: DMA channel 0 set */
 190     DMACON0 = (0 << 30) |       /* DEVSEL */
 191               (1 << 29) |       /* DIR */
 192               (0 << 24) |       /* SCHCNT */
 193               (1 << 22) |       /* DSIZE */
 194               (0 << 19) |       /* BLEN */
 195               (0 << 18) |       /* RELOAD */
 196               (0 << 17) |       /* HCOMINT */
 197               (1 << 16) |       /* WCOMINT */
 198               (0 << 0);         /* OFFSET */
 199
 200 #ifdef IPOD_NANO2G
 201     PCON5 = (PCON5 & ~(0xFFFF0000)) | 0x77720000;
 202     PCON6 = (PCON6 & ~(0x0F000000)) | 0x02000000;
 203
 204     I2STXCON = (1 << 20) |  /* undocumented */
 205                (0 << 16) |  /* burst length */
 206                (0 << 15) |  /* 0 = falling edge */
 207                (0 << 13) |  /* 0 = basic I2S format */
 208                (0 << 12) |  /* 0 = MSB first */
 209                (0 << 11) |  /* 0 = left channel for low polarity */
 210                (5 << 8) |   /* MCLK divider */
 211                (0 << 5) |   /* 0 = 16-bit */
 212                (2 << 3) |   /* bit clock per frame */
 213                (1 << 0);    /* channel index */
 214 #else
 215     /* S2: IIS Tx mode set */
 216     I2STXCON = (DMA_IISOUT_BLEN << 16) |  /* burst length */
 217                (0 << 15) |  /* 0 = falling edge */
 218                (0 << 13) |  /* 0 = basic I2S format */
 219                (0 << 12) |  /* 0 = MSB first */
 220                (0 << 11) |  /* 0 = left channel for low polarity */
 221                (3 << 8) |   /* MCLK divider */
 222                (0 << 5) |   /* 0 = 16-bit */
 223                (0 << 3) |   /* bit clock per frame */
 224                (1 << 0);    /* channel index */
 225 #endif
 226
 227     /* S3: DMA channel 0 on */
 228     if (!size)
 229     {
 230         register pcm_more_callback_type get_more = pcm_callback_for_more;
 231         if (get_more) get_more(&addr, &size);
 232         else return;  /* Nothing to play!? */
 233     }
 234     if (!size) return;  /* Nothing to play!? */
 235     clean_dcache();
 236     if (size >= 4096)
 237     {
 238         dblbufsize = (size >> 4) & ~3;
 239         size = size - dblbufsize;
 240         dblbuf = addr + size;
 241         dmamode = 0;
 242     }
 243     else dmamode = 1;
 244     bootstrap_fiq(addr, (size >> 1) - 1);
 245
 246     /* S4: IIS Tx clock on */
 247     I2SCLKCON = (1 << 0);   /* 1 = power on */
 248
 249     /* S5: IIS Tx on */
 250     I2STXCOM = (1 << 3) |   /* 1 = transmit mode on */
 251                (1 << 2) |   /* 1 = I2S interface enable */
 252                (1 << 1) |   /* 1 = DMA request enable */
 253                (0 << 0);    /* 0 = LRCK on */
 254 }
 255
 256 void pcm_play_dma_stop(void)
 257 {
 258     /* DMA channel off */
 259     DMACOM0 = 5;
 260
 261     /* TODO Some time wait */
 262     /* LRCK half cycle wait */
 263
 264     /* IIS Tx off */
 265     I2STXCOM = (1 << 3) |   /* 1 = transmit mode on */
 266                (0 << 2) |   /* 1 = I2S interface enable */
 267                (1 << 1) |   /* 1 = DMA request enable */
 268                (0 << 0);    /* 0 = LRCK on */
 269 }
 270
 271 /* pause playback by disabling the I2S interface */
 272 void pcm_play_dma_pause(bool pause)
 273 {
 274     if (pause) {
 275         I2STXCOM |= (1 << 0);   /* LRCK off */
 276     }
 277     else {
 278         I2STXCOM &= ~(1 << 0);  /* LRCK on */
 279     }
 280 }
 281
 282 void pcm_play_dma_init(void)
 283 {
 284     /* configure IIS pins */
 285 #ifdef IPOD_NANO2G
 286     PCON5 = (PCON5 & ~(0xFFFF0000)) | 0x22220000;
 287     PCON6 = (PCON6 & ~(0x0F000000)) | 0x02000000;
 288 #else
 289     PCON7 = (PCON7 & ~(0x0FFFFF00)) | 0x02222200;
 290 #endif
 291
 292     /* enable clock to the IIS module */
 293     PWRCON &= ~(1 << 6);
 294
 295     /* Enable the DMA FIQ */
 296     INTMOD |= (1 << 10);
 297     INTMSK |= (1 << 10);
 298
 299     audiohw_preinit();
 300 }
 301
 302 void pcm_postinit(void)
 303 {
 304     audiohw_postinit();
 305 }
 306
 307 /* set the configured PCM frequency */
 308 void pcm_dma_apply_settings(void)
 309 {
 310   //    audiohw_set_frequency(pcm_sampr);
 311
 312     struct div_entry div = div_table[pcm_fsel];
 313
 314     PLLCON &= ~4;
 315     PLLCON &= ~0x10;
 316     PLLCON &= 0x3f;
 317     PLLCON |= 4;
 318
 319     /* configure PLL1 and MCLK for the desired sample rate */
 320     PLL1PMS = (div.pdiv << 16) |
 321               (div.mdiv << 8) |
 322               (div.sdiv << 0);
 323     PLL1LCNT = 7500;    /* no idea what to put here */
 324
 325     /* enable PLL1 and wait for lock */
 326     PLLCON |= (1 << 1);
 327     while ((PLLLOCK & (1 << 1)) == 0);
 328
 329     /* configure MCLK */
 330     CLKCON = (CLKCON & ~(0xFF)) |
 331              (0 << 7) |         /* MCLK_MASK */
 332              (2 << 5) |         /* MCLK_SEL = PLL1 */
 333              (1 << 4) |         /* MCLK_DIV_ON */
 334              (div.cdiv - 1);    /* MCLK_DIV_VAL */
 335 }
 336
 337 size_t pcm_get_bytes_waiting(void)
 338 {
 339     return (nextsize + DMACTCNT0 + 2) << 1;
 340 }
 341
 342 const void * pcm_play_dma_get_peak_buffer(int *count)
 343 {
 344     *count = DMACTCNT0 >> 1;
 345     return (void *)(((DMACADDR0 + 2) & ~3) | 0x40000000);
 346 }
 347
 348 #ifdef HAVE_PCM_DMA_ADDRESS
 349 void * pcm_dma_addr(void *addr)
 350 {
 351     if (addr != NULL)
 352         addr = (void*)((uintptr_t)addr | 0x40000000);
 353     return addr;
 354 }
 355 #endif
 356
 357
 358 /****************************************************************************
 359  ** Recording DMA transfer
 360  **/
 361 #ifdef HAVE_RECORDING
 362 void pcm_rec_lock(void)
 363 {
 364 }
 365
 366 void pcm_rec_unlock(void)
 367 {
 368 }
 369
 370 void pcm_rec_dma_record_more(void *start, size_t size)
 371 {
 372     (void)start;
 373     (void)size;
 374 }
 375
 376 void pcm_rec_dma_stop(void)
 377 {
 378 }
 379
 380 void pcm_rec_dma_start(void *addr, size_t size)
 381 {
 382     (void)addr;
 383     (void)size;
 384 }
 385
 386 void pcm_rec_dma_close(void)
 387 {
 388 }
 389
 390
 391 void pcm_rec_dma_init(void)
 392 {
 393 }
 394
 395
 396 const void * pcm_rec_dma_get_peak_buffer(void)
 397 {
 398     return NULL;
 399 }
 400
 401 #endif /* HAVE_RECORDING */