firmware/target/arm/s5l8700/pcm-s5l8700.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2009 Bertrik Sikken
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include <string.h>
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "audio.h"
  26 #include "s5l8700.h"
  27 #include "panic.h"
  28 #include "audiohw.h"
  29 #include "pcm.h"
  30 #include "pcm_sampr.h"
  31 #include "dma-target.h"
  32
  33 /*  Driver for the IIS/PCM part of the s5l8700 using DMA
  34
  35     Notes:
  36     - not all possible PCM sample rates are enabled (no support in codec driver)
  37     - pcm_play_dma_pause is untested, not sure if implemented the right way
  38     - pcm_play_dma_stop is untested, not sure if implemented the right way
  39     - pcm_play_dma_get_peak_buffer is not implemented
  40     - recording is not implemented
  41 */
  42
  43 static void             dma_callback(void);
  44 static volatile int     locked = 0;
  45
  46 /* table of recommended PLL/MCLK dividers for mode 256Fs from the datasheet */
  47 static const struct div_entry {
  48     int             pdiv, mdiv, sdiv, cdiv;
  49 } div_table[HW_NUM_FREQ] = {
  50     [HW_FREQ_11] = {  26,  189,    3,    8},
  51 #ifdef IPOD_NANO2G
  52     [HW_FREQ_22] = {  5,   6,    3,    4},
  53 #else
  54     [HW_FREQ_22] = {  50,   98,    2,    8},
  55 #endif
  56     [HW_FREQ_44] = {  37,  151,    1,    9},
  57     [HW_FREQ_88] = {  50,   98,    1,    4},
  58 #if 0   /* disabled because the codec driver does not support it (yet) */
  59     [HW_FREQ_8 ] = {  28,  192,    3,   12}
  60     [HW_FREQ_16] = {  28,  192,    3,    6},
  61     [HW_FREQ_32] = {  28,  192,    2,    6},
  62
  63     [HW_FREQ_12] = {  28,  192,    3,    8},
  64     [HW_FREQ_24] = {  28,  192,    2,    8},
  65     [HW_FREQ_48] = {  28,  192,    2,    4},
  66     [HW_FREQ_96] = {  28,  192,    1,    4},
  67 #endif
  68 };
  69
  70 /* Mask the DMA interrupt */
  71 void pcm_play_lock(void)
  72 {
  73     if (locked++ == 0) {
  74         INTMSK &= ~(1 << 10);
  75     }
  76 }
  77
  78 /* Unmask the DMA interrupt if enabled */
  79 void pcm_play_unlock(void)
  80 {
  81     if (--locked == 0) {
  82         INTMSK |= (1 << 10);
  83     }
  84 }
  85
  86 static void play_next(void *addr, size_t size)
  87 {
  88     /* setup DMA */
  89     dma_setup_channel(DMA_IISOUT_CHANNEL, DMA_IISOUT_SELECT, DMA_MEM_TO_IO,
  90                       DMA_IISOUT_DSIZE, DMA_IISOUT_BLEN, addr, size / 2,
  91                       dma_callback);
  92
  93     /* DMA channel on */
  94     dma_enable_channel(DMA_IISOUT_CHANNEL);
  95 }
  96
  97 static void dma_callback(void)
  98 {
  99     unsigned char *dma_start_addr;
 100     size_t dma_size;
 101
 102     register pcm_more_callback_type get_more = pcm_callback_for_more;
 103     if (get_more) {
 104         get_more(&dma_start_addr, &dma_size);
 105
 106         if (dma_size == 0) {
 107             pcm_play_dma_stop();
 108             pcm_play_dma_stopped_callback();
 109         }
 110         else {
 111             play_next(dma_start_addr, dma_size);
 112         }
 113     }
 114 }
 115
 116 void pcm_play_dma_start(const void *addr, size_t size)
 117 {
 118     /* S1: DMA channel 0 set */
 119     dma_setup_channel(DMA_IISOUT_CHANNEL, DMA_IISOUT_SELECT, DMA_MEM_TO_IO,
 120                       DMA_IISOUT_DSIZE, DMA_IISOUT_BLEN, (void *)addr, size / 2,
 121                       dma_callback);
 122
 123 #ifdef IPOD_NANO2G
 124     I2STXCON = (0x10 << 16) |  /* burst length */
 125                (0 << 15) |  /* 0 = falling edge */
 126                (0 << 13) |  /* 0 = basic I2S format */
 127                (0 << 12) |  /* 0 = MSB first */
 128                (0 << 11) |  /* 0 = left channel for low polarity */
 129                (5 << 8) |   /* MCLK divider */
 130                (0 << 5) |   /* 0 = 16-bit */
 131                (2 << 3) |   /* bit clock per frame */
 132                (1 << 0);    /* channel index */
 133 #else
 134     /* S2: IIS Tx mode set */
 135     I2STXCON = (DMA_IISOUT_BLEN << 16) |  /* burst length */
 136                (0 << 15) |  /* 0 = falling edge */
 137                (0 << 13) |  /* 0 = basic I2S format */
 138                (0 << 12) |  /* 0 = MSB first */
 139                (0 << 11) |  /* 0 = left channel for low polarity */
 140                (3 << 8) |   /* MCLK divider */
 141                (0 << 5) |   /* 0 = 16-bit */
 142                (0 << 3) |   /* bit clock per frame */
 143                (1 << 0);    /* channel index */
 144 #endif
 145
 146     /* S3: DMA channel 0 on */
 147     dma_enable_channel(DMA_IISOUT_CHANNEL);
 148
 149     /* S4: IIS Tx clock on */
 150     I2SCLKCON = (1 << 0);   /* 1 = power on */
 151
 152     /* S5: IIS Tx on */
 153     I2STXCOM = (1 << 3) |   /* 1 = transmit mode on */
 154                (1 << 2) |   /* 1 = I2S interface enable */
 155                (1 << 1) |   /* 1 = DMA request enable */
 156                (0 << 0);    /* 0 = LRCK on */
 157 }
 158
 159 void pcm_play_dma_stop(void)
 160 {
 161     /* DMA channel off */
 162     dma_disable_channel(DMA_IISOUT_CHANNEL);
 163
 164     /* TODO Some time wait */
 165     /* LRCK half cycle wait */
 166
 167     /* IIS Tx off */
 168     I2STXCOM = (1 << 3) |   /* 1 = transmit mode on */
 169                (0 << 2) |   /* 1 = I2S interface enable */
 170                (1 << 1) |   /* 1 = DMA request enable */
 171                (0 << 0);    /* 0 = LRCK on */
 172 }
 173
 174 /* pause playback by disabling further DMA requests */
 175 void pcm_play_dma_pause(bool pause)
 176 {
 177     if (pause) {
 178         I2STXCOM &= ~(1 << 1);  /* DMA request enable */
 179     }
 180     else {
 181         I2STXCOM |= (1 << 1);   /* DMA request enable */
 182     }
 183 }
 184
 185 void pcm_play_dma_init(void)
 186 {
 187     /* configure IIS pins */
 188 #ifdef IPOD_NANO2G
 189     PCON5 = (PCON5 & ~(0xFFFFF000)) | 0x22220000;
 190     PCON6 = (PCON6 & ~(0x0F000000)) | 0x02000000;
 191 #else
 192     PCON7 = (PCON7 & ~(0x0FFFFF00)) | 0x02222200;
 193 #endif
 194
 195     /* enable clock to the IIS module */
 196     PWRCON &= ~(1 << 6);
 197
 198     audiohw_preinit();
 199 }
 200
 201 void pcm_postinit(void)
 202 {
 203     audiohw_postinit();
 204 }
 205
 206 /* set the configured PCM frequency */
 207 void pcm_dma_apply_settings(void)
 208 {
 209   //    audiohw_set_frequency(pcm_sampr);
 210
 211     struct div_entry div = div_table[pcm_fsel];
 212
 213     PLLCON &= ~4;
 214     PLLCON &= ~0x10;
 215     PLLCON &= 0x3f;
 216     PLLCON |= 4;
 217
 218     /* configure PLL1 and MCLK for the desired sample rate */
 219 #ifdef IPOD_NANO2G
 220     PLL1PMS = (2 << 16) | /* PDIV */
 221               (12 << 8) | /* MDIV */
 222               (2 << 0);   /* SDIV */
 223     PLL1LCNT = 0x4d2;
 224 #else
 225     PLL1PMS = (div.pdiv << 16) |
 226               (div.mdiv << 8) |
 227               (div.sdiv << 0);
 228     PLL1LCNT = 7500;    /* no idea what to put here */
 229 #endif
 230
 231     /* enable PLL1 and wait for lock */
 232     PLLCON |= (1 << 1);
 233     while ((PLLLOCK & (1 << 1)) == 0);
 234
 235     /* configure MCLK */
 236     CLKCON = (CLKCON & ~(0xFF)) |
 237              (0 << 7) |         /* MCLK_MASK */
 238              (2 << 5) |         /* MCLK_SEL = PLL2 */
 239              (1 << 4) |         /* MCLK_DIV_ON */
 240 #ifdef IPOD_NANO2G
 241              (3 - 1);           /* MCLK_DIV_VAL */
 242 #else
 243              (div.cdiv - 1);    /* MCLK_DIV_VAL */
 244 #endif
 245 }
 246
 247 size_t pcm_get_bytes_waiting(void)
 248 {
 249     return DMATCNT0 * 2;
 250 }
 251
 252 const void * pcm_play_dma_get_peak_buffer(int *count)
 253 {
 254     /* currently not supported */
 255     *count = 0;
 256     return 0;
 257 }
 258
 259 #ifdef HAVE_PCM_DMA_ADDRESS
 260 void * pcm_dma_addr(void *addr)
 261 {
 262     if (addr != NULL)
 263         addr = UNCACHED_ADDR(addr);
 264     return addr;
 265 }
 266 #endif
 267
 268
 269 /****************************************************************************
 270  ** Recording DMA transfer
 271  **/
 272 #ifdef HAVE_RECORDING
 273 void pcm_rec_lock(void)
 274 {
 275 }
 276
 277 void pcm_rec_unlock(void)
 278 {
 279 }
 280
 281 void pcm_record_more(void *start, size_t size)
 282 {
 283     (void)start;
 284     (void)size;
 285 }
 286
 287 void pcm_rec_dma_stop(void)
 288 {
 289 }
 290
 291 void pcm_rec_dma_start(void *addr, size_t size)
 292 {
 293     (void)addr;
 294     (void)size;
 295 }
 296
 297 void pcm_rec_dma_close(void)
 298 {
 299 }
 300
 301
 302 void pcm_rec_dma_init(void)
 303 {
 304 }
 305
 306
 307 const void * pcm_rec_dma_get_peak_buffer(int *count)
 308 {
 309     (void)count;
 310 }
 311
 312 #endif /* HAVE_RECORDING */
 313