firmware/target/arm/imx31/gigabeat-s/system-imx31.c

   1 #include "kernel.h"
   2 #include "system.h"
   3 #include "panic.h"
   4 #include "avic-imx31.h"
   5 #include "gpio-imx31.h"
   6 #include "mmu-imx31.h"
   7 #include "system-target.h"
   8 #include "lcd.h"
   9 #include "serial-imx31.h"
  10 #include "debug.h"
  11
  12 int system_memory_guard(int newmode)
  13 {
  14     (void)newmode;
  15     return 0;
  16 }
  17
  18 void system_reboot(void)
  19 {
  20 }
  21
  22 void system_init(void)
  23 {
  24     /* MCR WFI enables wait mode */
  25     CLKCTL_CCMR &= ~(3 << 14);
  26     avic_init();
  27     gpio_init();
  28 }
  29
  30 void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value, uint32_t mask)
  31 {
  32     value &= mask;
  33     mask = ~mask;
  34
  35     int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
  36     *reg_p = (*reg_p & mask) | value;
  37     restore_interrupt(oldlevel);
  38 }
  39
  40 #ifdef BOOTLOADER
  41 void system_prepare_fw_start(void)
  42 {
  43     disable_interrupt(IRQ_FIQ_STATUS);
  44     avic_disable_int(ALL);
  45     tick_stop();
  46 }
  47 #endif
  48
  49 inline void dumpregs(void)
  50 {
  51         asm volatile ("mov %0,r0\n\t"
  52                                   "mov %1,r1\n\t"
  53                                   "mov %2,r2\n\t"
  54                                   "mov %3,r3":
  55                                   "=r"(regs.r0),"=r"(regs.r1),
  56                                   "=r"(regs.r2),"=r"(regs.r3):);
  57
  58     asm volatile ("mov %0,r4\n\t"
  59                                   "mov %1,r5\n\t"
  60                                   "mov %2,r6\n\t"
  61                                   "mov %3,r7":
  62                                   "=r"(regs.r4),"=r"(regs.r5),
  63                                   "=r"(regs.r6),"=r"(regs.r7):);
  64
  65     asm volatile ("mov %0,r8\n\t"
  66                                   "mov %1,r9\n\t"
  67                                   "mov %2,r10\n\t"
  68                                   "mov %3,r12":
  69                                   "=r"(regs.r8),"=r"(regs.r9),
  70                                   "=r"(regs.r10),"=r"(regs.r11):);
  71
  72         asm volatile ("mov %0,r12\n\t"
  73                                    "mov %1,sp\n\t"
  74                                    "mov %2,lr\n\t"
  75                                    "mov %3,pc\n"
  76                                    "sub %3,%3,#8":
  77                                    "=r"(regs.r12),"=r"(regs.sp),
  78                                    "=r"(regs.lr),"=r"(regs.pc):);
  79 #ifdef HAVE_SERIAL
  80     dprintf("Register Dump :\n");
  81         dprintf("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
  82     dprintf("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
  83         dprintf("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
  84         dprintf("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
  85         //dprintf("CPSR=0x%x\t\n",regs.cpsr);
  86 #endif
  87         DEBUGF("Register Dump :\n");
  88         DEBUGF("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
  89     DEBUGF("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
  90         DEBUGF("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
  91         DEBUGF("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
  92         //DEBUGF("CPSR=0x%x\t\n",regs.cpsr);
  93
  94  }
  95
  96 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
  97
  98 void set_cpu_frequency(long frequency)
  99 {
 100     (void)freqency;
 101 }
 102
 103 #endif