firmware/target/arm/imx31/gigabeat-s/system-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by James Espinoza
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "kernel.h"
  23 #include "system.h"
  24 #include "panic.h"
  25 #include "avic-imx31.h"
  26 #include "gpio-imx31.h"
  27 #include "mmu-imx31.h"
  28 #include "system-target.h"
  29 #include "lcd.h"
  30 #include "serial-imx31.h"
  31 #include "debug.h"
  32 #include "ccm-imx31.h"
  33 #include "mc13783.h"
  34
  35 static unsigned long product_rev;
  36 static unsigned long system_rev;
  37
  38 /** IC revision info routines **/
  39 unsigned int iim_system_rev(void)
  40 {
  41     return system_rev & IIM_SREV_SREV;
  42 }
  43
  44 unsigned int iim_prod_rev(void)
  45 {
  46     return product_rev;
  47 }
  48
  49 static void iim_init(void)
  50 {
  51     /* Initialize the IC revision info (required by SDMA) */
  52     ccm_module_clock_gating(CG_IIM, CGM_ON_RUN_WAIT);
  53     product_rev = IIM_PREV;
  54     system_rev = IIM_SREV;
  55 }
  56
  57 /** Watchdog timer routines **/
  58
  59 /* Initialize the watchdog timer */
  60 void watchdog_init(unsigned int half_seconds)
  61 {
  62     uint16_t wcr = ((half_seconds << WDOG_WCR_WT_POS) & WDOG_WCR_WT) |
  63                    WDOG_WCR_WOE |       /* WDOG output enabled */
  64                    WDOG_WCR_WDA |       /* WDOG assertion - no effect */
  65                    WDOG_WCR_SRS |       /* System reset - no effect */
  66                    WDOG_WCR_WRE;        /* Generate a WDOG signal */
  67
  68     ccm_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT);
  69
  70     WDOG_WCR = wcr;
  71     WDOG_WSR = 0x5555;
  72     WDOG_WCR = wcr | WDOG_WCR_WDE; /* Enable timer - hardware does
  73                                       not allow a disable now */
  74     WDOG_WSR = 0xaaaa;
  75 }
  76
  77 /* Service the watchdog timer */
  78 void watchdog_service(void)
  79 {
  80     WDOG_WSR = 0x5555;
  81     WDOG_WSR = 0xaaaa;
  82 }
  83
  84 /** GPT timer routines - basis for udelay **/
  85
  86 /* Start the general-purpose timer (1MHz) */
  87 void gpt_start(void)
  88 {
  89     ccm_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT);
  90     unsigned int ipg_mhz = ccm_get_ipg_clk() / 1000000;
  91
  92     GPTCR &= ~GPTCR_EN; /* Disable counter */
  93     GPTCR |= GPTCR_SWR; /* Reset module */
  94     while (GPTCR & GPTCR_SWR);
  95     /* No output
  96      * No capture
  97      * Enable in run mode only (doesn't tick while in WFI)
  98      * Freerun mode (count to 0xFFFFFFFF and roll-over to 0x00000000)
  99      */
 100     GPTCR = GPTCR_FRR | GPTCR_CLKSRC_IPG_CLK;
 101     GPTPR = ipg_mhz - 1;
 102     GPTCR |= GPTCR_EN;
 103 }
 104
 105 /* Stop the general-purpose timer */
 106 void gpt_stop(void)
 107 {
 108     GPTCR &= ~GPTCR_EN;
 109 }
 110
 111 int system_memory_guard(int newmode)
 112 {
 113     (void)newmode;
 114     return 0;
 115 }
 116
 117 void system_reboot(void)
 118 {
 119     /* Multi-context so no SPI available (WDT?)  */
 120     while (1);
 121 }
 122
 123 void system_exception_wait(void)
 124 {
 125     /* Called in many contexts so button reading may be a chore */
 126     avic_disable_int(INT_ALL);
 127     core_idle();
 128     while (1);
 129 }
 130
 131 void system_init(void)
 132 {
 133     static const int disable_clocks[] =
 134     {
 135         /* CGR0 */
 136         CG_SD_MMC1,
 137         CG_SD_MMC2,
 138         CG_IIM,
 139         CG_SDMA,
 140         CG_CSPI3,
 141         CG_RNG,
 142         CG_UART1,
 143         CG_UART2,
 144         CG_SSI1,
 145         CG_I2C1,
 146         CG_I2C2,
 147         CG_I2C3,
 148
 149         /* CGR1 */
 150         CG_HANTRO,
 151         CG_MEMSTICK1,
 152         CG_MEMSTICK2,
 153         CG_CSI,
 154         CG_RTC,
 155         CG_WDOG,
 156         CG_PWM,
 157         CG_SIM,
 158         CG_ECT,
 159         CG_USBOTG,
 160         CG_KPP,
 161         CG_UART3,
 162         CG_UART4,
 163         CG_UART5,
 164         CG_1_WIRE,
 165
 166         /* CGR2 */
 167         CG_SSI2,
 168         CG_CSPI1,
 169         CG_CSPI2,
 170         CG_GACC,
 171         CG_RTIC,
 172         CG_FIR
 173     };
 174
 175     unsigned int i;
 176
 177     /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */
 178     imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM);
 179
 180     iim_init();
 181
 182     imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK);
 183     imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK);
 184     imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP);
 185     imx31_regclr32(&UCR1_1, EUARTUCR1_UARTEN);
 186     imx31_regclr32(&UCR1_2, EUARTUCR1_UARTEN);
 187     imx31_regclr32(&UCR1_3, EUARTUCR1_UARTEN);
 188     imx31_regclr32(&UCR1_4, EUARTUCR1_UARTEN);
 189     imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN);
 190
 191     for (i = 0; i < ARRAYLEN(disable_clocks); i++)
 192         ccm_module_clock_gating(disable_clocks[i], CGM_OFF);
 193
 194     avic_init();
 195     gpt_start();
 196     gpio_init();
 197 }
 198
 199 void  __attribute__((naked)) imx31_regmod32(volatile uint32_t *reg_p,
 200                                             uint32_t value,
 201                                             uint32_t mask)
 202 {
 203     asm volatile("and    r1, r1, r2 \n"
 204                  "mrs    ip, cpsr   \n"
 205                  "cpsid  if         \n"
 206                  "ldr    r3, [r0]   \n"
 207                  "bic    r3, r3, r2 \n"
 208                  "orr    r3, r3, r1 \n"
 209                  "str    r3, [r0]   \n"
 210                  "msr    cpsr_c, ip \n"
 211                  "bx     lr         \n");
 212     (void)reg_p; (void)value; (void)mask;
 213 }
 214
 215 void __attribute__((naked)) imx31_regset32(volatile uint32_t *reg_p,
 216                                            uint32_t mask)
 217 {
 218     asm volatile("mrs    r3, cpsr   \n"
 219                  "cpsid  if         \n"
 220                  "ldr    r2, [r0]   \n"
 221                  "orr    r2, r2, r1 \n"
 222                  "str    r2, [r0]   \n"
 223                  "msr    cpsr_c, r3 \n"
 224                  "bx     lr         \n");
 225     (void)reg_p; (void)mask;
 226 }
 227
 228 void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p,
 229                                            uint32_t mask)
 230 {
 231     asm volatile("mrs    r3, cpsr   \n"
 232                  "cpsid  if         \n"
 233                  "ldr    r2, [r0]   \n"
 234                  "bic    r2, r2, r1 \n"
 235                  "str    r2, [r0]   \n"
 236                  "msr    cpsr_c, r3 \n"
 237                  "bx     lr         \n");
 238     (void)reg_p; (void)mask;
 239 }
 240
 241 #ifdef BOOTLOADER
 242 void system_prepare_fw_start(void)
 243 {
 244     disable_interrupt(IRQ_FIQ_STATUS);
 245     avic_disable_int(INT_ALL);
 246     mc13783_close();
 247     tick_stop();
 248 }
 249 #endif
 250
 251 inline void dumpregs(void)
 252 {
 253         asm volatile ("mov %0,r0\n\t"
 254                                   "mov %1,r1\n\t"
 255                                   "mov %2,r2\n\t"
 256                                   "mov %3,r3":
 257                                   "=r"(regs.r0),"=r"(regs.r1),
 258                                   "=r"(regs.r2),"=r"(regs.r3):);
 259
 260     asm volatile ("mov %0,r4\n\t"
 261                                   "mov %1,r5\n\t"
 262                                   "mov %2,r6\n\t"
 263                                   "mov %3,r7":
 264                                   "=r"(regs.r4),"=r"(regs.r5),
 265                                   "=r"(regs.r6),"=r"(regs.r7):);
 266
 267     asm volatile ("mov %0,r8\n\t"
 268                                   "mov %1,r9\n\t"
 269                                   "mov %2,r10\n\t"
 270                                   "mov %3,r12":
 271                                   "=r"(regs.r8),"=r"(regs.r9),
 272                                   "=r"(regs.r10),"=r"(regs.r11):);
 273
 274         asm volatile ("mov %0,r12\n\t"
 275                                    "mov %1,sp\n\t"
 276                                    "mov %2,lr\n\t"
 277                                    "mov %3,pc\n"
 278                                    "sub %3,%3,#8":
 279                                    "=r"(regs.r12),"=r"(regs.sp),
 280                                    "=r"(regs.lr),"=r"(regs.pc):);
 281 #ifdef HAVE_SERIAL
 282     dprintf("Register Dump :\n");
 283         dprintf("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
 284     dprintf("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
 285         dprintf("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
 286         dprintf("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
 287         //dprintf("CPSR=0x%x\t\n",regs.cpsr);
 288 #endif
 289         DEBUGF("Register Dump :\n");
 290         DEBUGF("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
 291     DEBUGF("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
 292         DEBUGF("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
 293         DEBUGF("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
 294         //DEBUGF("CPSR=0x%x\t\n",regs.cpsr);
 295
 296  }
 297
 298 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 299
 300 void set_cpu_frequency(long frequency)
 301 {
 302     (void)freqency;
 303 }
 304
 305 #endif