firmware/target/arm/s5l8700/pcm-s5l8700.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2009 Bertrik Sikken
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include <string.h>
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "audio.h"
  26 #include "s5l8700.h"
  27 #include "panic.h"
  28 #include "audiohw.h"
  29 #include "pcm.h"
  30 #include "pcm_sampr.h"
  31 #include "dma-target.h"
  32 #include "mmu-arm.h"
  33
  34 /*  Driver for the IIS/PCM part of the s5l8700 using DMA
  35
  36     Notes:
  37     - pcm_play_dma_pause is untested, not sure if implemented the right way
  38     - pcm_play_dma_stop is untested, not sure if implemented the right way
  39     - recording is not implemented
  40 */
  41
  42 static volatile int locked = 0;
  43 static const int zerosample = 0;
  44 static unsigned char dblbuf[1024] IBSS_ATTR;
  45 static const unsigned char* queuedbuf;
  46 static size_t queuedsize;
  47 static const unsigned char* nextbuf;
  48 static size_t nextsize;
  49
  50 static const struct div_entry {
  51     int             pdiv, mdiv, sdiv, cdiv;
  52 } div_table[HW_NUM_FREQ] = {
  53 #ifdef IPOD_NANO2G
  54     [HW_FREQ_11] = {   0,   41,    3,    8},
  55     [HW_FREQ_22] = {   0,   41,    3,    4},
  56     [HW_FREQ_44] = {   0,   41,    3,    2},
  57     [HW_FREQ_88] = {   0,   41,    3,    1},
  58     [HW_FREQ_8 ] = {   0,    2,    1,    9},
  59     [HW_FREQ_16] = {   0,    2,    0,    9},
  60     [HW_FREQ_32] = {   2,    2,    0,    9},
  61     [HW_FREQ_64] = {   6,    2,    0,    9},
  62     [HW_FREQ_12] = {   0,    2,    2,    3},
  63     [HW_FREQ_24] = {   0,    2,    1,    3},
  64     [HW_FREQ_48] = {   0,    2,    0,    3},
  65     [HW_FREQ_96] = {   2,    2,    0,    3},
  66 #else
  67 /* table of recommended PLL/MCLK dividers for mode 256Fs from the datasheet */
  68     [HW_FREQ_11] = {  26,  189,    3,    8},
  69     [HW_FREQ_22] = {  50,   98,    2,    8},
  70     [HW_FREQ_44] = {  37,  151,    1,    9},
  71     [HW_FREQ_88] = {  50,   98,    1,    4},
  72 #if 0   /* disabled because the codec driver does not support it (yet) */
  73     [HW_FREQ_8 ] = {  28,  192,    3,   12},
  74     [HW_FREQ_16] = {  28,  192,    3,    6},
  75     [HW_FREQ_32] = {  28,  192,    2,    6},
  76     [HW_FREQ_12] = {  28,  192,    3,    8},
  77     [HW_FREQ_24] = {  28,  192,    2,    8},
  78     [HW_FREQ_48] = {  28,  192,    2,    4},
  79     [HW_FREQ_96] = {  28,  192,    1,    4},
  80 #endif
  81 #endif
  82 };
  83
  84 /* Mask the DMA interrupt */
  85 void pcm_play_lock(void)
  86 {
  87     if (locked++ == 0) {
  88         INTMSK &= ~(1 << 10);
  89     }
  90 }
  91
  92 /* Unmask the DMA interrupt if enabled */
  93 void pcm_play_unlock(void)
  94 {
  95     if (--locked == 0) {
  96         INTMSK |= (1 << 10);
  97     }
  98 }
  99
 100 void INT_DMA(void) ICODE_ATTR;
 101 void INT_DMA(void)
 102 {
 103     DMACOM0 = 7;
 104     while (!(DMACON0 & (1 << 18)))
 105     {
 106         if (queuedsize)
 107         {
 108             memcpy(dblbuf, queuedbuf, queuedsize);
 109             DMABASE0 = (unsigned int)dblbuf;
 110             DMATCNT0 = queuedsize / 2 - 1;
 111             queuedsize = 0;
 112         }
 113         else
 114         {
 115             if (!nextsize) pcm_play_get_more_callback((void**)&nextbuf, &nextsize);
 116             if (!nextsize) break;
 117             queuedsize = MIN(sizeof(dblbuf), nextsize / 2);
 118             nextsize -= queuedsize;
 119             queuedbuf = nextbuf + nextsize;
 120             DMABASE0 = (unsigned int)nextbuf;
 121             DMATCNT0 = nextsize / 2 - 1;
 122             nextsize = 0;
 123         }
 124         clean_dcache();
 125         DMACOM0 = 4;
 126         DMACOM0 = 7;
 127     }
 128 }
 129
 130 void pcm_play_dma_start(const void* addr, size_t size)
 131 {
 132     /* DMA channel on */
 133     nextbuf = (const unsigned char*)addr;
 134     nextsize = size;
 135     queuedsize = 0;
 136     DMABASE0 = (unsigned int)(&zerosample);
 137     DMATCNT0 = 0;
 138     DMACOM0 = 4;
 139
 140     /* IIS Tx clock on */
 141     I2SCLKCON = (1 << 0);   /* 1 = power on */
 142
 143     /* IIS Tx on */
 144     I2STXCOM = (1 << 3) |   /* 1 = transmit mode on */
 145                (1 << 2) |   /* 1 = I2S interface enable */
 146                (1 << 1) |   /* 1 = DMA request enable */
 147                (0 << 0);    /* 0 = LRCK on */
 148 }
 149
 150 void pcm_play_dma_stop(void)
 151 {
 152     /* DMA channel off */
 153     DMACOM0 = 5;
 154
 155     /* IIS Tx off */
 156     I2STXCOM = (1 << 3) |   /* 1 = transmit mode on */
 157                (0 << 2) |   /* 1 = I2S interface enable */
 158                (1 << 1) |   /* 1 = DMA request enable */
 159                (0 << 0);    /* 0 = LRCK on */
 160 }
 161
 162 /* pause playback by disabling the I2S interface */
 163 void pcm_play_dma_pause(bool pause)
 164 {
 165     if (pause) {
 166         I2STXCOM |= (1 << 0);   /* LRCK off */
 167     }
 168     else {
 169         I2STXCOM &= ~(1 << 0);  /* LRCK on */
 170     }
 171 }
 172
 173 static void pcm_dma_set_freq(enum hw_freq_indexes idx)
 174 {
 175     struct div_entry div = div_table[idx];
 176
 177     /* configure PLL1 and MCLK for the desired sample rate */
 178     PLL1PMS = (div.pdiv << 16) |
 179               (div.mdiv << 8) |
 180               (div.sdiv << 0);
 181     PLL1LCNT = 280;    /* 150 microseconds */
 182
 183     /* enable PLL1 and wait for lock */
 184     PLLCON |= 1 << 1;
 185     while ((PLLLOCK & (1 << 1)) == 0);
 186
 187     /* configure MCLK */
 188     CLKCON = (CLKCON & ~(0xFF)) |
 189              (0 << 7) |         /* MCLK_MASK */
 190              (2 << 5) |         /* MCLK_SEL = PLL1 */
 191              (1 << 4) |         /* MCLK_DIV_ON */
 192              (div.cdiv - 1);    /* MCLK_DIV_VAL */
 193 }
 194
 195 void pcm_play_dma_init(void)
 196 {
 197     /* configure IIS pins */
 198 #ifdef IPOD_NANO2G
 199     PCON5 = (PCON5 & ~(0xFFFF0000)) | 0x77720000;
 200     PCON6 = (PCON6 & ~(0x0F000000)) | 0x02000000;
 201 #else
 202     PCON7 = (PCON7 & ~(0x0FFFFF00)) | 0x02222200;
 203 #endif
 204
 205     /* configure DMA channel */
 206     DMACON0 = (0 << 30) |       /* DEVSEL */
 207               (1 << 29) |       /* DIR */
 208               (0 << 24) |       /* SCHCNT */
 209               (1 << 22) |       /* DSIZE */
 210               (0 << 19) |       /* BLEN */
 211               (0 << 18) |       /* RELOAD */
 212               (0 << 17) |       /* HCOMINT */
 213               (1 << 16) |       /* WCOMINT */
 214               (0 << 0);         /* OFFSET */
 215
 216     /* Enable the DMA IRQ */
 217     INTMSK |= (1 << 10);
 218
 219     /* setup PLL */
 220     pcm_dma_set_freq(HW_FREQ_44);
 221
 222     /* enable clock to the IIS module */
 223     PWRCON &= ~(1 << 6);
 224
 225     /* configure IIS core */
 226 #ifdef IPOD_NANO2G
 227     I2STXCON = (1 << 20) |  /* undocumented */
 228                (0 << 16) |  /* burst length */
 229                (0 << 15) |  /* 0 = falling edge */
 230                (0 << 13) |  /* 0 = basic I2S format */
 231                (0 << 12) |  /* 0 = MSB first */
 232                (0 << 11) |  /* 0 = left channel for low polarity */
 233                (3 << 8) |   /* MCLK divider */
 234                (0 << 5) |   /* 0 = 16-bit */
 235                (2 << 3) |   /* bit clock per frame */
 236                (1 << 0);    /* channel index */
 237 #else
 238     I2STXCON = (DMA_IISOUT_BLEN << 16) |  /* burst length */
 239                (0 << 15) |  /* 0 = falling edge */
 240                (0 << 13) |  /* 0 = basic I2S format */
 241                (0 << 12) |  /* 0 = MSB first */
 242                (0 << 11) |  /* 0 = left channel for low polarity */
 243                (3 << 8) |   /* MCLK divider */
 244                (0 << 5) |   /* 0 = 16-bit */
 245                (0 << 3) |   /* bit clock per frame */
 246                (1 << 0);    /* channel index */
 247 #endif
 248
 249     audiohw_preinit();
 250 }
 251
 252 void pcm_postinit(void)
 253 {
 254     audiohw_postinit();
 255 }
 256
 257 /* set the configured PCM frequency */
 258 void pcm_dma_apply_settings(void)
 259 {
 260     pcm_dma_set_freq(pcm_fsel);
 261 }
 262
 263 size_t pcm_get_bytes_waiting(void)
 264 {
 265     return (nextsize + DMACTCNT0 + 2) << 1;
 266 }
 267
 268 const void * pcm_play_dma_get_peak_buffer(int *count)
 269 {
 270     *count = DMACTCNT0 >> 1;
 271     return (void *)(((DMACADDR0 + 2) & ~3) | 0x40000000);
 272 }
 273
 274 #ifdef HAVE_PCM_DMA_ADDRESS
 275 void * pcm_dma_addr(void *addr)
 276 {
 277     if (addr != NULL)
 278         addr = (void*)((uintptr_t)addr | 0x40000000);
 279     return addr;
 280 }
 281 #endif
 282
 283
 284 /****************************************************************************
 285  ** Recording DMA transfer
 286  **/
 287 #ifdef HAVE_RECORDING
 288 void pcm_rec_lock(void)
 289 {
 290 }
 291
 292 void pcm_rec_unlock(void)
 293 {
 294 }
 295
 296 void pcm_rec_dma_stop(void)
 297 {
 298 }
 299
 300 void pcm_rec_dma_start(void *addr, size_t size)
 301 {
 302     (void)addr;
 303     (void)size;
 304 }
 305
 306 void pcm_rec_dma_close(void)
 307 {
 308 }
 309
 310
 311 void pcm_rec_dma_init(void)
 312 {
 313 }
 314
 315
 316 const void * pcm_rec_dma_get_peak_buffer(void)
 317 {
 318     return NULL;
 319 }
 320
 321 #endif /* HAVE_RECORDING */