firmware/export/s3c2440.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by Marcoen Hirschberg
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #ifndef __S3C2440_H__
  20 #define __S3C2440_H__
  21
  22 #define LCD_BUFFER_SIZE (320*240*2)
  23 #define TTB_SIZE (0x4000)
  24 /* must be 16Kb (0x4000) aligned */
  25 #define TTB_BASE   ((unsigned int *)(0x30000000 + (32*1024*1024) - TTB_SIZE)) /* End of memory */
  26 #define FRAME   ((short *) ((char *)TTB_BASE - LCD_BUFFER_SIZE))  /* Right before TTB */
  27
  28 /* Memory Controllers */
  29
  30 #define BWSCON (*(volatile int *)0x48000000) /* Bus width & wait status control */
  31 #define BANKCON0 (*(volatile int *)0x48000004) /* Boot ROM control */
  32 #define BANKCON1 (*(volatile int *)0x48000008) /* BANK1 control */
  33 #define BANKCON2 (*(volatile int *)0x4800000C) /* BANK2 control */
  34 #define BANKCON3 (*(volatile int *)0x48000010) /* BANK3 control */
  35 #define BANKCON4 (*(volatile int *)0x48000014) /* BANK4 control */
  36 #define BANKCON5 (*(volatile int *)0x48000018) /* BANK5 control */
  37 #define BANKCON6 (*(volatile int *)0x4800001C) /* BANK6 control */
  38 #define BANKCON7 (*(volatile int *)0x48000020) /* BANK7 control */
  39 #define REFRESH (*(volatile int *)0x48000024) /* DRAM/SDRAM refresh control */
  40 #define BANKSIZE (*(volatile int *)0x48000028) /* Flexible bank size */
  41 #define MRSRB6 (*(volatile int *)0x4800002C) /* Mode register set for SDRAM BANK6 */
  42 #define MRSRB7 (*(volatile int *)0x48000030) /* Mode register set for SDRAM BANK7 */
  43
  44 /* USB Host Controller */
  45
  46 /* Control and status group */
  47 #define HcRevision (*(volatile int *)0x49000000)
  48 #define HcControl (*(volatile int *)0x49000004)
  49 #define HcCommonStatus (*(volatile int *)0x49000008)
  50 #define HcInterruptStatus (*(volatile int *)0x4900000C)
  51 #define HcInterruptEnable (*(volatile int *)0x49000010)
  52 #define HcInterruptDisable (*(volatile int *)0x49000014)
  53 /* Memory pointer group */
  54 #define HcHCCA (*(volatile int *)0x49000018)
  55 #define HcPeriodCuttentED (*(volatile int *)0x4900001C)
  56 #define HcControlHeadED (*(volatile int *)0x49000020)
  57 #define HcControlCurrentED (*(volatile int *)0x49000024)
  58 #define HcBulkHeadED (*(volatile int *)0x49000028)
  59 #define HcBulkCurrentED (*(volatile int *)0x4900002C)
  60 /* Frame counter group */
  61 #define HcDoneHead (*(volatile int *)0x49000030)
  62 #define HcRmInterval (*(volatile int *)0x49000034)
  63 #define HcFmRemaining (*(volatile int *)0x49000038)
  64 #define HcFmNumber (*(volatile int *)0x4900003C)
  65 #define HcPeriodicStart (*(volatile int *)0x49000040)
  66 #define HcLSThreshold (*(volatile int *)0x49000044)
  67 /* Root hub group */
  68 #define HcRhDescriptorA (*(volatile int *)0x49000048)
  69 #define HcRhDescriptorB (*(volatile int *)0x4900004C)
  70 #define HcRhStatus (*(volatile int *)0x49000050)
  71 #define HcRhPortStatus1 (*(volatile int *)0x49000054)
  72 #define HcRhPortStatus2 (*(volatile int *)0x49000058)
  73
  74 /* Interrupt Controller */
  75
  76 #define SRCPND (*(volatile int *)0x4A000000) /* Interrupt request status */
  77 #define INTMOD (*(volatile int *)0x4A000004) /* Interrupt mode control */
  78 #define INTMSK (*(volatile int *)0x4A000008) /* Interrupt mask control */
  79 #define PRIORITY (*(volatile int *)0x4A00000C) /* IRQ priority control */
  80 #define INTPND (*(volatile int *)0x4A000010) /* Interrupt request status */
  81 #define INTOFFSET (*(volatile int *)0x4A000014) /* Interrupt request source offset */
  82 #define SUBSRCPND (*(volatile int *)0x4A000018) /* Sub source pending */
  83 #define INTSUBMSK (*(volatile int *)0x4A00001C) /* Interrupt sub mask */
  84
  85 /* Interrupt indexes - INTOFFSET - IRQ mode only */
  86 /* Arbiter 5 => Arbiter 6 Req 5 */
  87 #define ADC_INTOFFSET       31 /* REQ4 */
  88 #define RTC_INTOFFSET       30 /* REQ3 */
  89 #define SPI1_INTOFFSET      29 /* REQ2 */
  90 #define UART0_INTOFFSET     28 /* REQ1 */
  91 /* Arbiter 4 => Arbiter 6 Req 4 */
  92 #define IIC_INTOFFSET       27 /* REQ5 */
  93 #define USBH_INTOFFSET      26 /* REQ4 */
  94 #define USBD_INTOFFSET      25 /* REQ3 */
  95 #define NFCON_INTOFFSET     24 /* REQ2 */
  96 #define UART1_INTOFFSET     23 /* REQ1 */
  97 #define SPI0_INTOFFSET      22 /* REQ0 */
  98 /* Arbiter 3 => Arbiter 6 Req 3  */
  99 #define SDI_INTOFFSET       21 /* REQ5 */
 100 #define DMA3_INTOFFSET      20 /* REQ4 */
 101 #define DMA2_INTOFFSET      19 /* REQ3 */
 102 #define DMA1_INTOFFSET      18 /* REQ2 */
 103 #define DMA0_INTOFFSET      17 /* REQ1 */
 104 #define LCD_INTOFFSET       16 /* REQ0 */
 105 /* Arbiter 2 => Arbiter 6 Req 2 */
 106 #define UART2_INTOFFSET     15 /* REQ5 */
 107 #define TIMER4_INTOFFSET    14 /* REQ4 */
 108 #define TIMER3_INTOFFSET    13 /* REQ3 */
 109 #define TIMER2_INTOFFSET    12 /* REQ2 */
 110 #define TIMER1_INTOFFSET    11 /* REQ1 */
 111 #define TIMER0_INTOFFSET    10 /* REQ0 */
 112 /* Arbiter 1 => Arbiter 6 Req 1  */
 113 #define WDT_AC97_INTOFFSET   9 /* REQ5 */
 114 #define TICK_INTOFFSET       8 /* REQ4 */
 115 #define nBATT_FLT_INTOFFSET  7 /* REQ3 */
 116 #define CAM_INTOFFSET        6 /* REQ2 */
 117 #define EINT8_23_INTOFFSET   5 /* REQ1 */
 118 #define EINT4_7_INTOFFSET    4 /* REQ0 */
 119 /* Arbiter 0  => Arbiter 6 Req 0 */
 120 #define EINT3_INTOFFSET      3 /* REQ4 */
 121 #define EINT2_INTOFFSET      2 /* REQ3 */
 122 #define EINT1_INTOFFSET      1 /* REQ2 */
 123 #define EINT0_INTOFFSET      0 /* REQ1 */
 124
 125 /* Interrupt bitmasks - SRCPND, INTMOD, INTMSK, INTPND */
 126 /* Arbiter 5 => Arbiter 6 Req 5 */
 127 #define ADC_MASK       (1 << 31) /* REQ4 */
 128 #define RTC_MASK       (1 << 30) /* REQ3 */
 129 #define SPI1_MASK      (1 << 29) /* REQ2 */
 130 #define UART0_MASK     (1 << 28) /* REQ1 */
 131 /* Arbiter 4 => Arbiter 6 Req 4 */
 132 #define IIC_MASK       (1 << 27) /* REQ5 */
 133 #define USBH_MASK      (1 << 26) /* REQ4 */
 134 #define USBD_MASK      (1 << 25) /* REQ3 */
 135 #define NFCON_MASK     (1 << 24) /* REQ2 */
 136 #define UART1_MASK     (1 << 23) /* REQ1 */
 137 #define SPI0_MASK      (1 << 22) /* REQ0 */
 138 /* Arbiter 3 => Arbiter 6 Req 3  */
 139 #define SDI_MASK       (1 << 21) /* REQ5 */
 140 #define DMA3_MASK      (1 << 20) /* REQ4 */
 141 #define DMA2_MASK      (1 << 19) /* REQ3 */
 142 #define DMA1_MASK      (1 << 18) /* REQ2 */
 143 #define DMA0_MASK      (1 << 17) /* REQ1 */
 144 #define LCD_MASK       (1 << 16) /* REQ0 */
 145 /* Arbiter 2 => Arbiter 6 Req 2 */
 146 #define UART2_MASK     (1 << 15) /* REQ5 */
 147 #define TIMER4_MASK    (1 << 14) /* REQ4 */
 148 #define TIMER3_MASK    (1 << 13) /* REQ3 */
 149 #define TIMER2_MASK    (1 << 12) /* REQ2 */
 150 #define TIMER1_MASK    (1 << 11) /* REQ1 */
 151 #define TIMER0_MASK    (1 << 10) /* REQ0 */
 152 /* Arbiter 1 => Arbiter 6 Req 1  */
 153 #define WDT_AC97_MASK  (1 <<  9) /* REQ5 */
 154 #define TICK_MASK      (1 <<  8) /* REQ4 */
 155 #define nBATT_FLT_MASK (1 <<  7) /* REQ3 */
 156 #define CAM_MASK       (1 <<  6) /* REQ2 */
 157 #define EINT8_23_MASK  (1 <<  5) /* REQ1 */
 158 #define EINT4_7_MASK   (1 <<  4) /* REQ0 */
 159 /* Arbiter 0  => Arbiter 6 Req 0 */
 160 #define EINT3_MASK     (1 <<  3) /* REQ4 */
 161 #define EINT2_MASK     (1 <<  2) /* REQ3 */
 162 #define EINT1_MASK     (1 <<  1) /* REQ2 */
 163 #define EINT0_MASK     (1 <<  0) /* REQ1 */
 164
 165 /* DMA */
 166
 167 #define DISRC0 (*(volatile int *)0x4B000000) /* DMA 0 initial source */
 168 #define DISRCC0 (*(volatile int *)0x4B000004) /* DMA 0 initial source control */
 169 #define DIDST0 (*(volatile int *)0x4B000008) /* DMA 0 initial destination */
 170 #define DIDSTC0 (*(volatile int *)0x4B00000C) /* DMA 0 initial destination control */
 171 #define DCON0 (*(volatile int *)0x4B000010) /* DMA 0 control */
 172 #define DSTAT0 (*(volatile int *)0x4B000014) /* DMA 0 count */
 173 #define DCSRC0 (*(volatile int *)0x4B000018) /* DMA 0 current source */
 174 #define DCDST0 (*(volatile int *)0x4B00001C) /* DMA 0 current destination */
 175 #define DMASKTRIG0 (*(volatile int *)0x4B000020) /* DMA 0 mask trigger */
 176 #define DISRC1 (*(volatile int *)0x4B000040) /* DMA 1 initial source */
 177 #define DISRCC1 (*(volatile int *)0x4B000044) /* DMA 1 initial source control */
 178 #define DIDST1 (*(volatile int *)0x4B000048) /* DMA 1 initial destination */
 179 #define DIDSTC1 (*(volatile int *)0x4B00004C) /* DMA 1 initial destination control */
 180 #define DCON1 (*(volatile int *)0x4B000050) /* DMA 1 control */
 181 #define DSTAT1 (*(volatile int *)0x4B000054) /* DMA 1 count */
 182 #define DCSRC1 (*(volatile int *)0x4B000058) /* DMA 1 current source */
 183 #define DCDST1 (*(volatile int *)0x4B00005C) /* DMA 1 current destination */
 184 #define DMASKTRIG1 (*(volatile int *)0x4B000060) /* DMA 1 mask trigger */
 185 #define DISRC2 (*(volatile int *)0x4B000080) /* DMA 2 initial source */
 186 #define DISRCC2 (*(volatile int *)0x4B000084) /* DMA 2 initial source control */
 187 #define DIDST2 (*(volatile int *)0x4B000088) /* DMA 2 initial destination */
 188 #define DIDSTC2 (*(volatile int *)0x4B00008C) /* DMA 2 initial destination control */
 189 #define DCON2 (*(volatile int *)0x4B000090) /* DMA 2 control */
 190 #define DSTAT2 (*(volatile int *)0x4B000094) /* DMA 2 count */
 191 #define DCSRC2 (*(volatile int *)0x4B000098) /* DMA 2 current source */
 192 #define DCDST2 (*(volatile int *)0x4B00009C) /* DMA 2 current destination */
 193 #define DMASKTRIG2 (*(volatile int *)0x4B0000A0) /* DMA 2 mask trigger */
 194 #define DISRC3 (*(volatile int *)0x4B0000C0) /* DMA 3 initial source */
 195 #define DISRCC3 (*(volatile int *)0x4B0000C4) /* DMA 3 initial source control */
 196 #define DIDST3 (*(volatile int *)0x4B0000C8) /* DMA 3 initial destination */
 197 #define DIDSTC3 (*(volatile int *)0x4B0000CC) /* DMA 3 initial destination control */
 198 #define DCON3 (*(volatile int *)0x4B0000D0) /* DMA 3 control */
 199 #define DSTAT3 (*(volatile int *)0x4B0000D4) /* DMA 3 count */
 200 #define DCSRC3 (*(volatile int *)0x4B0000D8) /* DMA 3 current source */
 201 #define DCDST3 (*(volatile int *)0x4B0000DC) /* DMA 3 current destination */
 202 #define DMASKTRIG3 (*(volatile int *)0x4B0000E0) /* DMA 3 mask trigger */
 203
 204 /* Clock & Power Management */
 205
 206 #define LOCKTIME (*(volatile int *)0x4C000000) /* PLL lock time counter */
 207 #define MPLLCON (*(volatile int *)0x4C000004) /* MPLL control */
 208 #define UPLLCON (*(volatile int *)0x4C000008) /* UPLL control */
 209 #define CLKCON (*(volatile int *)0x4C00000C) /* Clock generator control */
 210 #define CLKSLOW (*(volatile int *)0x4C000010) /* Slow clock control */
 211 #define CLKDIVN (*(volatile int *)0x4C000014) /* Clock divider control */
 212 #define CAMDIVN (*(volatile int *)0x4C000018) /* Camera clock divider control */
 213
 214 /* LCD Controller */
 215
 216 #define LCDCON1 (*(volatile int *)0x4D000000) /* LCD control 1 */
 217 #define LCDCON2 (*(volatile int *)0x4D000004) /* LCD control 2 */
 218 #define LCDCON3 (*(volatile int *)0x4D000008) /* LCD control 3 */
 219 #define LCDCON4 (*(volatile int *)0x4D00000C) /* LCD control 4 */
 220 #define LCDCON5 (*(volatile int *)0x4D000010) /* LCD control 5 */
 221 #define LCDSADDR1 (*(volatile int *)0x4D000014) /* STN/TFT: frame buffer start address 1 */
 222 #define LCDSADDR2 (*(volatile int *)0x4D000018) /* STN/TFT: frame buffer start address 2 */
 223 #define LCDSADDR3 (*(volatile int *)0x4D00001C) /* STN/TFT: virtual screen address set */
 224 #define REDLUT (*(volatile int *)0x4D000020) /* STN: red lookup table */
 225 #define GREENLUT (*(volatile int *)0x4D000024) /* STN: green lookup table */
 226 #define BLUELUT (*(volatile int *)0x4D000028) /* STN: blue lookup table */
 227 #define DITHMODE (*(volatile int *)0x4D00004C) /* STN: dithering mode */
 228 #define TPAL (*(volatile int *)0x4D000050) /* TFT: temporary palette */
 229 #define LCDINTPND (*(volatile int *)0x4D000054) /* LCD interrupt pending */
 230 #define LCDSRCPND (*(volatile int *)0x4D000058) /* LCD interrupt source */
 231 #define LCDINTMSK (*(volatile int *)0x4D00005C) /* LCD interrupt mask */
 232 #define TCONSEL (*(volatile int *)0x4D000060) /* TCON(LPC3600/LCC3600) control */
 233
 234 /* NAND Flash */
 235
 236 #define NFCONF (*(volatile int *)0x4E000000) /* NAND flash configuration */
 237 #define NFCONT (*(volatile int *)0x4E000004) /* NAND flash control */
 238 #define NFCMD (*(volatile int *)0x4E000008) /* NAND flash command */
 239 #define NFADDR (*(volatile int *)0x4E00000C) /* NAND flash address */
 240 #define NFDATA (*(volatile int *)0x4E000010) /* NAND flash data */
 241 #define NFMECC0 (*(volatile int *)0x4E000014) /* NAND flash main area ECC0/1 */
 242 #define NFMECC1 (*(volatile int *)0x4E000018) /* NAND flash main area ECC2/3 */
 243 #define NFSECC (*(volatile int *)0x4E00001C) /* NAND flash spare area ECC */
 244 #define NFSTAT (*(volatile int *)0x4E000020) /* NAND flash operation status */
 245 #define NFESTAT0 (*(volatile int *)0x4E000024) /* NAND flash ECC status for I/O[7:0] */
 246 #define NFESTAT1 (*(volatile int *)0x4E000028) /* NAND flash ECC status for I/O[15:8] */
 247 #define NFMECCSTAT0 (*(volatile int *)0x4E00002C) /* NAND flash main area ECC0 status */
 248 #define NFMECCSTAT1 (*(volatile int *)0x4E000030) /* NAND flash main area ECC1 status */
 249 #define NFSECCSTAT (*(volatile int *)0x4E000034) /* NAND flash spare area ECC status */
 250 #define NFSBLK (*(volatile int *)0x4E000038) /* NAND flash start block address */
 251 #define NFEBLK (*(volatile int *)0x4E00003C) /* NAND flash end block address */
 252
 253 /* Camera Interface */
 254
 255 #define CISRCFMT (*(volatile int *)0x4F000000) /* Input source format */
 256 #define CIWDOFST (*(volatile int *)0x4F000004) /* Window offset register */
 257 #define CIGCTRL (*(volatile int *)0x4F000008) /* Global control register */
 258 #define CICOYSA1 (*(volatile int *)0x4F000018) /* Y 1st frame start address for codec DMA */
 259 #define CICOYSA2 (*(volatile int *)0x4F00001C) /* Y 2nd frame start address for codec DMA */
 260 #define CICOYSA3 (*(volatile int *)0x4F000020) /* Y 3nd frame start address for codec DMA */
 261 #define CICOYSA4 (*(volatile int *)0x4F000024) /* Y 4th frame start address for codec DMA */
 262 #define CICOCBSA1 (*(volatile int *)0x4F000028) /* Cb 1st frame start address for codec DMA */
 263 #define CICOCBSA2 (*(volatile int *)0x4F00002C) /* Cb 2nd frame start address for codec DMA */
 264 #define CICOCBSA3 (*(volatile int *)0x4F000030) /* Cb 3nd frame start address for codec DMA */
 265 #define CICOCBSA4 (*(volatile int *)0x4F000034) /* Cb 4th frame start address for codec DMA */
 266 #define CICOCRSA1 (*(volatile int *)0x4F000038) /* Cr 1st frame start address for codec DMA */
 267 #define CICOCRSA2 (*(volatile int *)0x4F00003C) /* Cr 2nd frame start address for codec DMA */
 268 #define CICOCRSA3 (*(volatile int *)0x4F000040) /* Cr 3nd frame start address for codec DMA */
 269 #define CICOCRSA4 (*(volatile int *)0x4F000044) /* Cr 4th frame start address for codec DMA */
 270 #define CICOTRGFMT (*(volatile int *)0x4F000048) /* Target image format of codec DMA */
 271 #define CICOCTRL (*(volatile int *)0x4F00004C
 272
 273 /* Codec DMA control related */
 274
 275 #define CICOSCPRERATIO (*(volatile int *)0x4F000050) /* Codec pre-scaler ratio control */
 276 #define CICOSCPREDST (*(volatile int *)0x4F000054) /* Codec pre-scaler destination format */
 277 #define CICOSCCTRL (*(volatile int *)0x4F000058) /* Codec main-scaler control */
 278 #define CICOTAREA (*(volatile int *)0x4F00005C) /* Codec scaler target area */
 279 #define CICOSTATUS (*(volatile int *)0x4F000064) /* Codec path status */
 280 #define CIPRCLRSA1 (*(volatile int *)0x4F00006C) /* RGB 1st frame start address for preview DMA */
 281 #define CIPRCLRSA2 (*(volatile int *)0x4F000070) /* RGB 2nd frame start address for preview DMA */
 282 #define CIPRCLRSA3 (*(volatile int *)0x4F000074) /* RGB 3nd frame start address for preview DMA */
 283 #define CIPRCLRSA4 (*(volatile int *)0x4F000078) /* RGB 4th frame start address for preview DMA */
 284 #define CIPRTRGFMT (*(volatile int *)0x4F00007C) /* Target image format of preview DMA */
 285 #define CIPRCTRL (*(volatile int *)0x4F000080) /* Preview DMA control related */
 286 #define CIPRSCPRERATIO (*(volatile int *)0x4F000084) /* Preview pre-scaler ratio control */
 287 #define CIPRSCPREDST (*(volatile int *)0x4F000088) /* Preview pre-scaler destination format */
 288 #define CIPRSCCTRL (*(volatile int *)0x4F00008C) /* Preview main-scaler control */
 289 #define CIPRTAREA (*(volatile int *)0x4F000090) /* Preview scaler target area */
 290 #define CIPRSTATUS (*(volatile int *)0x4F000098) /* Preview path status */
 291 #define CIIMGCPT (*(volatile int *)0x4F0000A0) /* Image capture enable command */
 292
 293 /* UART */
 294
 295 #define ULCON0 (*(volatile int *)0x50000000) /* UART 0 line control */
 296 #define UCON0 (*(volatile int *)0x50000004) /* UART 0 control */
 297 #define UFCON0 (*(volatile int *)0x50000008) /* UART 0 FIFO control */
 298 #define UMCON0 (*(volatile int *)0x5000000C) /* UART 0 modem control */
 299 #define UTRSTAT0 (*(volatile int *)0x50000010) /* UART 0 Tx/Rx status */
 300 #define UERSTAT0 (*(volatile int *)0x50000014) /* UART 0 Rx error status */
 301 #define UFSTAT0 (*(volatile int *)0x50000018) /* UART 0 FIFO status */
 302 #define UMSTAT0 (*(volatile int *)0x5000001C) /* UART 0 modem status */
 303 #define UTXH0 (*(volatile char *)0x50000020) /* UART 0 transmission hold */
 304 #define URXH0 (*(volatile char *)0x50000024) /* UART 0 receive buffer */
 305 #define UBRDIV0 (*(volatile int *)0x50000028) /* UART 0 baud rate divisor */
 306 #define ULCON1 (*(volatile int *)0x50004000) /* UART 1 line control */
 307 #define UCON1 (*(volatile int *)0x50004004) /* UART 1 control */
 308 #define UFCON1 (*(volatile int *)0x50004008) /* UART 1 FIFO control */
 309 #define UMCON1 (*(volatile int *)0x5000400C) /* UART 1 modem control */
 310 #define UTRSTAT1 (*(volatile int *)0x50004010) /* UART 1 Tx/Rx status */
 311 #define UERSTAT1 (*(volatile int *)0x50004014) /* UART 1 Rx error status */
 312 #define UFSTAT1 (*(volatile int *)0x50004018) /* UART 1 FIFO status */
 313 #define UMSTAT1 (*(volatile int *)0x5000401C) /* UART 1 modem status */
 314 #define UTXH1 (*(volatile char*)0x50004020) /* UART 1 transmission hold */
 315 #define URXH1 (*(volatile char*)0x50004024) /* UART 1 receive buffer */
 316 #define UBRDIV1 (*(volatile int *)0x50004028) /* UART 1 baud rate divisor */
 317 #define ULCON2 (*(volatile int *)0x50008000) /* UART 2 line control */
 318 #define UCON2 (*(volatile int *)0x50008004) /* UART 2 control */
 319 #define UFCON2 (*(volatile int *)0x50008008) /* UART 2 FIFO control */
 320 #define UTRSTAT2 (*(volatile int *)0x50008010) /* UART 2 Tx/Rx status */
 321 #define UERSTAT2 (*(volatile int *)0x50008014) /* UART 2 Rx error status */
 322 #define UFSTAT2 (*(volatile int *)0x50008018) /* UART 2 FIFO status */
 323 #define UTXH2 (*(volatile char*)0x50008020) /* UART 2 transmission hold */
 324 #define URXH2 (*(volatile char*)0x50008024) /* UART 2 receive buffer */
 325 #define UBRDIV2 (*(volatile int *)0x50008028) /* UART 2 baud rate divisor */
 326
 327 /* PWM Timer */
 328
 329 #define TCFG0 (*(volatile int *)0x51000000) /* Timer configuration */
 330 #define TCFG1 (*(volatile int *)0x51000004) /* Timer configuration */
 331 #define TCON (*(volatile int *)0x51000008) /* Timer control */
 332 #define TCNTB0 (*(volatile int *)0x5100000C) /* Timer count buffer 0 */
 333 #define TCMPB0 (*(volatile int *)0x51000010) /* Timer compare buffer 0 */
 334 #define TCNTO0 (*(volatile int *)0x51000014) /* Timer count observation 0 */
 335 #define TCNTB1 (*(volatile int *)0x51000018) /* Timer count buffer 1 */
 336 #define TCMPB1 (*(volatile int *)0x5100001C) /* Timer compare buffer 1 */
 337 #define TCNTO1 (*(volatile int *)0x51000020) /* Timer count observation 1 */
 338 #define TCNTB2 (*(volatile int *)0x51000024) /* Timer count buffer 2 */
 339 #define TCMPB2 (*(volatile int *)0x51000028) /* Timer compare buffer 2 */
 340 #define TCNTO2 (*(volatile int *)0x5100002C) /* Timer count observation 2 */
 341 #define TCNTB3 (*(volatile int *)0x51000030) /* Timer count buffer 3 */
 342 #define TCMPB3 (*(volatile int *)0x51000034) /* Timer compare buffer 3 */
 343 #define TCNTO3 (*(volatile int *)0x51000038) /* Timer count observation 3 */
 344 #define TCNTB4 (*(volatile int *)0x5100003C) /* Timer count buffer 4 */
 345 #define TCNTO4 (*(volatile int *)0x51000040) /* Timer count observation 4 */
 346
 347 /* USB Device */
 348
 349 #define FUNC_ADDR_REG (*(volatile char *)0x52000140) /* Function address */
 350 #define PWR_REG (*(volatile char *)0x52000144) /* Power management */
 351 #define EP_INT_REG (*(volatile char *)0x52000148) /* EP interrupt pending and clear */
 352 #define USB_INT_REG (*(volatile char *)0x52000158) /* USB interrupt pending and clear */
 353 #define EP_INT_EN_REG (*(volatile char *)0x5200015C) /* Interrupt enable */
 354 #define USB_INT_EN_REG (*(volatile char *)0x5200016C) /* Interrupt enable */
 355 #define FRAME_NUM1_REG (*(volatile char *)0x52000170) /* Frame number lower byte */
 356 #define FRAME_NUM2_REG (*(volatile char *)0x52000174) /* Frame number higher byte */
 357 #define INDEX_REG (*(volatile char *)0x52000178) /* Register index */
 358 #define EP0_CSR (*(volatile char *)0x52000184) /* Endpoint 0 status */
 359 #define IN_CSR1_REG (*(volatile char *)0x52000184) /* In endpoint control status */
 360 #define IN_CSR2_REG (*(volatile char *)0x52000188) /* In endpoint control status */
 361 #define MAXP_REG (*(volatile char *)0x52000180) /* Endpoint max packet */
 362 #define OUT_CSR1_REG (*(volatile char *)0x52000190) /* Out endpoint control status */
 363 #define OUT_CSR2_REG (*(volatile char *)0x52000194) /* Out endpoint control status */
 364 #define OUT_FIFO_CNT1_REG (*(volatile char *)0x52000198) /* Endpoint out write count */
 365 #define OUT_FIFO_CNT2_REG (*(volatile char *)0x5200019C) /* Endpoint out write count */
 366 #define EP0_FIFO (*(volatile char *)0x520001C0) /* Endpoint 0 FIFO */
 367 #define EP1_FIFO (*(volatile char *)0x520001C4) /* Endpoint 1 FIFO */
 368 #define EP2_FIFO (*(volatile char *)0x520001C8) /* Endpoint 2 FIFO */
 369 #define EP3_FIFO (*(volatile char *)0x520001CC) /* Endpoint 3 FIFO */
 370 #define EP4_FIFO (*(volatile char *)0x520001D0) /* Endpoint 4 FIFO */
 371 #define EP1_DMA_CON (*(volatile char *)0x52000200) /* EP1 DMA Interface control */
 372 #define EP1_DMA_UNIT (*(volatile char *)0x52000204) /* EP1 DMA Tx unit counter */
 373 #define EP1_DMA_FIFO (*(volatile char *)0x52000208) /* EP1 DMA Tx FIFO counter */
 374 #define EP1_DMA_TTC_L (*(volatile char *)0x5200020C) /* EP1 DMA Total Tx counter */
 375 #define EP1_DMA_TTC_M (*(volatile char *)0x52000210) /* EP1 DMA Total Tx counter */
 376 #define EP1_DMA_TTC_H (*(volatile char *)0x52000214) /* EP1 DMA Total Tx counter */
 377 #define EP2_DMA_CON (*(volatile char *)0x52000218) /* EP2 DMA interface control */
 378 #define EP2_DMA_UNIT (*(volatile char *)0x5200021C) /* EP2 DMA Tx Unit counter */
 379 #define EP2_DMA_FIFO (*(volatile char *)0x52000220) /* EP2 DMA Tx FIFO counter */
 380 #define EP2_DMA_TTC_L (*(volatile char *)0x52000224) /* EP2 DMA total Tx counter */
 381 #define EP2_DMA_TTC_M (*(volatile char *)0x52000228) /* EP2 DMA total Tx counter */
 382 #define EP2_DMA_TTC_H (*(volatile char *)0x5200022C) /* EP2 DMA Total Tx counter */
 383 #define EP3_DMA_CON (*(volatile char *)0x52000240) /* EP3 DMA Interface control */
 384 #define EP3_DMA_UNIT (*(volatile char *)0x52000244) /* EP3 DMA Tx Unit counter */
 385 #define EP3_DMA_FIFO (*(volatile char *)0x52000248) /* EP3 DMA Tx FIFO counter */
 386 #define EP3_DMA_TTC_L (*(volatile char *)0x5200024C) /* EP3 DMA Total Tx counter */
 387 #define EP3_DMA_TTC_M (*(volatile char *)0x52000250) /* EP3 DMA Total Tx counter */
 388 #define EP3_DMA_TTC_H (*(volatile char *)0x52000254) /* EP3 DMA Total Tx counter */
 389 #define EP4_DMA_CON (*(volatile char *)0x52000258) /* EP4 DMA Interface control */
 390 #define EP4_DMA_UNIT (*(volatile char *)0x5200025C) /* EP4 DMA Tx Unit counter */
 391 #define EP4_DMA_FIFO (*(volatile char *)0x52000260) /* EP4 DMA Tx FIFO counter */
 392 #define EP4_DMA_TTC_L (*(volatile char *)0x52000264) /* EP4 DMA Total Tx counter */
 393 #define EP4_DMA_TTC_M (*(volatile char *)0x52000268) /* EP4 DMA Total Tx counter */
 394 #define EP4_DMA_TTC_H (*(volatile char *)0x5200026C) /* EP4 DMA Total Tx counter */
 395
 396 /* Watchdog Timer */
 397
 398 #define WTCON (*(volatile int *)0x53000000) /* Watchdog timer mode */
 399 #define WTDAT (*(volatile int *)0x53000004) /* Watchdog timer data */
 400 #define WTCNT (*(volatile int *)0x53000008) /* Watchdog timer count */
 401
 402 /* IIC */
 403
 404 #define IICCON (*(volatile int *)0x54000000) /* IIC control  */
 405 #define IICSTAT (*(volatile int *)0x54000004) /* IIC status */
 406 #define IICADD (*(volatile int *)0x54000008) /* IIC address */
 407 #define IICDS (*(volatile int *)0x5400000C) /* IIC data shift */
 408 #define IICLC (*(volatile int *)0x54000010) /* IIC multi-master line control */
 409
 410 /* IIS */
 411
 412 #define IISCON (*(volatile int *)0x55000000) /* IIS control */
 413 #define IISMOD (*(volatile int *)0x55000004) /* IIS mode */
 414 #define IISPSR (*(volatile int *)0x55000008) /* IIS prescaler */
 415 #define IISFCON (*(volatile int *)0x5500000C) /* IIS FIFO control */
 416 #define IISFIFO (*(volatile short *)0x55000010) /* IIS FIFO entry */
 417
 418 /* I/O port */
 419
 420 #define GPACON (*(volatile int *)0x56000000) /* Port A control */
 421 #define GPADAT (*(volatile int *)0x56000004) /* Port A data */
 422 #define GPBCON (*(volatile int *)0x56000010) /* Port B control */
 423 #define GPBDAT (*(volatile int *)0x56000014) /* Port B data */
 424 #define GPBUP (*(volatile int *)0x56000018) /* Pull-up control B */
 425 #define GPCCON (*(volatile int *)0x56000020) /* Port C control */
 426 #define GPCDAT (*(volatile int *)0x56000024) /* Port C data */
 427 #define GPCUP (*(volatile int *)0x56000028) /* Pull-up control C */
 428 #define GPDCON (*(volatile int *)0x56000030) /* Port D control */
 429 #define GPDDAT (*(volatile int *)0x56000034) /* Port D data */
 430 #define GPDUP (*(volatile int *)0x56000038) /* Pull-up control D */
 431 #define GPECON (*(volatile int *)0x56000040) /* Port E control */
 432 #define GPEDAT (*(volatile int *)0x56000044) /* Port E data */
 433 #define GPEUP (*(volatile int *)0x56000048) /* Pull-up control E */
 434 #define GPFCON (*(volatile int *)0x56000050) /* Port F control */
 435 #define GPFDAT (*(volatile int *)0x56000054) /* Port F data */
 436 #define GPFUP (*(volatile int *)0x56000058) /* Pull-up control F */
 437 #define GPGCON (*(volatile int *)0x56000060) /* Port G control */
 438 #define GPGDAT (*(volatile int *)0x56000064) /* Port G data */
 439 #define GPGUP (*(volatile int *)0x56000068) /* Pull-up control G */
 440 #define GPHCON (*(volatile int *)0x56000070) /* Port H control */
 441 #define GPHDAT (*(volatile int *)0x56000074) /* Port H data */
 442 #define GPHUP (*(volatile int *)0x56000078) /* Pull-up control H */
 443 #define MISCCR (*(volatile int *)0x56000080) /* Miscellaneous control */
 444 #define DCLKCON (*(volatile int *)0x56000084) /* DCLK0/1 control */
 445 #define EXTINT0 (*(volatile int *)0x56000088) /* External interrupt control register 0 */
 446 #define EXTINT1 (*(volatile int *)0x5600008C) /* External interrupt control register 1 */
 447 #define EXTINT2 (*(volatile int *)0x56000090) /* External interrupt control register 2 */
 448 #define EINTFLT0 (*(volatile int *)0x56000094) /* Reserved */
 449 #define EINTFLT1 (*(volatile int *)0x56000098) /* Reserved */
 450 #define EINTFLT2 (*(volatile int *)0x5600009C) /* External interrupt filter control register 2 */
 451 #define EINTFLT3 (*(volatile int *)0x560000A0) /* External interrupt filter control register 3 */
 452 #define EINTMASK (*(volatile int *)0x560000A4) /* External interrupt mask */
 453 #define EINTPEND (*(volatile int *)0x560000A8) /* External interrupt pending */
 454 #define GSTATUS0 (*(volatile int *)0x560000AC) /* External pin status */
 455 #define GSTATUS1 (*(volatile int *)0x560000B0) /* Chip ID */
 456 #define GSTATUS2 (*(volatile int *)0x560000B4) /* Reset status */
 457 #define GSTATUS3 (*(volatile int *)0x560000B8) /* Inform register */
 458 #define GSTATUS4 (*(volatile int *)0x560000BC) /* Inform register */
 459 #define MSLCON (*(volatile int *)0x560000CC) /* Memory sleep control register */
 460 #define GPJCON (*(volatile int *)0x560000D0) /* Port J control */
 461 #define GPJDAT (*(volatile int *)0x560000D4) /* Port J data */
 462 #define GPJUP (*(volatile int *)0x560000D8) /* Pull-up control J */
 463
 464 /* RTC */
 465
 466 #define RTCCON (*(volatile char *)0x57000040) /* RTC control */
 467 #define TICNT (*(volatile char *)0x57000044) /* Tick time count */
 468 #define RTCALM (*(volatile char *)0x57000050) /* RTC alarm control */
 469 #define ALMSEC (*(volatile char *)0x57000054) /* Alarm second */
 470 #define ALMMIN (*(volatile char *)0x57000058) /* Alarm minute */
 471 #define ALMHOUR (*(volatile char *)0x5700005C) /* Alarm hour */
 472 #define ALMDATE (*(volatile char *)0x57000060) /* alarm day */
 473 #define ALMMON (*(volatile char *)0x57000064) /* Alarm month */
 474 #define ALMYEAR (*(volatile char *)0x57000068) /* Alarm year */
 475 #define BCDSEC (*(volatile char *)0x57000070) /* BCD second */
 476 #define BCDMIN (*(volatile char *)0x57000074) /* BCD minute */
 477 #define BCDHOUR (*(volatile char *)0x57000078) /* BCD hour */
 478 #define BCDDATE (*(volatile char *)0x5700007C) /* BCD day */
 479 #define BCDDAY (*(volatile char *)0x57000080) /* BCD date */
 480 #define BCDMON (*(volatile char *)0x57000084) /* BCD month */
 481 #define BCDYEAR (*(volatile char *)0x57000088) /* BCD year */
 482
 483 /* A/D Converter */
 484
 485 #define ADCCON (*(volatile int *)0x58000000) /* ADC control */
 486 #define ADCTSC (*(volatile int *)0x58000004) /* ADC touch screen control */
 487 #define ADCDLY (*(volatile int *)0x58000008) /* ADC start or interval delay */
 488 #define ADCDAT0 (*(volatile int *)0x5800000C) /* ADC conversion data */
 489 #define ADCDAT1 (*(volatile int *)0x58000010) /* ADC conversion data */
 490 #define ADCUPDN (*(volatile int *)0x58000014) /* Stylus up or down interrupt status */
 491
 492 /* SPI */
 493
 494 #define SPCON0 (*(volatile int *)0x59000000) /* SPI control */
 495 #define SPSTA0 (*(volatile int *)0x59000004) /* SPI status */
 496 #define SPPIN0 (*(volatile int *)0x59000008) /* SPI pin control */
 497 #define SPPRE0 (*(volatile int *)0x5900000C) /* SPI baud rate prescaler */
 498 #define SPTDAT0 (*(volatile int *)0x59000010) /* SPI Tx data */
 499 #define SPRDAT0 (*(volatile int *)0x59000014) /* SPI Rx data */
 500 #define SPCON1 (*(volatile int *)0x59000020) /* SPI control */
 501 #define SPSTA1 (*(volatile int *)0x59000024) /* SPI status */
 502 #define SPPIN1 (*(volatile int *)0x59000028) /* SPI pin control */
 503 #define SPPRE1 (*(volatile int *)0x5900002C) /* SPI baud rate prescaler */
 504 #define SPTDAT1 (*(volatile int *)0x59000030) /* SPI Tx data */
 505 #define SPRDAT1 (*(volatile int *)0x59000034) /* SPI Rx data */
 506
 507 /* SD Interface */
 508
 509 #define SDICON (*(volatile int *)0x5A000000) /* SDI control */
 510 #define SDIPRE (*(volatile int *)0x5A000004) /* SDI baud rate prescaler */
 511 #define SDICARG (*(volatile int *)0x5A000008) /* SDI command argument */
 512 #define SDICCON (*(volatile int *)0x5A00000C) /* SDI command control */
 513 #define SDICSTA (*(volatile int *)0x5A000010) /* SDI command status */
 514 #define SDIRSP0 (*(volatile int *)0x5A000014) /* SDI response */
 515 #define SDIRSP1 (*(volatile int *)0x5A000018) /* SDI response */
 516 #define SDIRSP2 (*(volatile int *)0x5A00001C) /* SDI response */
 517 #define SDIRSP3 (*(volatile int *)0x5A000020) /* SDI response */
 518 #define SDIDTIMER (*(volatile int *)0x5A000024) /* SDI data / busy timer */
 519 #define SDIBSIZE (*(volatile int *)0x5A000028) /* SDI block size */
 520 #define SDIDCON (*(volatile int *)0x5A00002C) /* SDI data control */
 521 #define SDIDCNT (*(volatile int *)0x5A000030) /* SDI data remain counter */
 522 #define SDIDSTA (*(volatile int *)0x5A000034) /* SDI data status */
 523 #define SDIFSTA (*(volatile int *)0x5A000038) /* SDI FIFO status */
 524 #define SDIIMSK (*(volatile int *)0x5A00003C) /* SDI interrupt mask */
 525 #define SDIDAT (*(volatile char *)0x5A000040) /* SDI data */
 526
 527 /* AC97 Audio-CODEC Interface */
 528
 529 #define AC_GLBCTRL (*(volatile int *)0x5B000000) /* AC97 global control register */
 530 #define AC_GLBSTAT (*(volatile int *)0x5B000004) /* AC97 global status register */
 531 #define AC_CODEC_CMD (*(volatile int *)0x5B000008) /* AC97 codec command register */
 532 #define AC_CODEC_STAT (*(volatile int *)0x5B00000C) /* AC97 codec status register */
 533 #define AC_PCMADDR (*(volatile int *)0x5B000010) /* AC97 PCM out/in channel FIFO address register */
 534 #define AC_MICADDR (*(volatile int *)0x5B000014) /* AC97 mic in channel FIFO address register */
 535 #define AC_PCMDATA (*(volatile int *)0x5B000018) /* AC97 PCM out/in channel FIFO data register */
 536 #define AC_MICDATA (*(volatile int *)0x5B00001C) /* AC97 MIC in channel FIFO data register */
 537
 538 /* Memory banks */
 539
 540 #define BANK0 0x00000000
 541 #define BANK1 0x08000000
 542 #define BANK2 0x10000000
 543 #define BANK3 0x18000000
 544 #define BANK4 0x20000000
 545 #define BANK5 0x28000000
 546 #define DRAM0 0x30000000
 547 #define DRAM1 0x31000000
 548 #define BOOTRAM 0x40000000
 549
 550 #endif /* __S3C2440_H__ */