firmware/target/arm/s5l8700/system-s5l8700.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Rob Purchase
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "kernel.h"
  23 #include "system.h"
  24 #include "panic.h"
  25 #ifdef IPOD_NANO2G
  26 #include "storage.h"
  27 #include "pmu-target.h"
  28 #endif
  29
  30 #define default_interrupt(name) \
  31   extern __attribute__((weak,alias("UIRQ"))) void name (void)
  32
  33 void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
  34 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked, \
  35                                       weak, alias("fiq_dummy")));
  36
  37 default_interrupt(EXT0);
  38 default_interrupt(EXT1);
  39 default_interrupt(EXT2);
  40 default_interrupt(EINT_VBUS);
  41 default_interrupt(EINTG);
  42 default_interrupt(INT_TIMERA);
  43 default_interrupt(INT_WDT);
  44 default_interrupt(INT_TIMERB);
  45 default_interrupt(INT_TIMERC);
  46 default_interrupt(INT_TIMERD);
  47 default_interrupt(INT_DMA);
  48 default_interrupt(INT_ALARM_RTC);
  49 default_interrupt(INT_PRI_RTC);
  50 default_interrupt(RESERVED1);
  51 default_interrupt(INT_UART);
  52 default_interrupt(INT_USB_HOST);
  53 default_interrupt(INT_USB_FUNC);
  54 default_interrupt(INT_LCDC_0);
  55 default_interrupt(INT_LCDC_1);
  56 default_interrupt(INT_ECC);
  57 default_interrupt(INT_CALM);
  58 default_interrupt(INT_ATA);
  59 default_interrupt(INT_UART0);
  60 default_interrupt(INT_SPDIF_OUT);
  61 default_interrupt(INT_SDCI);
  62 default_interrupt(INT_LCD);
  63 default_interrupt(INT_SPI);
  64 default_interrupt(INT_IIC);
  65 default_interrupt(RESERVED2);
  66 default_interrupt(INT_MSTICK);
  67 default_interrupt(INT_ADC_WAKEUP);
  68 default_interrupt(INT_ADC);
  69 default_interrupt(INT_UNK1);
  70 default_interrupt(INT_UNK2);
  71 default_interrupt(INT_UNK3);
  72
  73
  74 void INT_TIMER(void)
  75 {
  76     if (TACON & 0x00038000) INT_TIMERA();
  77     if (TBCON & 0x00038000) INT_TIMERB();
  78     if (TCCON & 0x00038000) INT_TIMERC();
  79     if (TDCON & 0x00038000) INT_TIMERD();
  80 }
  81
  82
  83 #if CONFIG_CPU==S5L8701
  84 static void (* const irqvector[])(void) =
  85 { /* still 90% unverified and probably incorrect */
  86     EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMER,INT_WDT,INT_UNK1,
  87     INT_UNK2,INT_UNK3,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
  88     INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,INT_ECC,
  89     INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
  90 };
  91 #else
  92 static void (* const irqvector[])(void) =
  93 {
  94     EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB,
  95     INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
  96     INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
  97     INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
  98 };
  99 #endif
 100
 101 #if CONFIG_CPU==S5L8701
 102 static const char * const irqname[] =
 103 { /* still 90% unverified and probably incorrect */
 104     "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMER","INT_WDT","INT_UNK1",
 105     "INT_UNK2","INT_UNK3","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
 106     "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT","INT_ECC",
 107     "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
 108 };
 109 #else
 110 static const char * const irqname[] =
 111 {
 112     "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB",
 113     "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
 114     "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
 115     "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
 116 };
 117 #endif
 118
 119 static void UIRQ(void)
 120 {
 121     unsigned int offset = INTOFFSET;
 122     panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
 123 }
 124
 125 void irq_handler(void)
 126 {
 127     /*
 128      * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
 129      */
 130
 131     asm volatile(   "stmfd sp!, {r0-r7, ip, lr} \n"   /* Store context */
 132                     "sub   sp, sp, #8           \n"); /* Reserve stack */
 133
 134     int irq_no = INTOFFSET;
 135
 136     irqvector[irq_no]();
 137
 138     /* clear interrupt */
 139     SRCPND = (1 << irq_no);
 140     INTPND = INTPND;
 141
 142     asm volatile(   "add   sp, sp, #8           \n"   /* Cleanup stack   */
 143                     "ldmfd sp!, {r0-r7, ip, lr} \n"   /* Restore context */
 144                     "subs  pc, lr, #4           \n"); /* Return from IRQ */
 145 }
 146
 147 void fiq_dummy(void)
 148 {
 149     asm volatile (
 150         "subs   pc, lr, #4   \r\n"
 151     );
 152 }
 153
 154
 155 void system_init(void)
 156 {
 157 #ifdef IPOD_NANO2G
 158     pmu_init();
 159 #endif
 160 }
 161
 162 void system_reboot(void)
 163 {
 164 #ifdef IPOD_NANO2G
 165 #ifdef HAVE_STORAGE_FLUSH
 166     storage_flush();
 167 #endif
 168
 169     /* Reset the SoC */
 170     asm volatile("msr CPSR_c, #0xd3    \n"
 171                  "mov r5, #0x110000    \n"
 172                  "add r5, r5, #0xff    \n"
 173                  "add r6, r5, #0xa00   \n"
 174                  "mov r10, #0x3c800000 \n"
 175                  "str r6, [r10]        \n"
 176                  "mov r6, #0xff0       \n"
 177                  "str r6, [r10,#4]     \n"
 178                  "str r5, [r10]        \n");
 179
 180     /* Wait for reboot to kick in */
 181     while(1);
 182 #endif
 183 }
 184
 185 void system_exception_wait(void)
 186 {
 187     while(1);
 188 }
 189
 190 int system_memory_guard(int newmode)
 191 {
 192     (void)newmode;
 193     return 0;
 194 }
 195
 196 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 197
 198 void set_cpu_frequency(long frequency)
 199 {
 200     if (cpu_frequency == frequency)
 201         return;
 202
 203     int oldlevel = disable_irq_save();
 204
 205 #if 1
 206     if (frequency == CPUFREQ_MAX)
 207     {
 208         /* FCLK_CPU = PLL0, HCLK = PLL0 / 2 */
 209         CLKCON = (CLKCON & ~0xFF00FF00) | 0x20003100;
 210         /* PCLK = HCLK / 2 */
 211         CLKCON2 |= 0x200;
 212         /* Switch to ASYNCHRONOUS mode */
 213         asm volatile(
 214             "mrc     p15, 0, r0,c1,c0    \n\t"
 215             "orr     r0, r0, #0xc0000000 \n\t"
 216             "mcr     p15, 0, r0,c1,c0    \n\t"
 217             ::: "r0"
 218           );
 219     }
 220     else
 221     {
 222         /* Switch to FASTBUS mode */
 223         asm volatile(
 224             "mrc     p15, 0, r0,c1,c0    \n\t"
 225             "bic     r0, r0, #0xc0000000 \n\t"
 226             "mcr     p15, 0, r0,c1,c0    \n\t"
 227             ::: "r0"
 228           );
 229         /* PCLK = HCLK */
 230         CLKCON2 &= ~0x200;
 231         /* FCLK_CPU = OFF, HCLK = PLL0 / 4 */
 232         CLKCON = (CLKCON & ~0xFF00FF00) | 0x80003300;
 233     }
 234
 235 #else  /* Alternative: Also clock down the PLL. Doesn't seem to save much
 236                        current, but results in high switching latency. */
 237
 238     if (frequency == CPUFREQ_MAX)
 239     {
 240         CLKCON &= ~0xFF00FF00;  /* Everything back to the OSC */
 241         PLLCON &= ~1;  /* Power down PLL0 */
 242         PLL0PMS = 0x021200;  /* 192 MHz */
 243         PLL0LCNT = 8100;
 244         PLLCON |= 1;  /* Power up PLL0 */
 245         while (!(PLLLOCK & 1));  /* Wait for PLL to lock */
 246         CLKCON2 |= 0x200;  /* PCLK = HCLK / 2 */
 247         CLKCON |= 0x20003100;  /* FCLK_CPU = PLL0, PCLK = PLL0 / 2 */
 248     }
 249     else
 250     {
 251         CLKCON &= ~0xFF00FF00;  /* Everything back to the OSC */
 252         CLKCON2 &= ~0x200;  /* PCLK = HCLK */
 253         PLLCON &= ~1;  /* Power down PLL0 */
 254         PLL0PMS = 0x000500;  /* 48 MHz */
 255         PLL0LCNT = 8100;
 256         PLLCON |= 1;  /* Power up PLL0 */
 257         while (!(PLLLOCK & 1));  /* Wait for PLL to lock */
 258         CLKCON |= 0x20002000;  /* FCLK_CPU = PLL0, PCLK = PLL0 */
 259     }
 260 #endif
 261
 262     cpu_frequency = frequency;
 263     restore_irq(oldlevel);
 264 }
 265
 266 #endif