1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright © 2009 Bertrik Sikken
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
30 #include "pcm_sampr.h"
31 #include "dma-target.h"
34 /* Driver for the IIS/PCM part of the s5l8700 using DMA
37 - not all possible PCM sample rates are enabled (no support in codec driver)
38 - pcm_play_dma_pause is untested, not sure if implemented the right way
39 - pcm_play_dma_stop is untested, not sure if implemented the right way
40 - recording is not implemented
43 static volatile int locked
= 0;
47 const unsigned char* dblbuf
;
49 /* table of recommended PLL/MCLK dividers for mode 256Fs from the datasheet */
50 static const struct div_entry
{
51 int pdiv
, mdiv
, sdiv
, cdiv
;
52 } div_table
[HW_NUM_FREQ
] = {
54 [HW_FREQ_11
] = { 2, 41, 5, 4},
55 [HW_FREQ_22
] = { 2, 41, 4, 4},
56 [HW_FREQ_44
] = { 2, 41, 3, 4},
57 [HW_FREQ_88
] = { 2, 41, 2, 4},
58 #if 0 /* disabled because the codec driver does not support it (yet) */
59 [HW_FREQ_8
] = { 2, 12, 3, 9},
60 [HW_FREQ_16
] = { 2, 12, 2, 9},
61 [HW_FREQ_32
] = { 2, 12, 1, 9},
62 [HW_FREQ_12
] = { 2, 12, 4, 3},
63 [HW_FREQ_24
] = { 2, 12, 3, 3},
64 [HW_FREQ_48
] = { 2, 12, 2, 3},
65 [HW_FREQ_96
] = { 2, 12, 1, 3},
68 [HW_FREQ_11
] = { 26, 189, 3, 8},
69 [HW_FREQ_22
] = { 50, 98, 2, 8},
70 [HW_FREQ_44
] = { 37, 151, 1, 9},
71 [HW_FREQ_88
] = { 50, 98, 1, 4},
72 #if 0 /* disabled because the codec driver does not support it (yet) */
73 [HW_FREQ_8
] = { 28, 192, 3, 12},
74 [HW_FREQ_16
] = { 28, 192, 3, 6},
75 [HW_FREQ_32
] = { 28, 192, 2, 6},
76 [HW_FREQ_12
] = { 28, 192, 3, 8},
77 [HW_FREQ_24
] = { 28, 192, 2, 8},
78 [HW_FREQ_48
] = { 28, 192, 2, 4},
79 [HW_FREQ_96
] = { 28, 192, 1, 4},
84 /* Mask the DMA interrupt */
85 void pcm_play_lock(void)
92 /* Unmask the DMA interrupt if enabled */
93 void pcm_play_unlock(void)
100 static const void* dma_callback(void) ICODE_ATTR
__attribute__((used
));
101 static const void* dma_callback(void)
105 void *dma_start_addr
;
106 pcm_play_get_more_callback(&dma_start_addr
, &nextsize
);
110 if (nextsize
>= 4096)
112 dblbufsize
= (nextsize
>> 4) & ~3;
113 nextsize
= nextsize
- dblbufsize
;
114 dblbuf
= dma_start_addr
+ nextsize
;
117 nextsize
= (nextsize
>> 1) - 1;
119 return dma_start_addr
;
130 nextsize
= (dblbufsize
>> 1) - 1;
135 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked
)) ICODE_ATTR
;
136 void fiq_handler(void)
140 "strne r10, [r8] \n" /* DMABASE0 */
141 "strne r11, [r8,#0x08] \n" /* DMATCNT0 */
142 "strne r9, [r8,#0x14] \n" /* DMACOM0 */
143 "moveq r10, #5 \n" /* STOP DMA */
144 "streq r10, [r8,#0x14] \n" /* DMACOM0 */
145 "mov r10, #7 \n" /* CLEAR IRQ */
146 "str r10, [r8,#0x14] \n" /* DMACOM0 */
147 "mov r11, #0x39C00000 \n" /* SRCPND */
148 "mov r10, #0x00000400 \n" /* INT_DMA */
149 "str r10, [r11] \n" /* ACK FIQ */
150 "stmfd sp!, {r0-r3,lr} \n"
153 "ldmfd sp!, {r0-r3,lr} \n"
154 "ldr r11, =nextsize \n"
160 void bootstrap_fiq(const void* addr
, size_t tcnt
) __attribute__((naked
,noinline
));
161 void bootstrap_fiq(const void* addr
, size_t tcnt
)
168 "msr cpsr_c, #0xD1 \n" /* FIQ mode, IRQ/FIQ disabled */
169 "mov r8, #0x38400000 \n" /* DMA BASE */
170 "mov r9, #4 \n" /* START DMA */
174 "ldr r12, =fiq_handler \n"
175 "ldr sp, =_fiqstackend \n"
177 "msr spsr_all, r3 \n"
182 void pcm_play_dma_start(const void *addr_in
, size_t size
)
184 unsigned char* addr
= (unsigned char*)addr_in
;
186 /* S1: DMA channel 0 set */
187 DMACON0
= (0 << 30) | /* DEVSEL */
188 (1 << 29) | /* DIR */
189 (0 << 24) | /* SCHCNT */
190 (1 << 22) | /* DSIZE */
191 (0 << 19) | /* BLEN */
192 (0 << 18) | /* RELOAD */
193 (0 << 17) | /* HCOMINT */
194 (1 << 16) | /* WCOMINT */
195 (0 << 0); /* OFFSET */
198 PCON5
= (PCON5
& ~(0xFFFF0000)) | 0x77720000;
199 PCON6
= (PCON6
& ~(0x0F000000)) | 0x02000000;
201 I2STXCON
= (1 << 20) | /* undocumented */
202 (0 << 16) | /* burst length */
203 (0 << 15) | /* 0 = falling edge */
204 (0 << 13) | /* 0 = basic I2S format */
205 (0 << 12) | /* 0 = MSB first */
206 (0 << 11) | /* 0 = left channel for low polarity */
207 (5 << 8) | /* MCLK divider */
208 (0 << 5) | /* 0 = 16-bit */
209 (2 << 3) | /* bit clock per frame */
210 (1 << 0); /* channel index */
212 /* S2: IIS Tx mode set */
213 I2STXCON
= (DMA_IISOUT_BLEN
<< 16) | /* burst length */
214 (0 << 15) | /* 0 = falling edge */
215 (0 << 13) | /* 0 = basic I2S format */
216 (0 << 12) | /* 0 = MSB first */
217 (0 << 11) | /* 0 = left channel for low polarity */
218 (3 << 8) | /* MCLK divider */
219 (0 << 5) | /* 0 = 16-bit */
220 (0 << 3) | /* bit clock per frame */
221 (1 << 0); /* channel index */
224 /* S3: DMA channel 0 on */
228 dblbufsize
= (size
>> 4) & ~3;
229 size
= size
- dblbufsize
;
230 dblbuf
= addr
+ size
;
234 bootstrap_fiq(addr
, (size
>> 1) - 1);
236 /* S4: IIS Tx clock on */
237 I2SCLKCON
= (1 << 0); /* 1 = power on */
240 I2STXCOM
= (1 << 3) | /* 1 = transmit mode on */
241 (1 << 2) | /* 1 = I2S interface enable */
242 (1 << 1) | /* 1 = DMA request enable */
243 (0 << 0); /* 0 = LRCK on */
246 void pcm_play_dma_stop(void)
248 /* DMA channel off */
251 /* TODO Some time wait */
252 /* LRCK half cycle wait */
255 I2STXCOM
= (1 << 3) | /* 1 = transmit mode on */
256 (0 << 2) | /* 1 = I2S interface enable */
257 (1 << 1) | /* 1 = DMA request enable */
258 (0 << 0); /* 0 = LRCK on */
261 /* pause playback by disabling the I2S interface */
262 void pcm_play_dma_pause(bool pause
)
265 I2STXCOM
|= (1 << 0); /* LRCK off */
268 I2STXCOM
&= ~(1 << 0); /* LRCK on */
272 void pcm_play_dma_init(void)
274 /* configure IIS pins */
276 PCON5
= (PCON5
& ~(0xFFFF0000)) | 0x22220000;
277 PCON6
= (PCON6
& ~(0x0F000000)) | 0x02000000;
279 PCON7
= (PCON7
& ~(0x0FFFFF00)) | 0x02222200;
282 /* enable clock to the IIS module */
285 /* Enable the DMA FIQ */
292 void pcm_postinit(void)
297 /* set the configured PCM frequency */
298 void pcm_dma_apply_settings(void)
300 // audiohw_set_frequency(pcm_sampr);
302 struct div_entry div
= div_table
[pcm_fsel
];
309 /* configure PLL1 and MCLK for the desired sample rate */
310 PLL1PMS
= (div
.pdiv
<< 16) |
313 PLL1LCNT
= 7500; /* no idea what to put here */
315 /* enable PLL1 and wait for lock */
317 while ((PLLLOCK
& (1 << 1)) == 0);
320 CLKCON
= (CLKCON
& ~(0xFF)) |
321 (0 << 7) | /* MCLK_MASK */
322 (2 << 5) | /* MCLK_SEL = PLL1 */
323 (1 << 4) | /* MCLK_DIV_ON */
324 (div
.cdiv
- 1); /* MCLK_DIV_VAL */
327 size_t pcm_get_bytes_waiting(void)
329 return (nextsize
+ DMACTCNT0
+ 2) << 1;
332 const void * pcm_play_dma_get_peak_buffer(int *count
)
334 *count
= DMACTCNT0
>> 1;
335 return (void *)(((DMACADDR0
+ 2) & ~3) | 0x40000000);
338 #ifdef HAVE_PCM_DMA_ADDRESS
339 void * pcm_dma_addr(void *addr
)
342 addr
= (void*)((uintptr_t)addr
| 0x40000000);
348 /****************************************************************************
349 ** Recording DMA transfer
351 #ifdef HAVE_RECORDING
352 void pcm_rec_lock(void)
356 void pcm_rec_unlock(void)
360 void pcm_rec_dma_stop(void)
364 void pcm_rec_dma_start(void *addr
, size_t size
)
370 void pcm_rec_dma_close(void)
375 void pcm_rec_dma_init(void)
380 const void * pcm_rec_dma_get_peak_buffer(void)
385 #endif /* HAVE_RECORDING */