firmware/target/arm/as3525/clock-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef CLOCK_TARGET_H
  22 #define CLOCK_TARGET_H
  23
  24 #include "config.h"
  25 #include "cpu.h"
  26
  27 /* returns clock divider, given maximal target frequency and clock reference */
  28 #define CLK_DIV(ref, target) ((ref + target - 1) / target)
  29
  30
  31 /*  Frequency and Bus Settings
  32  *  These bus settings work on the assumption that unboosted performance will be
  33  *  based on fastbus mode(FCLK == PCLK) at a frequency configured with this file.
  34  *  Boosted performance defaults to synchronous bus but will be changed to
  35  *  asynchronous bus if FCLK is not an integer multiple of PCLK.
  36  *  The player starts up in fastbus mode and synchronous or asynchronous mode is
  37  *  implemented in the set_cpu_frequency() function in system-as3525.c.  There
  38  *  are limitations on both frequencies and frequency relationships listed in 7.3.14
  39  *  of the as3525 datasheet that need to be observed.  If you are determined to
  40  *  use a frequency that is not "legal" you can do that. There are no checks for
  41  *  legal frequency values, only some validity checks to make sure the divider
  42  *  value fits into the number of bits allotted to it.
  43  *
  44  *  The CLOCK_DIV macro does a pretty good job at selecting divider values but
  45  *  you can always override it by choosing your own value and commenting out the
  46  *  macro.   AS3525_FCLK_PREDIV values other than 0 allow you to choose frequencies
  47  *  from lines below the main PLL frequency lines.  AS3525_FCLK_POSTDIV
  48  *  will be calculated automagically depending on the value you have selected
  49  *  for AS3525_FCLK_FREQ.  You may add more PLL frequencies by simply commenting
  50  *  out the current #defines for AS3525_PLLA_FREQ & AS3525_PLLA_SETTING and
  51  *  adding a #define for FREQ and divider setting to produce that frequency.I
  52  *  have included USB & PLLB for future use but commented them out for now.
  53  */
  54
  55 /* Clock Sources  */
  56 #define AS3525_CLK_MAIN           0
  57 #define AS3525_CLK_PLLA           1
  58 #define AS3525_CLK_PLLB           2
  59 #define AS3525_CLK_FCLK           3         /* Available as PCLK input only  */
  60
  61 /** ************ Change these to reconfigure clocking scheme *******************/
  62 #if CONFIG_CPU == AS3525v2
  63
  64 /* PLLA & PLLB registers differ from AS3525(v1)
  65  * so we use a setting with a known frequency */
  66 #define AS3525_PLLA_FREQ        240000000
  67 #define AS3525_PLLA_SETTING     0x113B
  68
  69 #define AS3525_FCLK_PREDIV      0
  70 #define AS3525_FCLK_FREQ        AS3525_PLLA_FREQ
  71
  72 /* XXX: CGU_PERI might also be different (i.e. no PCLK_DIV1_SEL), so we don't
  73  * set bit 6 (PCLK_DIV1_SEL) for the moment
  74  *
  75  * Note that setting bits 1:0 have no effect and they always read back as 0
  76  * Also note that CGU_PERI is based on fclk, not PLLA
  77  */
  78
  79 #ifdef SANSA_FUZEV2
  80 /* XXX: display is noticeably slower at 24MHz */
  81 #define AS3525_DRAM_FREQ        60000000    /* Initial DRAM frequency  */
  82 #else
  83 #define AS3525_DRAM_FREQ        24000000    /* Initial DRAM frequency  */
  84 #endif /* SANSA_FUZEV2 */
  85
  86 #else
  87 /* AS3525v1 */
  88
  89 /* PLL  frequencies and settings*/
  90 #define AS3525_PLLA_FREQ        248000000   /*124,82.7,62,49.6,41.3,35.4 */
  91        /* FCLK_PREDIV->  *7/8 = 217MHz      108.5 ,72.3, 54.25, 43.4, 36.17 */
  92                       /* *6/8 = 186MHz      93, 62, 46.5, 37.2 */
  93                       /* *5/8 = 155MHz      77.5, 51.67, 38.75 */
  94 #define AS3525_PLLA_SETTING     0x261F
  95
  96 /* PLLB frequencies and settings (audio and USB) */
  97 #define AS3525_PLLB_FREQ        384000000   /* allows 44.1kHz with 0.04% error*/
  98 #define AS3525_PLLB_SETTING     0x2630
  99
 100 //#define AS3525_PLLA_FREQ        384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/
 101        /* FCLK_PREDIV->  *7/8 = 336MHz      168, 112, 84, 67.2, 56, 48, 42, 37.3*/
 102                       /* *6/8 = 288MHz      144, 96, 72, 57.6, 48, 41.1, */
 103                       /* *5/8 = 240MHz      120, 80, 60, 48, 40  */
 104 //#define AS3525_PLLA_SETTING     0x2630
 105
 106 #define AS3525_FCLK_PREDIV    0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/
 107                                 /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */
 108
 109 #define AS3525_FCLK_FREQ      248000000            /* Boosted FCLK frequency  */
 110 #define AS3525_DRAM_FREQ       62000000            /* Initial DRAM frequency  */
 111 /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */
 112
 113 #endif  /* CONFIG_CPU == AS3525v2 */
 114
 115 #define AS3525_PCLK_FREQ      (AS3525_DRAM_FREQ/1)   /* PCLK divided from DRAM freq */
 116
 117 #define AS3525_DBOP_FREQ      (AS3525_PCLK_FREQ/1)   /* DBOP divided from PCLK freq */
 118
 119 /** ****************************************************************************/
 120
 121 /* Tell the software what frequencies we're running */
 122 #define CPUFREQ_MAX              AS3525_FCLK_FREQ
 123 #define CPUFREQ_DEFAULT          AS3525_PCLK_FREQ
 124 #define CPUFREQ_NORMAL           AS3525_PCLK_FREQ
 125
 126 /* FCLK */
 127 #define AS3525_FCLK_SEL          AS3525_CLK_PLLA
 128 #define AS3525_FCLK_POSTDIV      (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/
 129
 130 #if CONFIG_CPU == AS3525v2
 131 /* On as3525v2 we change fclk by writing to CGU_PROC */
 132 #define AS3525_FCLK_POSTDIV_UNBOOSTED      (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) */
 133 /* Since pclk is based on fclk, we need to change CGU_PERI as well */
 134 #define AS3525_PCLK_DIV0_UNBOOSTED (CLK_DIV(CPUFREQ_NORMAL, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
 135 #endif /* CONFIG_CPU == AS3525v2 */
 136
 137 /* MCLK */
 138 #define AS3525_MCLK_SEL          AS3525_CLK_PLLA
 139 #if (AS3525_MCLK_SEL==AS3525_CLK_PLLA)
 140 #define AS3525_MCLK_FREQ         AS3525_PLLA_FREQ
 141 #elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB)
 142 #define AS3525_MCLK_FREQ         AS3525_PLLB_FREQ
 143 #else
 144 #error Choose either PLLA or PLLB for MCLK!
 145 #endif
 146
 147 /* PCLK */
 148
 149 /* Figure out if we need to use asynchronous bus */
 150 #if ((CONFIG_CPU == AS3525) && (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ))
 151 #define ASYNCHRONOUS_BUS                          /* Boosted mode asynchronous */
 152 #endif
 153
 154 #ifdef ASYNCHRONOUS_BUS
 155 #define AS3525_PCLK_SEL          AS3525_CLK_PLLA    /* PLLA input for asynchronous */
 156 #define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/
 157 #else /* ASYNCHRONOUS_BUS */
 158 #define AS3525_PCLK_SEL          AS3525_CLK_FCLK    /* Fclk input for synchronous */
 159 #define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
 160 #endif /* ASYNCHRONOUS_BUS */
 161
 162          /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/
 163 #define AS3525_PCLK_DIV1         (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/
 164
 165    /* PCLK as Source */
 166   #define AS3525_DBOP_DIV        (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
 167   #define AS3525_I2C_PRESCALER   CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
 168   #define AS3525_I2C_FREQ        400000
 169   #define AS3525_SD_IDENT_DIV    ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
 170   #define AS3525_SD_IDENT_FREQ   400000      /* must be between 100 & 400 kHz */
 171   #define AS3525_SSP_PRESCALER   ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1)    /* must be an even number */
 172   #define AS3525_SSP_FREQ        12000000
 173
 174 #define AS3525_IDE_SEL           AS3525_CLK_PLLA           /* Input Source   */
 175 #define AS3525_IDE_DIV           (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
 176
 177 #if CONFIG_CPU == AS3525v2
 178 #define AS3525_MS_FREQ           120000000
 179 #define AS3525_MS_DIV            (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1)
 180 #define AS3525_SDSLOT_FREQ       24000000
 181 #define AS3525_SDSLOT_DIV        (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1)
 182 #define AS3525_IDE_FREQ          80000000
 183 #else
 184 #define AS3525_IDE_FREQ          50000000    /* The OF uses 66MHz maximal freq */
 185 #endif /* CONFIG_CPU == AS3525v2 */
 186
 187
 188 //#define AS3525_USB_SEL           AS3525_CLK_PLLA            /* Input Source   */
 189 //#define AS3525_USB_DIV           /* div = 1/(n=0?1:2n)*/
 190
 191
 192 /* Validity Checks */
 193
 194 /* AS3525_PCLK_FREQ  */
 195 #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
 196 #error PCLK frequency is too low : clock divider will not fit !
 197 #endif
 198
 199 /*  AS3525_DBOP_FREQ */
 200 #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
 201 #error DBOP frequency is too low : clock divider will not fit !
 202 #endif
 203
 204 /* AS3525_IDE_FREQ */
 205 #if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
 206 #error IDE frequency is too low : clock divider will not fit !
 207 #endif
 208
 209 /* AS3525_I2C_FREQ */
 210 #if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */
 211 #error I2C frequency is too low : clock divider will not fit !
 212 #endif
 213
 214 /* AS3525_SSP_FREQ */
 215 #if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ)) + 1 ) & ~1) >= (1<<8) /* 8 bits */
 216 #error SSP frequency is too low : clock divider will not fit !
 217 #endif
 218
 219 /* AS3525_SD_IDENT_FREQ */
 220 #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
 221 #error SD IDENTIFICATION frequency is too low : clock divider will not fit !
 222 #endif
 223
 224 /* I2SIN / I2SOUT frequencies */
 225 /* low samplerate */
 226 #if ((AS3525_MCLK_FREQ/(128*8000))) > 512   /* 8kHz = lowest frequency */
 227 #error AS3525_MCLK_FREQ is too high for 8kHz samplerate !
 228 #endif
 229 /* high samplerate */
 230 #if ((AS3525_MCLK_FREQ/(128*96000))) < 1   /* 96kHz = highest frequency */
 231 #error AS3525_MCLK_FREQ is too low for 96kHz samplerate !
 232 #endif
 233
 234 #endif /* CLOCK_TARGET_H */