| commit | 88c3039cb1cebace4f9342556a60384f0d7a189e | |
| author | funman <funman@a1c6a512-1295-4272-9138-f99709370657> | |
| Mon, 5 Apr 2010 04:48:43 +0000 (5 04:48 +0000) | ||
| committer | funman <funman@a1c6a512-1295-4272-9138-f99709370657> | |
| Mon, 5 Apr 2010 04:48:43 +0000 (5 04:48 +0000) | ||
| tree | 2c774a7926363d96fe0d8066e7b2735ed5d73ff9 | treesnapshot (tar.gz zip) |
| parent | 663f8892ab487d2da63fa4681dbdc886ff627416 | commitdiff |
as3525v2: set PCLK correctly
PCLK doesn't use PLLA as a source but FCLK, so when changing FCLK with
CGU_PROC register, we must change PCLK as well with CGU_PERI register
Operate with 24MHz PCLK (and unboosted FCLK) for Clipv2/Clip+
Use 60MHz on Fuzev2 to keep the display fast enough (still slower than
Fuzev1 though)
µSD seems to function correctly now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25475 a1c6a512-1295-4272-9138-f99709370657
PCLK doesn't use PLLA as a source but FCLK, so when changing FCLK with
CGU_PROC register, we must change PCLK as well with CGU_PERI register
Operate with 24MHz PCLK (and unboosted FCLK) for Clipv2/Clip+
Use 60MHz on Fuzev2 to keep the display fast enough (still slower than
Fuzev1 though)
µSD seems to function correctly now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25475 a1c6a512-1295-4272-9138-f99709370657
| firmware/target/arm/as3525/clock-target.h | diffblobblamehistory | |
| firmware/target/arm/as3525/system-as3525.c | diffblobblamehistory |