firmware/target/arm/as3525/ata_sd_as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 /* TODO: Find the real capacity of >2GB models (will be useful for USB) */
  26
  27 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  28 #include "fat.h"
  29 #include "thread.h"
  30 #include "led.h"
  31 #include "hotswap.h"
  32 #include "system.h"
  33 #include "cpu.h"
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include "as3525.h"
  38 #include "pl180.h"  /* SD controller */
  39 #include "pl081.h"  /* DMA controller */
  40 #include "dma-target.h" /* DMA request lines */
  41 #include "clock-target.h"
  42 #include "panic.h"
  43 #ifdef HAVE_BUTTON_LIGHT
  44 #include "backlight-target.h"
  45 #endif
  46 #include "stdbool.h"
  47 #include "ata_idle_notify.h"
  48 #include "sd.h"
  49 #include "usb.h"
  50
  51 #ifdef HAVE_HOTSWAP
  52 #include "disk.h"
  53 #endif
  54
  55 /* command flags */
  56 #define MCI_NO_FLAGS    (0<<0)
  57 #define MCI_RESP        (1<<0)
  58 #define MCI_LONG_RESP   (1<<1)
  59 #define MCI_ARG         (1<<2)
  60
  61 /* ARM PL180 registers */
  62 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  63 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  64 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  65 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  66 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  67 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  68 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  69 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  70 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  71 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  72 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  73 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  74 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  75 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  76 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  77 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  78 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  79 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  80 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  81
  82 #define MCI_ERROR \
  83     (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_TX_UNDERRUN)
  84
  85 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  86 /* volumes */
  87 #define     INTERNAL_AS3525 0   /* embedded SD card */
  88 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  89
  90 static const int pl180_base[NUM_DRIVES] = {
  91             NAND_FLASH_BASE
  92 #ifdef HAVE_MULTIDRIVE
  93             , SD_MCI_BASE
  94 #endif
  95 };
  96
  97 static int sd_select_bank(signed char bank);
  98 static int sd_init_card(const int drive);
  99 static void init_pl180_controller(const int drive);
 100 #define SECTOR_SIZE     512 /* XXX: different sector sizes ? */
 101 #define BLOCKS_PER_BANK 0x7a7800
 102
 103 static tCardInfo card_info[NUM_DRIVES];
 104
 105 /* maximum timeouts recommanded in the SD Specification v2.00 */
 106 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 107 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 108
 109 /* for compatibility */
 110 static long last_disk_activity = -1;
 111
 112 #define MIN_YIELD_PERIOD 5  /* ticks */
 113 static long next_yield = 0;
 114
 115 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 116 static const char         sd_thread_name[] = "ata/sd";
 117 static struct mutex       sd_mtx;
 118 static struct event_queue sd_queue;
 119 #ifndef BOOTLOADER
 120 static bool sd_enabled = false;
 121 #endif
 122
 123 static struct wakeup transfer_completion_signal;
 124 static volatile unsigned int transfer_error[NUM_VOLUMES];
 125 #define PL180_MAX_TRANSFER_ERRORS 10
 126
 127 #define UNALIGNED_NUM_SECTORS 10
 128 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SECTOR_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 129 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 130
 131 static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
 132
 133 #ifdef HAVE_HOTSWAP
 134 #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
 135 static int sd1_oneshot_callback(struct timeout *tmo)
 136 {
 137     (void)tmo;
 138
 139     /* This is called only if the state was stable for 300ms - check state
 140      * and post appropriate event. */
 141     if (card_detect_target())
 142     {
 143         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 144     }
 145     else
 146         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 147
 148     return 0;
 149 }
 150
 151 void INT_GPIOA(void)
 152 {
 153     static struct timeout sd1_oneshot;
 154     /* reset irq */
 155     GPIOA_IC = (1<<2);
 156     timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 157 }
 158 #endif  /* defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2) */
 159 #endif  /* HAVE_HOTSWAP */
 160
 161 void INT_NAND(void)
 162 {
 163     const int status = MCI_STATUS(INTERNAL_AS3525);
 164
 165     transfer_error[INTERNAL_AS3525] = status & MCI_ERROR;
 166
 167     wakeup_signal(&transfer_completion_signal);
 168     MCI_CLEAR(INTERNAL_AS3525) = status;
 169 }
 170
 171 #ifdef HAVE_MULTIDRIVE
 172 void INT_MCI0(void)
 173 {
 174     const int status = MCI_STATUS(SD_SLOT_AS3525);
 175
 176     transfer_error[SD_SLOT_AS3525] = status & MCI_ERROR;
 177
 178     wakeup_signal(&transfer_completion_signal);
 179     MCI_CLEAR(SD_SLOT_AS3525) = status;
 180 }
 181 #endif
 182
 183 static bool send_cmd(const int drive, const int cmd, const int arg,
 184                      const int flags, long *response)
 185 {
 186     int val, status;
 187
 188     while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 189
 190     if(MCI_COMMAND(drive) & MCI_COMMAND_ENABLE) /* clears existing command */
 191     {
 192         MCI_COMMAND(drive) = 0;
 193         mci_delay();
 194     }
 195
 196     val = cmd | MCI_COMMAND_ENABLE;
 197     if(flags & MCI_RESP)
 198     {
 199         val |= MCI_COMMAND_RESPONSE;
 200         if(flags & MCI_LONG_RESP)
 201             val |= MCI_COMMAND_LONG_RESPONSE;
 202     }
 203
 204     MCI_CLEAR(drive) = 0x7ff;
 205
 206     MCI_ARGUMENT(drive) = (flags & MCI_ARG) ? arg : 0;
 207     MCI_COMMAND(drive) = val;
 208
 209     while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);  /* wait for cmd completion */
 210
 211     MCI_COMMAND(drive) = 0;
 212     MCI_ARGUMENT(drive) = ~0;
 213
 214     status = MCI_STATUS(drive);
 215     MCI_CLEAR(drive) = 0x7ff;
 216
 217     if(flags & MCI_RESP)
 218     {
 219         if(status & MCI_CMD_TIMEOUT)
 220             return false;
 221         else if(status & (MCI_CMD_CRC_FAIL /* FIXME? */ | MCI_CMD_RESP_END))
 222         {   /* resp received */
 223             if(flags & MCI_LONG_RESP)
 224             {
 225                 /* store the response in reverse words order */
 226                 response[0] = MCI_RESP3(drive);
 227                 response[1] = MCI_RESP2(drive);
 228                 response[2] = MCI_RESP1(drive);
 229                 response[3] = MCI_RESP0(drive);
 230             }
 231             else
 232                 response[0] = MCI_RESP0(drive);
 233             return true;
 234         }
 235     }
 236     else if(status & MCI_CMD_SENT)
 237         return true;
 238
 239     return false;
 240 }
 241
 242 static int sd_init_card(const int drive)
 243 {
 244     unsigned long response;
 245     long init_timeout;
 246     bool sdhc;
 247     unsigned long temp_reg[4];
 248     int i;
 249
 250     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_FLAGS, NULL))
 251         return -1;
 252
 253     mci_delay();
 254
 255     sdhc = false;
 256     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP|MCI_ARG, &response))
 257         if((response & 0xFFF) == 0x1AA)
 258             sdhc = true;
 259
 260     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 261     init_timeout = current_tick + HZ;
 262
 263     do {
 264         /* timeout */
 265         if(current_tick > init_timeout)
 266             return -2;
 267
 268         /* app_cmd */
 269         if( !send_cmd(drive, SD_APP_CMD, 0, MCI_RESP|MCI_ARG, &response) ||
 270             !(response & (1<<5)) )
 271         {
 272             return -3;
 273         }
 274
 275         /* acmd41 */
 276         if(!send_cmd(drive, SD_APP_OP_COND, (sdhc ? 0x40FF8000 : (1<<23)),
 277                         MCI_RESP|MCI_ARG, &card_info[drive].ocr))
 278         {
 279             return -4;
 280         }
 281
 282     } while(!(card_info[drive].ocr & (1<<31)));
 283
 284     /* send CID */
 285     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP|MCI_ARG,
 286                             temp_reg))
 287         return -5;
 288
 289     for(i=0; i<4; i++)
 290         card_info[drive].cid[3-i] = temp_reg[i];
 291
 292     /* send RCA */
 293     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP|MCI_ARG,
 294                 &card_info[drive].rca))
 295         return -6;
 296
 297     /* send CSD */
 298     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 299                  MCI_RESP|MCI_LONG_RESP|MCI_ARG, temp_reg))
 300         return -7;
 301
 302     for(i=0; i<4; i++)
 303         card_info[drive].csd[3-i] = temp_reg[i];
 304
 305     sd_parse_csd(&card_info[drive]);
 306
 307     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 308         return -9;
 309
 310     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_ARG, NULL))
 311         return -10;
 312
 313     if(!send_cmd(drive, SD_SET_BUS_WIDTH, card_info[drive].rca | 2, MCI_ARG, NULL))
 314         return -11;
 315
 316     if(!send_cmd(drive, SD_SET_BLOCKLEN, card_info[drive].blocksize, MCI_ARG,
 317                  NULL))
 318         return -12;
 319
 320     card_info[drive].initialized = 1;
 321
 322     MCI_CLOCK(drive) |= MCI_CLOCK_BYPASS; /* full speed for controller clock */
 323     mci_delay();
 324
 325     /*
 326      * enable bank switching
 327      * without issuing this command, we only have access to 1/4 of the blocks
 328      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 329      * CSD register)
 330      */
 331     if(drive == INTERNAL_AS3525)
 332     {
 333         const int ret = sd_select_bank(-1);
 334         if(ret < 0)
 335             return ret - 13;
 336     }
 337
 338     return 0;
 339 }
 340
 341 static void sd_thread(void) __attribute__((noreturn));
 342 static void sd_thread(void)
 343 {
 344     struct queue_event ev;
 345     bool idle_notified = false;
 346
 347     while (1)
 348     {
 349         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 350
 351         switch ( ev.id )
 352         {
 353 #ifdef HAVE_HOTSWAP
 354         case SYS_HOTSWAP_INSERTED:
 355         case SYS_HOTSWAP_EXTRACTED:
 356         {
 357             int microsd_init = 1;
 358             fat_lock();          /* lock-out FAT activity first -
 359                                     prevent deadlocking via disk_mount that
 360                                     would cause a reverse-order attempt with
 361                                     another thread */
 362             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 363                                     into driver that bypass the fat cache */
 364
 365             /* We now have exclusive control of fat cache and ata */
 366
 367             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 368                                     descriptors aren't leaked and any busy
 369                                     ones are invalid if mounting */
 370
 371             /* Force card init for new card, re-init for re-inserted one or
 372              * clear if the last attempt to init failed with an error. */
 373             card_info[SD_SLOT_AS3525].initialized = 0;
 374
 375             if (ev.id == SYS_HOTSWAP_INSERTED)
 376             {
 377                 sd_enable(true);
 378                 init_pl180_controller(SD_SLOT_AS3525);
 379                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 380                 if (microsd_init < 0) /* initialisation failed */
 381                     panicf("microSD init failed : %d", microsd_init);
 382
 383                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 384             }
 385
 386             /*
 387              * Mount succeeded, or this was an EXTRACTED event,
 388              * in both cases notify the system about the changed filesystems
 389              */
 390             if (microsd_init)
 391                 queue_broadcast(SYS_FS_CHANGED, 0);
 392
 393             /* Access is now safe */
 394             mutex_unlock(&sd_mtx);
 395             fat_unlock();
 396             sd_enable(false);
 397         }
 398             break;
 399 #endif
 400         case SYS_TIMEOUT:
 401             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 402             {
 403                 idle_notified = false;
 404             }
 405             else
 406             {
 407                 /* never let a timer wrap confuse us */
 408                 next_yield = current_tick;
 409
 410                 if (!idle_notified)
 411                 {
 412                     call_storage_idle_notifys(false);
 413                     idle_notified = true;
 414                 }
 415             }
 416             break;
 417
 418         case SYS_USB_CONNECTED:
 419             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 420             /* Wait until the USB cable is extracted again */
 421             usb_wait_for_disconnect(&sd_queue);
 422
 423             break;
 424         case SYS_USB_DISCONNECTED:
 425             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 426             break;
 427         }
 428     }
 429 }
 430
 431 static void init_pl180_controller(const int drive)
 432 {
 433     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 434     MCI_CLEAR(drive) = 0x7ff;
 435
 436     MCI_MASK0(drive) = MCI_MASK1(drive) = MCI_ERROR | MCI_DATA_END;
 437
 438 #ifdef HAVE_MULTIDRIVE
 439     VIC_INT_ENABLE |=
 440         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 441
 442 #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
 443     /* setup isr for microsd monitoring */
 444     VIC_INT_ENABLE |= (INTERRUPT_GPIOA);
 445     /* clear previous irq */
 446     GPIOA_IC = (1<<2);
 447     /* enable edge detecting */
 448     GPIOA_IS &= ~(1<<2);
 449     /* detect both raising and falling edges */
 450     GPIOA_IBE |= (1<<2);
 451
 452 #endif
 453
 454 #else
 455     VIC_INT_ENABLE |= INTERRUPT_NAND;
 456 #endif
 457
 458     MCI_POWER(drive) = MCI_POWER_UP|(10 /*voltage*/ << 2); /* use OF voltage */
 459     mci_delay();
 460
 461     MCI_POWER(drive) |= MCI_POWER_ON;
 462     mci_delay();
 463
 464     MCI_SELECT(drive) = 0;
 465
 466     MCI_CLOCK(drive) = MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV;
 467     mci_delay();
 468 }
 469
 470 int sd_init(void)
 471 {
 472     int ret;
 473     CGU_IDE =   (1<<7)  /* AHB interface enable */  |
 474                 (1<<6)  /* interface enable */      |
 475                 (AS3525_IDE_DIV << 2)               |
 476                 AS3525_CLK_PLLA;  /* clock source = PLLA */
 477
 478
 479     CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 480 #ifdef HAVE_MULTIDRIVE
 481     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 482     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 483     CCU_IO |= (1<<2);
 484 #endif
 485
 486     wakeup_init(&transfer_completion_signal);
 487
 488     init_pl180_controller(INTERNAL_AS3525);
 489     ret = sd_init_card(INTERNAL_AS3525);
 490     if(ret < 0)
 491         return ret;
 492 #ifdef HAVE_MULTIDRIVE
 493     init_pl180_controller(SD_SLOT_AS3525);
 494 #endif
 495
 496     /* init mutex */
 497     mutex_init(&sd_mtx);
 498
 499     queue_init(&sd_queue, true);
 500     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 501             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 502
 503 #ifndef BOOTLOADER
 504     sd_enabled = true;
 505     sd_enable(false);
 506 #endif
 507     return 0;
 508 }
 509
 510 #ifdef HAVE_HOTSWAP
 511 bool sd_removable(IF_MD_NONVOID(int drive))
 512 {
 513 #ifndef HAVE_MULTIDRIVE
 514     const int drive=0;
 515 #endif
 516     return (drive==1);
 517 }
 518
 519 bool sd_present(IF_MD_NONVOID(int drive))
 520 {
 521 #ifndef HAVE_MULTIDRIVE
 522     const int drive=0;
 523 #endif
 524     if(drive==0)
 525     {
 526         return true;
 527     }
 528     else
 529     {
 530         return card_detect_target();
 531     }
 532 }
 533 #endif
 534
 535 static int sd_wait_for_state(const int drive, unsigned int state)
 536 {
 537     unsigned long response = 0;
 538     unsigned int timeout = 100; /* ticks */
 539     long t = current_tick;
 540
 541     while (1)
 542     {
 543         long tick;
 544
 545         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
 546                     MCI_RESP|MCI_ARG, &response))
 547             return -1;
 548
 549         if (((response >> 9) & 0xf) == state)
 550             return 0;
 551
 552         if(TIME_AFTER(current_tick, t + timeout))
 553             return -2;
 554
 555         if (TIME_AFTER((tick = current_tick), next_yield))
 556         {
 557             yield();
 558             timeout += current_tick - tick;
 559             next_yield = tick + MIN_YIELD_PERIOD;
 560         }
 561     }
 562 }
 563
 564 static int sd_select_bank(signed char bank)
 565 {
 566     int ret;
 567     unsigned loops = 0;
 568
 569     do {
 570         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 571             panicf("SD bank %d error : 0x%x", bank,
 572                     transfer_error[INTERNAL_AS3525]);
 573
 574         ret = sd_wait_for_state(INTERNAL_AS3525, SD_TRAN);
 575         if (ret < 0)
 576             return ret - 2;
 577
 578         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_ARG, NULL))
 579             return -1;
 580
 581         mci_delay();
 582
 583         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_FLAGS, NULL))
 584             return -2;
 585
 586         mci_delay();
 587
 588         memset(uncached_buffer, 0, 512);
 589         if(bank == -1)
 590         {   /* enable bank switching */
 591             uncached_buffer[0] = 16;
 592             uncached_buffer[1] = 1;
 593             uncached_buffer[2] = 10;
 594         }
 595         else
 596             uncached_buffer[0] = bank;
 597
 598         dma_retain();
 599         /* we don't use the uncached buffer here, because we need the
 600          * physical memory address for DMA transfers */
 601         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 602             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 603             NULL);
 604
 605         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 606         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 607         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 608                                 (0<<1) /* transfer direction */ |
 609                                 (1<<3) /* DMA */                |
 610                                 (9<<4) /* 2^9 = 512 */ ;
 611
 612         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 613
 614         dma_release();
 615
 616         mci_delay();
 617
 618         ret = sd_wait_for_state(INTERNAL_AS3525, SD_TRAN);
 619         if (ret < 0)
 620             return ret - 4;
 621     } while(transfer_error[INTERNAL_AS3525]);
 622
 623     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 624
 625     return 0;
 626 }
 627
 628 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 629                                int count, void* buf, const bool write)
 630 {
 631 #ifndef HAVE_MULTIDRIVE
 632     const int drive = 0;
 633 #endif
 634     int ret = 0;
 635     unsigned loops = 0;
 636
 637     /* skip SanDisk OF */
 638     if (drive == INTERNAL_AS3525)
 639         start += AMS_OF_SIZE;
 640
 641     mutex_lock(&sd_mtx);
 642 #ifndef BOOTLOADER
 643     sd_enable(true);
 644     led(true);
 645 #endif
 646
 647     if (card_info[drive].initialized <= 0)
 648     {
 649         ret = sd_init_card(drive);
 650         if (!(card_info[drive].initialized))
 651             goto sd_transfer_error;
 652     }
 653
 654     last_disk_activity = current_tick;
 655
 656     ret = sd_wait_for_state(drive, SD_TRAN);
 657     if (ret < 0)
 658     {
 659         ret -= 20;
 660         goto sd_transfer_error;
 661     }
 662
 663     dma_retain();
 664
 665     while(count)
 666     {
 667         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 668          * register, so we have to transfer maximum 127 sectors at a time. */
 669         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 670         void *dma_buf;
 671         const int cmd =
 672             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 673         unsigned long bank_start = start;
 674
 675         /* Only switch banks for internal storage */
 676         if(drive == INTERNAL_AS3525)
 677         {
 678             unsigned int bank = start / BLOCKS_PER_BANK; /* Current bank */
 679
 680             /* Switch bank if needed */
 681             if(card_info[INTERNAL_AS3525].current_bank != bank)
 682             {
 683                 ret = sd_select_bank(bank);
 684                 if (ret < 0)
 685                 {
 686                     ret -= 2*20;
 687                     goto sd_transfer_error;
 688                 }
 689             }
 690
 691             /* Adjust start block in current bank */
 692             bank_start -= bank * BLOCKS_PER_BANK;
 693
 694             /* Do not cross a bank boundary in a single transfer loop */
 695             if((transfer + bank_start) > BLOCKS_PER_BANK)
 696                 transfer = BLOCKS_PER_BANK - bank_start;
 697         }
 698
 699         dma_buf = aligned_buffer;
 700         if(transfer > UNALIGNED_NUM_SECTORS)
 701             transfer = UNALIGNED_NUM_SECTORS;
 702         if(write)
 703             memcpy(uncached_buffer, buf, transfer * SECTOR_SIZE);
 704
 705         /* Set bank_start to the correct unit (blocks or bytes) */
 706         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 707             bank_start *= SD_BLOCK_SIZE;
 708
 709         if(!send_cmd(drive, cmd, bank_start, MCI_ARG, NULL))
 710         {
 711             ret -= 3*20;
 712             goto sd_transfer_error;
 713         }
 714
 715         if(write)
 716             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 717                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 718                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 719         else
 720             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 721                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 722                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 723
 724         /* FIXME : we should check if the timeouts calculated from the card's
 725          * CSD are lower, and use them if it is the case
 726          * Note : the OF doesn't seem to use them anyway */
 727         MCI_DATA_TIMER(drive) = write ?
 728                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 729         MCI_DATA_LENGTH(drive) = transfer * card_info[drive].blocksize;
 730         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 731                                 (!write<<1) /* transfer direction */    |
 732                                 (1<<3) /* DMA */                        |
 733                                 (9<<4) /* 2^9 = 512 */ ;
 734
 735
 736         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 737
 738         /* Higher speed class cards need a write delay here for some reason */
 739         if((drive == SD_SLOT_AS3525) && write)
 740         {
 741             int delay = 3500;
 742             while(delay--)  asm volatile ("nop\n");
 743         }
 744
 745         if(!transfer_error[drive])
 746         {
 747             if(!write)
 748                 memcpy(buf, uncached_buffer, transfer * SECTOR_SIZE);
 749             buf += transfer * SECTOR_SIZE;
 750             start += transfer;
 751             count -= transfer;
 752             loops = 0;  /* reset errors counter */
 753         }
 754         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 755                 panicf("SD transfer error : 0x%x", transfer_error[drive]);
 756
 757         last_disk_activity = current_tick;
 758
 759         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_FLAGS, NULL))
 760         {
 761             ret = -4*20;
 762             goto sd_transfer_error;
 763         }
 764
 765         ret = sd_wait_for_state(drive, SD_TRAN);
 766         if (ret < 0)
 767         {
 768             ret -= 5*20;
 769             goto sd_transfer_error;
 770         }
 771     }
 772
 773     ret = 0;    /* success */
 774
 775 sd_transfer_error:
 776
 777     dma_release();
 778
 779 #ifndef BOOTLOADER
 780     led(false);
 781     sd_enable(false);
 782 #endif
 783
 784     if (ret)    /* error */
 785         card_info[drive].initialized = 0;
 786
 787     mutex_unlock(&sd_mtx);
 788     return ret;
 789 }
 790
 791 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 792                      void* buf)
 793 {
 794     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 795 }
 796
 797 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 798                      const void* buf)
 799 {
 800
 801 #ifdef BOOTLOADER /* we don't need write support in bootloader */
 802 #ifdef HAVE_MULTIDRIVE
 803     (void) drive;
 804 #endif
 805     (void) start;
 806     (void) count;
 807     (void) buf;
 808     return -1;
 809 #else
 810     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 811 #endif
 812 }
 813
 814 #ifndef BOOTLOADER
 815 long sd_last_disk_activity(void)
 816 {
 817     return last_disk_activity;
 818 }
 819
 820 void sd_enable(bool on)
 821 {
 822     /* buttonlight AMSes need a bit of special handling for the buttonlight here,
 823      * due to the dual mapping of GPIOD and XPD */
 824 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 825     extern int buttonlight_is_on;
 826 #endif
 827     if (sd_enabled == on)
 828         return; /* nothing to do */
 829     if(on)
 830     {
 831         CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 832 #ifdef HAVE_MULTIDRIVE
 833         CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 834 #ifdef HAVE_BUTTON_LIGHT
 835         CCU_IO |= (1<<2);
 836         if (buttonlight_is_on)
 837             GPIOD_DIR &= ~(1<<7);
 838         else
 839             _buttonlight_off();
 840 #endif
 841 #endif
 842         CGU_IDE |= (1<<7)  /* AHB interface enable */  |
 843                    (1<<6)  /* interface enable */;
 844         sd_enabled = true;
 845     }
 846     else
 847     {
 848         CGU_PERI &= ~CGU_NAF_CLOCK_ENABLE;
 849 #ifdef HAVE_MULTIDRIVE
 850 #ifdef HAVE_BUTTON_LIGHT
 851         CCU_IO &= ~(1<<2);
 852         if (buttonlight_is_on)
 853             _buttonlight_on();
 854 #endif
 855         CGU_PERI &= ~CGU_MCI_CLOCK_ENABLE;
 856 #endif
 857         CGU_IDE &= ~((1<<7)|(1<<6));
 858         sd_enabled = false;
 859     }
 860 }
 861
 862 tCardInfo *card_get_info_target(int card_no)
 863 {
 864     return &card_info[card_no];
 865 }
 866
 867 bool card_detect_target(void)
 868 {
 869 #if defined(HAVE_HOTSWAP) && \
 870     (defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2))
 871     return !(GPIOA_PIN(2));
 872 #else
 873     return false;
 874 #endif
 875 }
 876
 877 #ifdef HAVE_HOTSWAP
 878 void card_enable_monitoring_target(bool on)
 879 {
 880     if (on)
 881     {
 882     /* add e200v2/c200v2 here */
 883 #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
 884         /* enable isr*/
 885         GPIOA_IE |= (1<<2);
 886 #endif
 887     }
 888     else
 889     {
 890 #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
 891         /* edisable isr*/
 892         GPIOA_IE &= ~(1<<2);
 893 #endif
 894     }
 895 }
 896 #endif
 897
 898 #endif /* BOOTLOADER */
 899
 900 #ifdef CONFIG_STORAGE_MULTI
 901 int sd_num_drives(int first_drive)
 902 {
 903     /* We don't care which logical drive number(s) we have been assigned */
 904     (void)first_drive;
 905
 906 #ifdef HAVE_MULTIDRIVE
 907     return 2;
 908 #else
 909     return 1;
 910 #endif
 911 }
 912 #endif