firmware/target/arm/as3525/ata_sd_as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 /* TODO: Find the real capacity of >2GB models (will be useful for USB) */
  26
  27 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  28 #include "fat.h"
  29 #include "thread.h"
  30 #include "led.h"
  31 #include "hotswap.h"
  32 #include "system.h"
  33 #include "cpu.h"
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include "as3525.h"
  38 #include "pl180.h"  /* SD controller */
  39 #include "pl081.h"  /* DMA controller */
  40 #include "dma-target.h" /* DMA request lines */
  41 #include "clock-target.h"
  42 #include "panic.h"
  43 #ifdef HAVE_BUTTON_LIGHT
  44 #include "backlight-target.h"
  45 #endif
  46 #include "stdbool.h"
  47 #include "ata_idle_notify.h"
  48 #include "sd.h"
  49 #include "usb.h"
  50
  51 #ifdef HAVE_HOTSWAP
  52 #include "disk.h"
  53 #include "panic.h"
  54 #endif
  55
  56 /* command flags */
  57 #define MCI_NO_FLAGS    (0<<0)
  58 #define MCI_RESP        (1<<0)
  59 #define MCI_LONG_RESP   (1<<1)
  60 #define MCI_ARG         (1<<2)
  61
  62 /* ARM PL180 registers */
  63 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  64 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  65 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  66 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  67 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  68 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  69 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  70 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  71 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  72 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  73 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  74 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  75 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  76 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  77 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  78 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  79 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  80 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  81 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  82
  83 #define MCI_ERROR \
  84     (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_TX_UNDERRUN)
  85
  86 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  87 /* volumes */
  88 #define     INTERNAL_AS3525 0   /* embedded SD card */
  89 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  90
  91 static const int pl180_base[NUM_DRIVES] = {
  92             NAND_FLASH_BASE
  93 #ifdef HAVE_MULTIDRIVE
  94             , SD_MCI_BASE
  95 #endif
  96 };
  97
  98 static int sd_select_bank(signed char bank);
  99 static int sd_init_card(const int drive);
 100 static void init_pl180_controller(const int drive);
 101 #define SECTOR_SIZE     512 /* XXX: different sector sizes ? */
 102 #define BLOCKS_PER_BANK 0x7a7800
 103
 104 static tCardInfo card_info[NUM_DRIVES];
 105
 106 /* maximum timeouts recommanded in the SD Specification v2.00 */
 107 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 108 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 109
 110 /* for compatibility */
 111 static long last_disk_activity = -1;
 112
 113 #define MIN_YIELD_PERIOD 5  /* ticks */
 114 static long next_yield = 0;
 115
 116 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 117 static const char         sd_thread_name[] = "ata/sd";
 118 static struct mutex       sd_mtx;
 119 static struct event_queue sd_queue;
 120 #ifndef BOOTLOADER
 121 static bool sd_enabled = false;
 122 #endif
 123
 124 static struct wakeup transfer_completion_signal;
 125 static volatile unsigned int transfer_error[NUM_VOLUMES];
 126 #define PL180_MAX_TRANSFER_ERRORS 10
 127
 128 #define UNALIGNED_NUM_SECTORS 10
 129 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SECTOR_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 130 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 131
 132 static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
 133
 134 #ifdef HAVE_HOTSWAP
 135 #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
 136 static int sd1_oneshot_callback(struct timeout *tmo)
 137 {
 138     (void)tmo;
 139
 140     /* This is called only if the state was stable for 300ms - check state
 141      * and post appropriate event. */
 142     if (card_detect_target())
 143     {
 144         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 145     }
 146     else
 147         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 148
 149     return 0;
 150 }
 151
 152 void INT_GPIOA(void)
 153 {
 154     static struct timeout sd1_oneshot;
 155     /* reset irq */
 156     GPIOA_IC = (1<<2);
 157     timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 158 }
 159 #endif  /* defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2) */
 160 #endif  /* HAVE_HOTSWAP */
 161
 162 void INT_NAND(void)
 163 {
 164     const int status = MCI_STATUS(INTERNAL_AS3525);
 165
 166     transfer_error[INTERNAL_AS3525] = status & MCI_ERROR;
 167
 168     wakeup_signal(&transfer_completion_signal);
 169     MCI_CLEAR(INTERNAL_AS3525) = status;
 170 }
 171
 172 #ifdef HAVE_MULTIDRIVE
 173 void INT_MCI0(void)
 174 {
 175     const int status = MCI_STATUS(SD_SLOT_AS3525);
 176
 177     transfer_error[SD_SLOT_AS3525] = status & MCI_ERROR;
 178
 179     wakeup_signal(&transfer_completion_signal);
 180     MCI_CLEAR(SD_SLOT_AS3525) = status;
 181 }
 182 #endif
 183
 184 static bool send_cmd(const int drive, const int cmd, const int arg,
 185                      const int flags, long *response)
 186 {
 187     int val, status;
 188
 189     while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 190
 191     if(MCI_COMMAND(drive) & MCI_COMMAND_ENABLE) /* clears existing command */
 192     {
 193         MCI_COMMAND(drive) = 0;
 194         mci_delay();
 195     }
 196
 197     val = cmd | MCI_COMMAND_ENABLE;
 198     if(flags & MCI_RESP)
 199     {
 200         val |= MCI_COMMAND_RESPONSE;
 201         if(flags & MCI_LONG_RESP)
 202             val |= MCI_COMMAND_LONG_RESPONSE;
 203     }
 204
 205     MCI_CLEAR(drive) = 0x7ff;
 206
 207     MCI_ARGUMENT(drive) = (flags & MCI_ARG) ? arg : 0;
 208     MCI_COMMAND(drive) = val;
 209
 210     while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);  /* wait for cmd completion */
 211
 212     MCI_COMMAND(drive) = 0;
 213     MCI_ARGUMENT(drive) = ~0;
 214
 215     status = MCI_STATUS(drive);
 216     MCI_CLEAR(drive) = 0x7ff;
 217
 218     if(flags & MCI_RESP)
 219     {
 220         if(status & MCI_CMD_TIMEOUT)
 221             return false;
 222         else if(status & (MCI_CMD_CRC_FAIL /* FIXME? */ | MCI_CMD_RESP_END))
 223         {   /* resp received */
 224             if(flags & MCI_LONG_RESP)
 225             {
 226                 /* store the response in reverse words order */
 227                 response[0] = MCI_RESP3(drive);
 228                 response[1] = MCI_RESP2(drive);
 229                 response[2] = MCI_RESP1(drive);
 230                 response[3] = MCI_RESP0(drive);
 231             }
 232             else
 233                 response[0] = MCI_RESP0(drive);
 234             return true;
 235         }
 236     }
 237     else if(status & MCI_CMD_SENT)
 238         return true;
 239
 240     return false;
 241 }
 242
 243 static int sd_init_card(const int drive)
 244 {
 245     unsigned long response;
 246     long init_timeout;
 247     bool sdhc;
 248     unsigned long temp_reg[4];
 249     int i;
 250
 251     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_FLAGS, NULL))
 252         return -1;
 253
 254     mci_delay();
 255
 256     sdhc = false;
 257     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP|MCI_ARG, &response))
 258         if((response & 0xFFF) == 0x1AA)
 259             sdhc = true;
 260
 261     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 262     init_timeout = current_tick + HZ;
 263
 264     do {
 265         /* timeout */
 266         if(current_tick > init_timeout)
 267             return -2;
 268
 269         /* app_cmd */
 270         if( !send_cmd(drive, SD_APP_CMD, 0, MCI_RESP|MCI_ARG, &response) ||
 271             !(response & (1<<5)) )
 272         {
 273             return -3;
 274         }
 275
 276         /* acmd41 */
 277         if(!send_cmd(drive, SD_APP_OP_COND, (sdhc ? 0x40FF8000 : (1<<23)),
 278                         MCI_RESP|MCI_ARG, &card_info[drive].ocr))
 279         {
 280             return -4;
 281         }
 282
 283     } while(!(card_info[drive].ocr & (1<<31)));
 284
 285     /* send CID */
 286     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP|MCI_ARG,
 287                             temp_reg))
 288         return -5;
 289
 290     for(i=0; i<4; i++)
 291         card_info[drive].cid[3-i] = temp_reg[i];
 292
 293     /* send RCA */
 294     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP|MCI_ARG,
 295                 &card_info[drive].rca))
 296         return -6;
 297
 298     /* send CSD */
 299     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 300                  MCI_RESP|MCI_LONG_RESP|MCI_ARG, temp_reg))
 301         return -7;
 302
 303     for(i=0; i<4; i++)
 304         card_info[drive].csd[3-i] = temp_reg[i];
 305
 306     sd_parse_csd(&card_info[drive]);
 307
 308     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 309         return -9;
 310
 311     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_ARG, NULL))
 312         return -10;
 313
 314     if(!send_cmd(drive, SD_SET_BUS_WIDTH, card_info[drive].rca | 2, MCI_ARG, NULL))
 315         return -11;
 316
 317     if(!send_cmd(drive, SD_SET_BLOCKLEN, card_info[drive].blocksize, MCI_ARG,
 318                  NULL))
 319         return -12;
 320
 321     card_info[drive].initialized = 1;
 322
 323     MCI_CLOCK(drive) |= MCI_CLOCK_BYPASS; /* full speed for controller clock */
 324     mci_delay();
 325
 326     /*
 327      * enable bank switching
 328      * without issuing this command, we only have access to 1/4 of the blocks
 329      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 330      * CSD register)
 331      */
 332     if(drive == INTERNAL_AS3525)
 333     {
 334         const int ret = sd_select_bank(-1);
 335         if(ret < 0)
 336             return ret - 13;
 337     }
 338
 339     return 0;
 340 }
 341
 342 static void sd_thread(void) __attribute__((noreturn));
 343 static void sd_thread(void)
 344 {
 345     struct queue_event ev;
 346     bool idle_notified = false;
 347
 348     while (1)
 349     {
 350         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 351
 352         switch ( ev.id )
 353         {
 354 #ifdef HAVE_HOTSWAP
 355         case SYS_HOTSWAP_INSERTED:
 356         case SYS_HOTSWAP_EXTRACTED:
 357         {
 358             int microsd_init = 1;
 359             fat_lock();          /* lock-out FAT activity first -
 360                                     prevent deadlocking via disk_mount that
 361                                     would cause a reverse-order attempt with
 362                                     another thread */
 363             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 364                                     into driver that bypass the fat cache */
 365
 366             /* We now have exclusive control of fat cache and ata */
 367
 368             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 369                                     descriptors aren't leaked and any busy
 370                                     ones are invalid if mounting */
 371
 372             /* Force card init for new card, re-init for re-inserted one or
 373              * clear if the last attempt to init failed with an error. */
 374             card_info[SD_SLOT_AS3525].initialized = 0;
 375
 376             if (ev.id == SYS_HOTSWAP_INSERTED)
 377             {
 378                 sd_enable(true);
 379                 init_pl180_controller(SD_SLOT_AS3525);
 380                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 381                 if (microsd_init < 0) /* initialisation failed */
 382                     panicf("microSD init failed : %d", microsd_init);
 383
 384                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 385             }
 386
 387             /*
 388              * Mount succeeded, or this was an EXTRACTED event,
 389              * in both cases notify the system about the changed filesystems
 390              */
 391             if (microsd_init)
 392                 queue_broadcast(SYS_FS_CHANGED, 0);
 393
 394             /* Access is now safe */
 395             mutex_unlock(&sd_mtx);
 396             fat_unlock();
 397             sd_enable(false);
 398         }
 399             break;
 400 #endif
 401         case SYS_TIMEOUT:
 402             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 403             {
 404                 idle_notified = false;
 405             }
 406             else
 407             {
 408                 /* never let a timer wrap confuse us */
 409                 next_yield = current_tick;
 410
 411                 if (!idle_notified)
 412                 {
 413                     call_storage_idle_notifys(false);
 414                     idle_notified = true;
 415                 }
 416             }
 417             break;
 418
 419         case SYS_USB_CONNECTED:
 420             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 421             /* Wait until the USB cable is extracted again */
 422             usb_wait_for_disconnect(&sd_queue);
 423
 424             break;
 425         case SYS_USB_DISCONNECTED:
 426             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 427             break;
 428         }
 429     }
 430 }
 431
 432 static void init_pl180_controller(const int drive)
 433 {
 434     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 435     MCI_CLEAR(drive) = 0x7ff;
 436
 437     MCI_MASK0(drive) = MCI_MASK1(drive) = MCI_ERROR | MCI_DATA_END;
 438
 439 #ifdef HAVE_MULTIDRIVE
 440     VIC_INT_ENABLE |=
 441         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 442
 443 #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
 444     /* setup isr for microsd monitoring */
 445     VIC_INT_ENABLE |= (INTERRUPT_GPIOA);
 446     /* clear previous irq */
 447     GPIOA_IC = (1<<2);
 448     /* enable edge detecting */
 449     GPIOA_IS &= ~(1<<2);
 450     /* detect both raising and falling edges */
 451     GPIOA_IBE |= (1<<2);
 452
 453 #endif
 454
 455 #else
 456     VIC_INT_ENABLE |= INTERRUPT_NAND;
 457 #endif
 458
 459     MCI_POWER(drive) = MCI_POWER_UP|(10 /*voltage*/ << 2); /* use OF voltage */
 460     mci_delay();
 461
 462     MCI_POWER(drive) |= MCI_POWER_ON;
 463     mci_delay();
 464
 465     MCI_SELECT(drive) = 0;
 466
 467     MCI_CLOCK(drive) = MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV;
 468     mci_delay();
 469 }
 470
 471 int sd_init(void)
 472 {
 473     int ret;
 474     CGU_IDE =   (1<<7)  /* AHB interface enable */  |
 475                 (1<<6)  /* interface enable */      |
 476                 (AS3525_IDE_DIV << 2)               |
 477                 AS3525_CLK_PLLA;  /* clock source = PLLA */
 478
 479
 480     CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 481 #ifdef HAVE_MULTIDRIVE
 482     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 483     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 484     CCU_IO |= (1<<2);
 485 #endif
 486
 487     wakeup_init(&transfer_completion_signal);
 488
 489     init_pl180_controller(INTERNAL_AS3525);
 490     ret = sd_init_card(INTERNAL_AS3525);
 491     if(ret < 0)
 492         return ret;
 493 #ifdef HAVE_MULTIDRIVE
 494     init_pl180_controller(SD_SLOT_AS3525);
 495 #endif
 496
 497     /* init mutex */
 498     mutex_init(&sd_mtx);
 499
 500     queue_init(&sd_queue, true);
 501     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 502             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 503
 504 #ifndef BOOTLOADER
 505     sd_enabled = true;
 506     sd_enable(false);
 507 #endif
 508     return 0;
 509 }
 510
 511 #ifdef HAVE_HOTSWAP
 512 bool sd_removable(IF_MD_NONVOID(int drive))
 513 {
 514 #ifndef HAVE_MULTIDRIVE
 515     const int drive=0;
 516 #endif
 517     return (drive==1);
 518 }
 519
 520 bool sd_present(IF_MD_NONVOID(int drive))
 521 {
 522 #ifndef HAVE_MULTIDRIVE
 523     const int drive=0;
 524 #endif
 525     if(drive==0)
 526     {
 527         return true;
 528     }
 529     else
 530     {
 531         return card_detect_target();
 532     }
 533 }
 534 #endif
 535
 536 static int sd_wait_for_state(const int drive, unsigned int state)
 537 {
 538     unsigned long response = 0;
 539     unsigned int timeout = 100; /* ticks */
 540     long t = current_tick;
 541
 542     while (1)
 543     {
 544         long tick;
 545
 546         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
 547                     MCI_RESP|MCI_ARG, &response))
 548             return -1;
 549
 550         if (((response >> 9) & 0xf) == state)
 551             return 0;
 552
 553         if(TIME_AFTER(current_tick, t + timeout))
 554             return -2;
 555
 556         if (TIME_AFTER((tick = current_tick), next_yield))
 557         {
 558             yield();
 559             timeout += current_tick - tick;
 560             next_yield = tick + MIN_YIELD_PERIOD;
 561         }
 562     }
 563 }
 564
 565 static int sd_select_bank(signed char bank)
 566 {
 567     int ret;
 568     unsigned loops = 0;
 569
 570     do {
 571         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 572             panicf("SD bank %d error : 0x%x", bank,
 573                     transfer_error[INTERNAL_AS3525]);
 574
 575         ret = sd_wait_for_state(INTERNAL_AS3525, SD_TRAN);
 576         if (ret < 0)
 577             return ret - 2;
 578
 579         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_ARG, NULL))
 580             return -1;
 581
 582         mci_delay();
 583
 584         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_FLAGS, NULL))
 585             return -2;
 586
 587         mci_delay();
 588
 589         memset(uncached_buffer, 0, 512);
 590         if(bank == -1)
 591         {   /* enable bank switching */
 592             uncached_buffer[0] = 16;
 593             uncached_buffer[1] = 1;
 594             uncached_buffer[2] = 10;
 595         }
 596         else
 597             uncached_buffer[0] = bank;
 598
 599         dma_retain();
 600         /* we don't use the uncached buffer here, because we need the
 601          * physical memory address for DMA transfers */
 602         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 603             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 604             NULL);
 605
 606         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 607         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 608         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 609                                 (0<<1) /* transfer direction */ |
 610                                 (1<<3) /* DMA */                |
 611                                 (9<<4) /* 2^9 = 512 */ ;
 612
 613         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 614
 615         dma_release();
 616
 617         mci_delay();
 618
 619         ret = sd_wait_for_state(INTERNAL_AS3525, SD_TRAN);
 620         if (ret < 0)
 621             return ret - 4;
 622     } while(transfer_error[INTERNAL_AS3525]);
 623
 624     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 625
 626     return 0;
 627 }
 628
 629 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 630                                int count, void* buf, const bool write)
 631 {
 632 #ifndef HAVE_MULTIDRIVE
 633     const int drive = 0;
 634 #endif
 635     int ret = 0;
 636     unsigned loops = 0;
 637
 638     /* skip SanDisk OF */
 639     if (drive == INTERNAL_AS3525)
 640         start += AMS_OF_SIZE;
 641
 642     mutex_lock(&sd_mtx);
 643 #ifndef BOOTLOADER
 644     sd_enable(true);
 645     led(true);
 646 #endif
 647
 648     if (card_info[drive].initialized <= 0)
 649     {
 650         ret = sd_init_card(drive);
 651         if (!(card_info[drive].initialized))
 652             goto sd_transfer_error;
 653     }
 654
 655     last_disk_activity = current_tick;
 656
 657     ret = sd_wait_for_state(drive, SD_TRAN);
 658     if (ret < 0)
 659     {
 660         ret -= 20;
 661         goto sd_transfer_error;
 662     }
 663
 664     dma_retain();
 665
 666     while(count)
 667     {
 668         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 669          * register, so we have to transfer maximum 127 sectors at a time. */
 670         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 671         void *dma_buf;
 672         const int cmd =
 673             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 674         unsigned long bank_start = start;
 675
 676         /* Only switch banks for internal storage */
 677         if(drive == INTERNAL_AS3525)
 678         {
 679             unsigned int bank = start / BLOCKS_PER_BANK; /* Current bank */
 680
 681             /* Switch bank if needed */
 682             if(card_info[INTERNAL_AS3525].current_bank != bank)
 683             {
 684                 ret = sd_select_bank(bank);
 685                 if (ret < 0)
 686                 {
 687                     ret -= 2*20;
 688                     goto sd_transfer_error;
 689                 }
 690             }
 691
 692             /* Adjust start block in current bank */
 693             bank_start -= bank * BLOCKS_PER_BANK;
 694
 695             /* Do not cross a bank boundary in a single transfer loop */
 696             if((transfer + bank_start) > BLOCKS_PER_BANK)
 697                 transfer = BLOCKS_PER_BANK - bank_start;
 698         }
 699
 700         dma_buf = aligned_buffer;
 701         if(transfer > UNALIGNED_NUM_SECTORS)
 702             transfer = UNALIGNED_NUM_SECTORS;
 703         if(write)
 704             memcpy(uncached_buffer, buf, transfer * SECTOR_SIZE);
 705
 706         /* Set bank_start to the correct unit (blocks or bytes) */
 707         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 708             bank_start *= SD_BLOCK_SIZE;
 709
 710         if(!send_cmd(drive, cmd, bank_start, MCI_ARG, NULL))
 711         {
 712             ret -= 3*20;
 713             goto sd_transfer_error;
 714         }
 715
 716         if(write)
 717             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 718                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 719                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 720         else
 721             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 722                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 723                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 724
 725         /* FIXME : we should check if the timeouts calculated from the card's
 726          * CSD are lower, and use them if it is the case
 727          * Note : the OF doesn't seem to use them anyway */
 728         MCI_DATA_TIMER(drive) = write ?
 729                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 730         MCI_DATA_LENGTH(drive) = transfer * card_info[drive].blocksize;
 731         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 732                                 (!write<<1) /* transfer direction */    |
 733                                 (1<<3) /* DMA */                        |
 734                                 (9<<4) /* 2^9 = 512 */ ;
 735
 736
 737         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 738         if(!transfer_error[drive])
 739         {
 740             if(!write)
 741                 memcpy(buf, uncached_buffer, transfer * SECTOR_SIZE);
 742             buf += transfer * SECTOR_SIZE;
 743             start += transfer;
 744             count -= transfer;
 745             loops = 0;  /* reset errors counter */
 746         }
 747         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 748                 panicf("SD transfer error : 0x%x", transfer_error[drive]);
 749
 750         last_disk_activity = current_tick;
 751
 752         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_FLAGS, NULL))
 753         {
 754             ret = -4*20;
 755             goto sd_transfer_error;
 756         }
 757
 758         ret = sd_wait_for_state(drive, SD_TRAN);
 759         if (ret < 0)
 760         {
 761             ret -= 5*20;
 762             goto sd_transfer_error;
 763         }
 764     }
 765
 766     ret = 0;    /* success */
 767
 768 sd_transfer_error:
 769
 770     dma_release();
 771
 772 #ifndef BOOTLOADER
 773     led(false);
 774     sd_enable(false);
 775 #endif
 776
 777     if (ret)    /* error */
 778         card_info[drive].initialized = 0;
 779
 780     mutex_unlock(&sd_mtx);
 781     return ret;
 782 }
 783
 784 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 785                      void* buf)
 786 {
 787     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 788 }
 789
 790 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 791                      const void* buf)
 792 {
 793
 794 #ifdef BOOTLOADER /* we don't need write support in bootloader */
 795 #ifdef HAVE_MULTIDRIVE
 796     (void) drive;
 797 #endif
 798     (void) start;
 799     (void) count;
 800     (void) buf;
 801     return -1;
 802 #else
 803     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 804 #endif
 805 }
 806
 807 #ifndef BOOTLOADER
 808 long sd_last_disk_activity(void)
 809 {
 810     return last_disk_activity;
 811 }
 812
 813 void sd_enable(bool on)
 814 {
 815     /* buttonlight AMSes need a bit of special handling for the buttonlight here,
 816      * due to the dual mapping of GPIOD and XPD */
 817 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 818     extern int buttonlight_is_on;
 819 #endif
 820     if (sd_enabled == on)
 821         return; /* nothing to do */
 822     if(on)
 823     {
 824         CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 825 #ifdef HAVE_MULTIDRIVE
 826         CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 827 #ifdef HAVE_BUTTON_LIGHT
 828         CCU_IO |= (1<<2);
 829         if (buttonlight_is_on)
 830             GPIOD_DIR &= ~(1<<7);
 831         else
 832             _buttonlight_off();
 833 #endif
 834 #endif
 835         CGU_IDE |= (1<<7)  /* AHB interface enable */  |
 836                    (1<<6)  /* interface enable */;
 837         sd_enabled = true;
 838     }
 839     else
 840     {
 841         CGU_PERI &= ~CGU_NAF_CLOCK_ENABLE;
 842 #ifdef HAVE_MULTIDRIVE
 843 #ifdef HAVE_BUTTON_LIGHT
 844         CCU_IO &= ~(1<<2);
 845         if (buttonlight_is_on)
 846             _buttonlight_on();
 847 #endif
 848         CGU_PERI &= ~CGU_MCI_CLOCK_ENABLE;
 849 #endif
 850         CGU_IDE &= ~((1<<7)|(1<<6));
 851         sd_enabled = false;
 852     }
 853 }
 854
 855 tCardInfo *card_get_info_target(int card_no)
 856 {
 857     return &card_info[card_no];
 858 }
 859
 860 bool card_detect_target(void)
 861 {
 862 #if defined(HAVE_HOTSWAP) && \
 863     (defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2))
 864     return !(GPIOA_PIN(2));
 865 #else
 866     return false;
 867 #endif
 868 }
 869
 870 #ifdef HAVE_HOTSWAP
 871 void card_enable_monitoring_target(bool on)
 872 {
 873     if (on)
 874     {
 875     /* add e200v2/c200v2 here */
 876 #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
 877         /* enable isr*/
 878         GPIOA_IE |= (1<<2);
 879 #endif
 880     }
 881     else
 882     {
 883 #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
 884         /* edisable isr*/
 885         GPIOA_IE &= ~(1<<2);
 886 #endif
 887     }
 888 }
 889 #endif
 890
 891 #endif /* BOOTLOADER */
 892
 893 #ifdef CONFIG_STORAGE_MULTI
 894 int sd_num_drives(int first_drive)
 895 {
 896     /* We don't care which logical drive number(s) we have been assigned */
 897     (void)first_drive;
 898
 899 #ifdef HAVE_MULTIDRIVE
 900     return 2;
 901 #else
 902     return 1;
 903 #endif
 904 }
 905 #endif