firmware/target/arm/as3525/ata_sd_as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 /* TODO: Find the real capacity of >2GB models (will be useful for USB) */
  26
  27 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  28 #include "fat.h"
  29 #include "thread.h"
  30 #include "led.h"
  31 #include "hotswap.h"
  32 #include "system.h"
  33 #include "cpu.h"
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include "as3525.h"
  38 #include "pl180.h"  /* SD controller */
  39 #include "pl081.h"  /* DMA controller */
  40 #include "dma-target.h" /* DMA request lines */
  41 #include "clock-target.h"
  42 #include "panic.h"
  43 #ifdef HAVE_BUTTON_LIGHT
  44 #include "backlight-target.h"
  45 #endif
  46 #include "stdbool.h"
  47 #include "ata_idle_notify.h"
  48 #include "sd.h"
  49 #include "usb.h"
  50
  51 #ifdef HAVE_HOTSWAP
  52 #include "disk.h"
  53 #endif
  54
  55 /* command flags */
  56 #define MCI_NO_FLAGS    (0<<0)
  57 #define MCI_RESP        (1<<0)
  58 #define MCI_LONG_RESP   (1<<1)
  59 #define MCI_ARG         (1<<2)
  60
  61 /* ARM PL180 registers */
  62 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  63 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  64 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  65 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  66 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  67 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  68 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  69 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  70 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  71 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  72 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  73 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  74 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  75 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  76 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  77 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  78 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  79 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  80 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  81
  82 #define MCI_ERROR \
  83     (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_TX_UNDERRUN)
  84
  85 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  86 /* volumes */
  87 #define     INTERNAL_AS3525 0   /* embedded SD card */
  88 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  89
  90 static const int pl180_base[NUM_DRIVES] = {
  91             NAND_FLASH_BASE
  92 #ifdef HAVE_MULTIDRIVE
  93             , SD_MCI_BASE
  94 #endif
  95 };
  96
  97 static int sd_wait_for_state(const int drive, unsigned int state);
  98 static int sd_select_bank(signed char bank);
  99 static int sd_init_card(const int drive);
 100 static void init_pl180_controller(const int drive);
 101
 102 #define BLOCKS_PER_BANK 0x7a7800
 103
 104 static tCardInfo card_info[NUM_DRIVES];
 105
 106 /* maximum timeouts recommanded in the SD Specification v2.00 */
 107 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 108 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 109
 110 /* for compatibility */
 111 static long last_disk_activity = -1;
 112
 113 #define MIN_YIELD_PERIOD 5  /* ticks */
 114 static long next_yield = 0;
 115
 116 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 117 static const char         sd_thread_name[] = "ata/sd";
 118 static struct mutex       sd_mtx;
 119 static struct event_queue sd_queue;
 120 #ifndef BOOTLOADER
 121 bool sd_enabled = false;
 122 #endif
 123
 124 static struct wakeup transfer_completion_signal;
 125 static volatile unsigned int transfer_error[NUM_VOLUMES];
 126 #define PL180_MAX_TRANSFER_ERRORS 10
 127
 128 #define UNALIGNED_NUM_SECTORS 10
 129 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 130 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 131
 132 static inline void mci_delay(void)
 133 {
 134     int i = 0xffff;
 135     do {
 136         asm volatile("nop\n");
 137     } while (--i);
 138 }
 139
 140
 141 static inline bool card_detect_target(void)
 142 {
 143 #if defined(HAVE_MULTIDRIVE)
 144     return !(GPIOA_PIN(2));
 145 #else
 146     return false;
 147 #endif
 148 }
 149
 150 #ifdef HAVE_HOTSWAP
 151 static int sd1_oneshot_callback(struct timeout *tmo)
 152 {
 153     (void)tmo;
 154
 155     /* This is called only if the state was stable for 300ms - check state
 156      * and post appropriate event. */
 157     if (card_detect_target())
 158     {
 159         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 160     }
 161     else
 162         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 163
 164     return 0;
 165 }
 166
 167 void INT_GPIOA(void)
 168 {
 169     static struct timeout sd1_oneshot;
 170     /* acknowledge interrupt */
 171     GPIOA_IC = (1<<2);
 172     timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 173 }
 174 #endif  /* HAVE_HOTSWAP */
 175
 176 void INT_NAND(void)
 177 {
 178     const int status = MCI_STATUS(INTERNAL_AS3525);
 179
 180     transfer_error[INTERNAL_AS3525] = status & MCI_ERROR;
 181
 182     wakeup_signal(&transfer_completion_signal);
 183     MCI_CLEAR(INTERNAL_AS3525) = status;
 184 }
 185
 186 #ifdef HAVE_MULTIDRIVE
 187 void INT_MCI0(void)
 188 {
 189     const int status = MCI_STATUS(SD_SLOT_AS3525);
 190
 191     transfer_error[SD_SLOT_AS3525] = status & MCI_ERROR;
 192
 193     wakeup_signal(&transfer_completion_signal);
 194     MCI_CLEAR(SD_SLOT_AS3525) = status;
 195 }
 196 #endif
 197
 198 static bool send_cmd(const int drive, const int cmd, const int arg,
 199                      const int flags, long *response)
 200 {
 201     int status;
 202
 203     /* Clear old status flags */
 204     MCI_CLEAR(drive) = 0x7ff;
 205
 206     /* Load command argument or clear if none */
 207     MCI_ARGUMENT(drive) = (flags & MCI_ARG) ? arg : 0;
 208
 209     /* Construct MCI_COMMAND & enable CPSM */
 210     MCI_COMMAND(drive) =
 211        /*b0:5*/  cmd
 212        /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 213        /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 214        /* b8   | MCI_COMMAND_INTERRUPT */
 215        /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 216        /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 217
 218     /* Wait while cmd completes then disable CPSM */
 219     while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 220     MCI_COMMAND(drive) = 0;
 221
 222     status = MCI_STATUS(drive);
 223
 224     /*  Handle command responses */
 225     if(flags & MCI_RESP)                   /*  CMD expects response  */
 226     {
 227         response[0] = MCI_RESP0(drive);    /*  Always prepare short response  */
 228
 229         if(status & (MCI_CMD_TIMEOUT | MCI_CMD_CRC_FAIL))  /* failed response */
 230             return false;
 231
 232         if(status &  MCI_CMD_RESP_END)            /*Response passed CRC check */
 233         {
 234             if(flags & MCI_LONG_RESP)
 235             {   /* replace short response with long response */
 236                 /* store the response in reverse words order */
 237                 response[0] = MCI_RESP3(drive);
 238                 response[1] = MCI_RESP2(drive);
 239                 response[2] = MCI_RESP1(drive);
 240                 response[3] = MCI_RESP0(drive);
 241             }
 242             return true;
 243         }
 244     }
 245     else if(status & MCI_CMD_SENT)          /* CMD sent, no response required */
 246         return true;
 247
 248     return false;
 249 }
 250
 251 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 252 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 253 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 254 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 255
 256 static int sd_init_card(const int drive)
 257 {
 258     unsigned long response;
 259     long init_timeout;
 260     bool sd_v2 = false;
 261     unsigned long temp_reg[4];
 262     int i;
 263
 264
 265     /* MCLCK on and set to 400kHz ident frequency  */
 266     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 267
 268     /* 100 - 400kHz clock required for Identification Mode  */
 269     /*  Start of Card Identification Mode ************************************/
 270
 271     /* CMD0 Go Idle  */
 272     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_FLAGS, NULL))
 273         return -1;
 274
 275     mci_delay();
 276
 277     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 278       Non v2 cards will not respond to this command*/
 279     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP|MCI_ARG, &response))
 280         if((response & 0xFFF) == 0x1AA)
 281             sd_v2 = true;
 282
 283     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 284     init_timeout = current_tick + HZ;
 285
 286     do {
 287         /* this timeout is the only valid error for this loop*/
 288         if(TIME_AFTER(current_tick, init_timeout))
 289             return -2;
 290
 291         /* app_cmd */
 292         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP|MCI_ARG, &response);
 293
 294         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 295         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 296                         MCI_RESP|MCI_ARG, &card_info[drive].ocr);
 297
 298     } while(!(card_info[drive].ocr & (1<<31)));
 299
 300     /* CMD2 send CID */
 301     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP|MCI_ARG,
 302                             temp_reg))
 303         return -3;
 304
 305     for(i=0; i<4; i++)
 306         card_info[drive].cid[3-i] = temp_reg[i];
 307
 308     /* CMD3 send RCA */
 309     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP|MCI_ARG,
 310                 &card_info[drive].rca))
 311         return -4;
 312
 313     /*  End of Card Identification Mode   ************************************/
 314
 315     /* Boost MCICLK to operating speed */ /*FIXME: v1 at 31 MHz still too high*/
 316     MCI_CLOCK(drive) = (sd_v2 ? MCI_HALFSPEED : MCI_HALFSPEED);
 317
 318 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 319
 320     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 321     if(sd_v2)
 322     {
 323         /*  CMD7 w/rca: Select card to put it in TRAN state */
 324         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 325             return -5;
 326
 327         if(sd_wait_for_state(drive, SD_TRAN))
 328             return -6;
 329         /* CMD6 */
 330         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_ARG, NULL))
 331             return -7;
 332         mci_delay();
 333
 334         /*  go back to STBY state so we can read csd */
 335         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 336         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_ARG, NULL))
 337             return -8;
 338     }
 339 #endif /*  HAVE_MULTIDRIVE  */
 340
 341     /* CMD9 send CSD */
 342     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 343                  MCI_RESP|MCI_LONG_RESP|MCI_ARG, temp_reg))
 344         return -9;
 345
 346     for(i=0; i<4; i++)
 347         card_info[drive].csd[3-i] = temp_reg[i];
 348
 349     sd_parse_csd(&card_info[drive]);
 350
 351     /*  CMD7 w/rca: Select card to put it in TRAN state */
 352     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 353         return -10;
 354
 355     /*
 356      * enable bank switching
 357      * without issuing this command, we only have access to 1/4 of the blocks
 358      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 359      * CSD register)
 360      */
 361     if(drive == INTERNAL_AS3525)
 362     {
 363         const int ret = sd_select_bank(-1);
 364         if(ret < 0)
 365             return ret - 11;
 366     }
 367
 368     card_info[drive].initialized = 1;
 369
 370     return 0;
 371 }
 372
 373 static void sd_thread(void) __attribute__((noreturn));
 374 static void sd_thread(void)
 375 {
 376     struct queue_event ev;
 377     bool idle_notified = false;
 378
 379     while (1)
 380     {
 381         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 382
 383         switch ( ev.id )
 384         {
 385 #ifdef HAVE_HOTSWAP
 386         case SYS_HOTSWAP_INSERTED:
 387         case SYS_HOTSWAP_EXTRACTED:
 388         {
 389             int microsd_init = 1;
 390             fat_lock();          /* lock-out FAT activity first -
 391                                     prevent deadlocking via disk_mount that
 392                                     would cause a reverse-order attempt with
 393                                     another thread */
 394             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 395                                     into driver that bypass the fat cache */
 396
 397             /* We now have exclusive control of fat cache and ata */
 398
 399             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 400                                     descriptors aren't leaked and any busy
 401                                     ones are invalid if mounting */
 402
 403             /* Force card init for new card, re-init for re-inserted one or
 404              * clear if the last attempt to init failed with an error. */
 405             card_info[SD_SLOT_AS3525].initialized = 0;
 406
 407             if (ev.id == SYS_HOTSWAP_INSERTED)
 408             {
 409                 sd_enable(true);
 410                 init_pl180_controller(SD_SLOT_AS3525);
 411                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 412                 if (microsd_init < 0) /* initialisation failed */
 413                     panicf("microSD init failed : %d", microsd_init);
 414
 415                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 416             }
 417
 418             /*
 419              * Mount succeeded, or this was an EXTRACTED event,
 420              * in both cases notify the system about the changed filesystems
 421              */
 422             if (microsd_init)
 423                 queue_broadcast(SYS_FS_CHANGED, 0);
 424
 425             /* Access is now safe */
 426             mutex_unlock(&sd_mtx);
 427             fat_unlock();
 428             sd_enable(false);
 429         }
 430             break;
 431 #endif
 432         case SYS_TIMEOUT:
 433             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 434             {
 435                 idle_notified = false;
 436             }
 437             else
 438             {
 439                 /* never let a timer wrap confuse us */
 440                 next_yield = current_tick;
 441
 442                 if (!idle_notified)
 443                 {
 444                     call_storage_idle_notifys(false);
 445                     idle_notified = true;
 446                 }
 447             }
 448             break;
 449
 450         case SYS_USB_CONNECTED:
 451             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 452             /* Wait until the USB cable is extracted again */
 453             usb_wait_for_disconnect(&sd_queue);
 454
 455             break;
 456         case SYS_USB_DISCONNECTED:
 457             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 458             break;
 459         }
 460     }
 461 }
 462
 463 static void init_pl180_controller(const int drive)
 464 {
 465     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 466     MCI_CLEAR(drive) = 0x7ff;
 467
 468     MCI_MASK0(drive) = MCI_ERROR | MCI_DATA_END;
 469     MCI_MASK1(drive) = 0;
 470 #ifdef HAVE_MULTIDRIVE
 471     VIC_INT_ENABLE =
 472         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 473
 474     /* setup isr for microsd monitoring */
 475     VIC_INT_ENABLE = (INTERRUPT_GPIOA);
 476     /* clear previous irq */
 477     GPIOA_IC = (1<<2);
 478     /* enable edge detecting */
 479     GPIOA_IS &= ~(1<<2);
 480     /* detect both raising and falling edges */
 481     GPIOA_IBE |= (1<<2);
 482
 483 #else
 484     VIC_INT_ENABLE = INTERRUPT_NAND;
 485 #endif
 486
 487     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 488     mci_delay();
 489
 490     MCI_POWER(drive) |= MCI_POWER_ON;
 491     mci_delay();
 492
 493     MCI_SELECT(drive) = 0;
 494
 495     /* Pl180 clocks get turned on at start of card init */
 496 }
 497
 498 int sd_init(void)
 499 {
 500     int ret;
 501     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 502             |   (AS3525_IDE_DIV << 2)
 503             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 504
 505     CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 506 #ifdef HAVE_MULTIDRIVE
 507     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 508     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 509     CCU_IO |= (1<<2);
 510 #endif
 511
 512     wakeup_init(&transfer_completion_signal);
 513
 514     init_pl180_controller(INTERNAL_AS3525);
 515     ret = sd_init_card(INTERNAL_AS3525);
 516     if(ret < 0)
 517         return ret;
 518 #ifdef HAVE_MULTIDRIVE
 519     init_pl180_controller(SD_SLOT_AS3525);
 520 #endif
 521
 522     /* init mutex */
 523     mutex_init(&sd_mtx);
 524
 525     queue_init(&sd_queue, true);
 526     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 527             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 528
 529 #ifndef BOOTLOADER
 530     sd_enabled = true;
 531     sd_enable(false);
 532 #endif
 533     return 0;
 534 }
 535
 536 #ifdef HAVE_HOTSWAP
 537 bool sd_removable(IF_MD_NONVOID(int drive))
 538 {
 539     return (drive==1);
 540 }
 541
 542 bool sd_present(IF_MD_NONVOID(int drive))
 543 {
 544     return (drive == 0) ? true : card_detect_target();
 545 }
 546 #endif /* HAVE_HOTSWAP */
 547
 548 static int sd_wait_for_state(const int drive, unsigned int state)
 549 {
 550     unsigned long response = 0;
 551     unsigned int timeout = current_tick + 100; /* 100 ticks timeout */
 552
 553     while (1)
 554     {
 555         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
 556                     MCI_RESP|MCI_ARG, &response))
 557             return -1;
 558
 559         if (((response >> 9) & 0xf) == state)
 560             return 0;
 561
 562         if(TIME_AFTER(current_tick, timeout))
 563             return -2;
 564
 565         if (TIME_AFTER(current_tick, next_yield))
 566         {
 567             yield();
 568             next_yield = current_tick + MIN_YIELD_PERIOD;
 569         }
 570     }
 571 }
 572
 573 static int sd_select_bank(signed char bank)
 574 {
 575     int ret;
 576     unsigned loops = 0;
 577
 578     do {
 579         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 580             panicf("SD bank %d error : 0x%x", bank,
 581                     transfer_error[INTERNAL_AS3525]);
 582
 583         ret = sd_wait_for_state(INTERNAL_AS3525, SD_TRAN);
 584         if (ret < 0)
 585             return ret - 2;
 586
 587         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_ARG, NULL))
 588             return -1;
 589
 590         mci_delay();
 591
 592         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_FLAGS, NULL))
 593             return -2;
 594
 595         mci_delay();
 596
 597         memset(uncached_buffer, 0, 512);
 598         if(bank == -1)
 599         {   /* enable bank switching */
 600             uncached_buffer[0] = 16;
 601             uncached_buffer[1] = 1;
 602             uncached_buffer[2] = 10;
 603         }
 604         else
 605             uncached_buffer[0] = bank;
 606
 607         dma_retain();
 608         /* we don't use the uncached buffer here, because we need the
 609          * physical memory address for DMA transfers */
 610         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 611             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 612             NULL);
 613
 614         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 615         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 616         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 617                                 (0<<1) /* transfer direction */ |
 618                                 (1<<3) /* DMA */                |
 619                                 (9<<4) /* 2^9 = 512 */ ;
 620
 621         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 622
 623         /*  Wait for FIFO to empty, card may still be in PRG state  */
 624         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 625
 626         dma_release();
 627
 628     } while(transfer_error[INTERNAL_AS3525]);
 629
 630     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 631
 632     return 0;
 633 }
 634
 635 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 636                                int count, void* buf, const bool write)
 637 {
 638 #ifndef HAVE_MULTIDRIVE
 639     const int drive = 0;
 640 #endif
 641     int ret = 0;
 642     unsigned loops = 0;
 643
 644     /* skip SanDisk OF */
 645     if (drive == INTERNAL_AS3525)
 646         start += AMS_OF_SIZE;
 647
 648     mutex_lock(&sd_mtx);
 649 #ifndef BOOTLOADER
 650     sd_enable(true);
 651     led(true);
 652 #endif
 653
 654     if (card_info[drive].initialized <= 0)
 655     {
 656         ret = sd_init_card(drive);
 657         if (!(card_info[drive].initialized))
 658             goto sd_transfer_error;
 659     }
 660
 661     last_disk_activity = current_tick;
 662
 663     dma_retain();
 664
 665     while(count)
 666     {
 667         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 668          * register, so we have to transfer maximum 127 sectors at a time. */
 669         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 670         void *dma_buf;
 671         const int cmd =
 672             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 673         unsigned long bank_start = start;
 674
 675         /* Only switch banks for internal storage */
 676         if(drive == INTERNAL_AS3525)
 677         {
 678             unsigned int bank = start / BLOCKS_PER_BANK; /* Current bank */
 679
 680             /* Switch bank if needed */
 681             if(card_info[INTERNAL_AS3525].current_bank != bank)
 682             {
 683                 ret = sd_select_bank(bank);
 684                 if (ret < 0)
 685                 {
 686                     ret -= 20;
 687                     goto sd_transfer_error;
 688                 }
 689             }
 690
 691             /* Adjust start block in current bank */
 692             bank_start -= bank * BLOCKS_PER_BANK;
 693
 694             /* Do not cross a bank boundary in a single transfer loop */
 695             if((transfer + bank_start) > BLOCKS_PER_BANK)
 696                 transfer = BLOCKS_PER_BANK - bank_start;
 697         }
 698
 699         dma_buf = aligned_buffer;
 700         if(transfer > UNALIGNED_NUM_SECTORS)
 701             transfer = UNALIGNED_NUM_SECTORS;
 702         if(write)
 703             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 704
 705         /* Set bank_start to the correct unit (blocks or bytes) */
 706         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 707             bank_start *= SD_BLOCK_SIZE;
 708
 709         ret = sd_wait_for_state(drive, SD_TRAN);
 710         if (ret < 0)
 711         {
 712             ret -= 2*20;
 713             goto sd_transfer_error;
 714         }
 715
 716         if(!send_cmd(drive, cmd, bank_start, MCI_ARG, NULL))
 717         {
 718             ret -= 3*20;
 719             goto sd_transfer_error;
 720         }
 721
 722         if(write)
 723             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 724                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 725                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 726         else
 727             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 728                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 729                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 730
 731         /* FIXME : we should check if the timeouts calculated from the card's
 732          * CSD are lower, and use them if it is the case
 733          * Note : the OF doesn't seem to use them anyway */
 734         MCI_DATA_TIMER(drive) = write ?
 735                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 736         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 737         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 738                                 (!write<<1) /* transfer direction */    |
 739                                 (1<<3) /* DMA */                        |
 740                                 (9<<4) /* 2^9 = 512 */ ;
 741
 742         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 743
 744         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 745         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 746
 747         last_disk_activity = current_tick;
 748
 749         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_FLAGS, NULL))
 750         {
 751             ret = -4*20;
 752             goto sd_transfer_error;
 753         }
 754
 755         if(!transfer_error[drive])
 756         {
 757             if(!write)
 758                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 759             buf += transfer * SD_BLOCK_SIZE;
 760             start += transfer;
 761             count -= transfer;
 762             loops = 0;  /* reset errors counter */
 763         }
 764         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 765                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 766                                                   transfer_error[drive], drive);
 767     }
 768
 769     ret = 0;    /* success */
 770
 771 sd_transfer_error:
 772
 773     dma_release();
 774
 775 #ifndef BOOTLOADER
 776     led(false);
 777     sd_enable(false);
 778 #endif
 779
 780     if (ret)    /* error */
 781         card_info[drive].initialized = 0;
 782
 783     mutex_unlock(&sd_mtx);
 784     return ret;
 785 }
 786
 787 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 788                      void* buf)
 789 {
 790     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 791 }
 792
 793 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 794                      const void* buf)
 795 {
 796
 797 #ifdef BOOTLOADER /* we don't need write support in bootloader */
 798 #ifdef HAVE_MULTIDRIVE
 799     (void) drive;
 800 #endif
 801     (void) start;
 802     (void) count;
 803     (void) buf;
 804     return -1;
 805 #else
 806     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 807 #endif
 808 }
 809
 810 #ifndef BOOTLOADER
 811 long sd_last_disk_activity(void)
 812 {
 813     return last_disk_activity;
 814 }
 815
 816 void sd_enable(bool on)
 817 {
 818 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 819     extern int buttonlight_is_on;
 820 #endif
 821
 822 #ifdef HAVE_HOTSWAP
 823     static bool cpu_boosted = false;
 824 #endif
 825
 826     if (sd_enabled == on)
 827         return; /* nothing to do */
 828     if(on)
 829     {
 830         /*  Enable both NAF_CLOCK & IDE clk for internal SD */
 831         CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 832         CGU_IDE  |= (1<<6);     /* enable non AHB interface*/
 833 #ifdef HAVE_MULTIDRIVE
 834         /* Enable MCI clk for uSD */
 835         CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 836 #ifdef HAVE_BUTTON_LIGHT
 837         /* buttonlight AMSes need a bit of special handling for the buttonlight
 838          * here due to the dual mapping of GPIOD and XPD */
 839         CCU_IO |= (1<<2);              /* XPD is SD-MCI interface (b3:2 = 01) */
 840         if (buttonlight_is_on)
 841             GPIOD_DIR &= ~(1<<7);
 842         else
 843             _buttonlight_off();
 844 #endif /* HAVE_BUTTON_LIGHT */
 845 #endif /* HAVE_MULTIDRIVE */
 846         sd_enabled = true;
 847
 848 #ifdef HAVE_HOTSWAP
 849         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 850         {
 851             cpu_boosted = true;
 852             cpu_boost(true);
 853         }
 854 #endif
 855     }
 856     else
 857     {
 858 #ifdef HAVE_HOTSWAP
 859         if(cpu_boosted)
 860         {
 861             cpu_boost(false);
 862             cpu_boosted = false;
 863         }
 864 #endif
 865         sd_enabled = false;
 866
 867 #ifdef HAVE_MULTIDRIVE
 868 #ifdef HAVE_BUTTON_LIGHT
 869         CCU_IO &= ~(1<<2);           /* XPD is general purpose IO (b3:2 = 00) */
 870         if (buttonlight_is_on)
 871             _buttonlight_on();
 872 #endif /* HAVE_BUTTON_LIGHT */
 873         /* Disable MCI clk for uSD */
 874         CGU_PERI &= ~CGU_MCI_CLOCK_ENABLE;
 875 #endif /* HAVE_MULTIDRIVE */
 876
 877         /*  Disable both NAF_CLOCK & IDE clk for internal SD */
 878         CGU_PERI &= ~CGU_NAF_CLOCK_ENABLE;
 879         CGU_IDE &= ~(1<<6);       /* disable non AHB interface*/
 880     }
 881 }
 882
 883 tCardInfo *card_get_info_target(int card_no)
 884 {
 885     return &card_info[card_no];
 886 }
 887
 888 #ifdef HAVE_HOTSWAP
 889 void card_enable_monitoring_target(bool on)
 890 {
 891     if (on) /* enable interrupt */
 892         GPIOA_IE |= (1<<2);
 893     else    /* disable interrupt */
 894         GPIOA_IE &= ~(1<<2);
 895 }
 896 #endif /* HAVE_HOTSWAP */
 897
 898 #endif /* !BOOTLOADER */
 899
 900 #ifdef CONFIG_STORAGE_MULTI
 901 int sd_num_drives(int first_drive)
 902 {
 903     /* We don't care which logical drive number(s) we have been assigned */
 904     (void)first_drive;
 905
 906     return NUM_DRIVES;
 907 }
 908 #endif /* CONFIG_STORAGE_MULTI */