firmware/export/imx31l.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by James Espinoza
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #ifndef __IMX31L_H__
  20 #define __IMX31L_H__
  21
  22 /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
  23
  24 #define REG8_PTR_T  volatile unsigned char *
  25 #define REG16_PTR_T volatile unsigned short *
  26 #define REG32_PTR_T volatile unsigned long *
  27
  28 /* Place in the section with the framebuffer */
  29 #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE)
  30 #define TTB_SIZE      (0x4000)
  31 #define IRAM_SIZE     (0x4000)
  32 #define TTB_BASE      ((unsigned int *)TTB_BASE_ADDR)
  33 #define FRAME         ((void*)0x80100000)
  34 #define FRAME_SIZE    (240*320*2)
  35
  36 #define DEVBSS_ATTR   __attribute__((section(".devbss"),nocommon))
  37 #define QHARRAY_ATTR  __attribute__((section(".qharray"),nocommon))
  38
  39 /*
  40  * AIPS 1
  41  */
  42 #define IRAM_BASE_ADDR          0x1fffc000
  43 #define L2CC_BASE_ADDR          0x30000000
  44 #define AIPS1_BASE_ADDR         0x43F00000
  45 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
  46 #define MAX_BASE_ADDR           0x43F04000
  47 #define EVTMON_BASE_ADDR        0x43F08000
  48 #define CLKCTL_BASE_ADDR        0x43F0C000
  49 #define ETB_SLOT4_BASE_ADDR     0x43F10000
  50 #define ETB_SLOT5_BASE_ADDR     0x43F14000
  51 #define ECT_CTIO_BASE_ADDR      0x43F18000
  52 #define I2C_BASE_ADDR           0x43F80000
  53 #define I2C3_BASE_ADDR          0x43F84000
  54 #define OTG_BASE_ADDR           0x43F88000
  55 #define ATA_BASE_ADDR           0x43F8C000
  56 #define UART1_BASE_ADDR         0x43F90000
  57 #define UART2_BASE_ADDR         0x43F94000
  58 #define I2C2_BASE_ADDR          0x43F98000
  59 #define OWIRE_BASE_ADDR         0x43F9C000
  60 #define SSI1_BASE_ADDR          0x43FA0000
  61 #define CSPI1_BASE_ADDR         0x43FA4000
  62 #define KPP_BASE_ADDR           0x43FA8000
  63 #define IOMUXC_BASE_ADDR        0x43FAC000
  64 #define UART4_BASE_ADDR         0x43FB0000
  65 #define UART5_BASE_ADDR         0x43FB4000
  66 #define ECT_IP1_BASE_ADDR       0x43FB8000
  67 #define ECT_IP2_BASE_ADDR       0x43FBC000
  68
  69 /*
  70  * SPBA
  71  */
  72 #define SPBA_BASE_ADDR          0x50000000
  73 #define MMC_SDHC1_BASE_ADDR     0x50004000
  74 #define MMC_SDHC2_BASE_ADDR     0x50008000
  75 #define UART3_BASE_ADDR         0x5000C000
  76 #define CSPI2_BASE_ADDR         0x50010000
  77 #define SSI2_BASE_ADDR          0x50014000
  78 #define SIM_BASE_ADDR           0x50018000
  79 #define IIM_BASE_ADDR           0x5001C000
  80 #define ATA_DMA_BASE_ADDR       0x50020000
  81 #define SPBA_CTRL_BASE_ADDR     0x5003C000
  82
  83 /*
  84  * AIPS 2
  85  */
  86 #define AIPS2_BASE_ADDR         0x53F00000
  87 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
  88 #define CCM_BASE_ADDR           0x53F80000
  89 #define CSPI3_BASE_ADDR         0x53F84000
  90 #define FIRI_BASE_ADDR          0x53F8C000
  91 #define GPT1_BASE_ADDR          0x53F90000
  92 #define EPIT1_BASE_ADDR         0x53F94000
  93 #define EPIT2_BASE_ADDR         0x53F98000
  94 #define GPIO3_BASE_ADDR         0x53FA4000
  95 #define SCC_BASE                0x53FAC000
  96 #define SCM_BASE                0x53FAE000
  97 #define SMN_BASE                0x53FAF000
  98 #define RNGA_BASE_ADDR          0x53FB0000
  99 #define IPU_CTRL_BASE_ADDR      0x53FC0000
 100 #define AUDMUX_BASE             0x53FC4000
 101 #define MPEG4_ENC_BASE          0x53FC8000
 102 #define GPIO1_BASE_ADDR         0x53FCC000
 103 #define GPIO2_BASE_ADDR         0x53FD0000
 104 #define SDMA_BASE_ADDR          0x53FD4000
 105 #define RTC_BASE_ADDR           0x53FD8000
 106 #define WDOG_BASE_ADDR          0x53FDC000
 107 #define PWM_BASE_ADDR           0x53FE0000
 108 #define RTIC_BASE_ADDR          0x53FEC000
 109
 110 #define WDOG1_BASE_ADDR         WDOG_BASE_ADDR
 111 #define CRM_MCU_BASE_ADDR       CCM_BASE_ADDR
 112
 113 /* IOMUXC */
 114 #define IOMUXC_(o)              (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o)))
 115
 116 /* GPR */
 117 #define IOMUXC_GPR              IOMUXC_(0x008)
 118
 119 /* SW_MUX_CTL */
 120 #define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD          IOMUXC_(0x00C)
 121 #define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI              IOMUXC_(0x010)
 122 #define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK                  IOMUXC_(0x014)
 123 #define SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0                IOMUXC_(0x018)
 124 #define SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0                     IOMUXC_(0x01C)
 125 #define SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS                        IOMUXC_(0x020)
 126 #define SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ                             IOMUXC_(0x024)
 127 #define SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1                           IOMUXC_(0x028)
 128 #define SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I                           IOMUXC_(0x02C)
 129 #define SW_MUX_CTL_LD15_LD16_LD17_VSYNC0                                IOMUXC_(0x030)
 130 #define SW_MUX_CTL_LD11_LD12_LD13_LD14                                  IOMUXC_(0x034)
 131 #define SW_MUX_CTL_LD7_LD8_LD9_LD10                                     IOMUXC_(0x038)
 132 #define SW_MUX_CTL_LD3_LD4_LD5_LD6                                      IOMUXC_(0x03C)
 133 #define SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2                              IOMUXC_(0x040)
 134 #define SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0            IOMUXC_(0x044)
 135 #define SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK     IOMUXC_(0x048)
 136 #define SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4  IOMUXC_(0x04C)
 137 #define SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0        IOMUXC_(0x050)
 138 #define SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK                    IOMUXC_(0x054)
 139 #define SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD                               IOMUXC_(0x058)
 140 #define SW_MUX_CTL_RTCK_TCK_TMS_TDI                                     IOMUXC_(0x05C)
 141 #define SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7                  IOMUXC_(0x060)
 142 #define SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3                  IOMUXC_(0x064)
 143 #define SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7                  IOMUXC_(0x068)
 144 #define SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3                  IOMUXC_(0x06C)
 145 #define SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE                             IOMUXC_(0x070)
 146 #define SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2                       IOMUXC_(0x074)
 147 #define SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1                   IOMUXC_(0x078)
 148 #define SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1                          IOMUXC_(0x07C)
 149 #define SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1                   IOMUXC_(0x080)
 150 #define SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2             IOMUXC_(0x084)
 151 #define SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI        IOMUXC_(0x088)
 152 #define SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1            IOMUXC_(0x08C)
 153 #define SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6                                IOMUXC_(0x090)
 154 #define SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5                                IOMUXC_(0x094)
 155 #define SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4                                IOMUXC_(0x098)
 156 #define SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3                                IOMUXC_(0x09C)
 157 #define SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT                 IOMUXC_(0x0A0)
 158 #define SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC                   IOMUXC_(0x0A4)
 159 #define SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13                      IOMUXC_(0x0A8)
 160 #define SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9                          IOMUXC_(0x0AC)
 161 #define SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5                      IOMUXC_(0x0B0)
 162 #define SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE                         IOMUXC_(0x0B4)
 163 #define SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2                        IOMUXC_(0x0B8)
 164 #define SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON                 IOMUXC_(0x0BC)
 165 #define SW_MUX_CTL_D2_D1_D0_PC_CD1_B                                    IOMUXC_(0x0C0)
 166 #define SW_MUX_CTL_D6_D5_D4_D3                                          IOMUXC_(0x0C4)
 167 #define SW_MUX_CTL_D10_D9_D8_D7                                         IOMUXC_(0x0C8)
 168 #define SW_MUX_CTL_D14_D13_D12_D11                                      IOMUXC_(0x0CC)
 169 #define SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15                               IOMUXC_(0x0D0)
 170 #define SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE                            IOMUXC_(0x0D4)
 171 #define SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3                              IOMUXC_(0x0D8)
 172 #define SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B                          IOMUXC_(0x0DC)
 173 #define SW_MUX_CTL_RW_RAS_CAS_SDWE                                      IOMUXC_(0x0E0)
 174 #define SW_MUX_CTL_CS5_ECB_LBA_BCLK                                     IOMUXC_(0x0E4)
 175 #define SW_MUX_CTL_CS1_CS2_CS3_CS4                                      IOMUXC_(0x0E8)
 176 #define SW_MUX_CTL_EB0_EB1_OE_CS0                                       IOMUXC_(0x0EC)
 177 #define SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3                                  IOMUXC_(0x0F0)
 178 #define SW_MUX_CTL_SD28_SD29_SD30_SD31                                  IOMUXC_(0x0F4)
 179 #define SW_MUX_CTL_SD24_SD25_SD26_SD27                                  IOMUXC_(0x0F8)
 180 #define SW_MUX_CTL_SD20_SD21_SD22_SD23                                  IOMUXC_(0x0FC)
 181 #define SW_MUX_CTL_SD16_SD17_SD18_SD19                                  IOMUXC_(0x100)
 182 #define SW_MUX_CTL_SD12_SD13_SD14_SD15                                  IOMUXC_(0x104)
 183 #define SW_MUX_CTL_SD8_SD9_SD10_SD11                                    IOMUXC_(0x108)
 184 #define SW_MUX_CTL_SD4_SD5_SD6_SD7                                      IOMUXC_(0x10C)
 185 #define SW_MUX_CTL_SD0_SD1_SD2_SD3                                      IOMUXC_(0x110)
 186 #define SW_MUX_CTL_A24_A25_SDBA1_SDBA0                                  IOMUXC_(0x114)
 187 #define SW_MUX_CTL_A20_A21_A22_A23                                      IOMUXC_(0x118)
 188 #define SW_MUX_CTL_A16_A17_A18_A19                                      IOMUXC_(0x11C)
 189 #define SW_MUX_CTL_A12_A13_A14_A15                                      IOMUXC_(0x120)
 190 #define SW_MUX_CTL_A9_A10_MA10_A11                                      IOMUXC_(0x124)
 191 #define SW_MUX_CTL_A5_A6_A7_A8                                          IOMUXC_(0x128)
 192 #define SW_MUX_CTL_A1_A2_A3_A4                                          IOMUXC_(0x12C)
 193 #define SW_MUX_CTL_DVFS1_VPG0_VPG1_A0                                   IOMUXC_(0x130)
 194 #define SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0                          IOMUXC_(0x134)
 195 #define SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4          IOMUXC_(0x138)
 196 #define SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0                     IOMUXC_(0x13C)
 197 #define SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH                                IOMUXC_(0x140)
 198 #define SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0                            IOMUXC_(0x144)
 199 #define SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0                      IOMUXC_(0x148)
 200 #define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3                      IOMUXC_(0x14C)
 201 #define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO                    IOMUXC_(0x150)
 202
 203 #define SW_MUX_OUT_EN_GPIO_DR   0x0
 204 #define SW_MUX_OUT_FUNCTIONAL   0x1
 205 #define SW_MUX_OUT_ALTERNATE_1  0x2
 206 #define SW_MUX_OUT_ALTERNATE_2  0x3
 207 #define SW_MUX_OUT_ALTERNATE_3  0x4
 208 #define SW_MUX_OUT_ALTERNATE_4  0x5
 209 #define SW_MUX_OUT_ALTERNATE_5  0x6
 210 #define SW_MUX_OUT_ALTERNATE_6  0x7
 211
 212 #define SW_MUX_IN_NO_INPUTS     0x0
 213 #define SW_MUX_IN_GPIO_PSR_ISR  0x1
 214 #define SW_MUX_IN_FUNCTIONAL    0x2
 215 #define SW_MUX_IN_ALTERNATE_1   0x3
 216 #define SW_MUX_IN_ALTERNATE_2   0x4
 217
 218 /* Shift above flags into one of the four fields in each register */
 219 #define SW_MUX_CTL_FLD_0(x)     ((x) << 0)
 220 #define SW_MUX_CTL_FLD_1(x)     ((x) << 8)
 221 #define SW_MUX_CTL_FLD_2(x)     ((x) << 16)
 222 #define SW_MUX_CTL_FLD_3(x)     ((x) << 24)
 223
 224 /* SW_PAD_CTL */
 225 #define SW_PAD_CTL_TTM_PAD__X__X                            IOMUXC_(0x154)
 226 #define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY      IOMUXC_(0x158)
 227 #define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI              IOMUXC_(0x15C)
 228 #define SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B           IOMUXC_(0x160)
 229 #define SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR                 IOMUXC_(0x164)
 230 #define SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3            IOMUXC_(0x168)
 231 #define SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0                IOMUXC_(0x16C)
 232 #define SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL                     IOMUXC_(0x170)
 233 #define SW_PAD_CTL_READ_VSYNC3_CONTRAST                     IOMUXC_(0x174)
 234 #define SW_PAD_CTL_SER_RS_PAR_RS_WRITE                      IOMUXC_(0x178)
 235 #define SW_PAD_CTL_SD_D_CLK_LCS0_LCS1                       IOMUXC_(0x17C)
 236 #define SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO                     IOMUXC_(0x180)
 237 #define SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT                     IOMUXC_(0x184)
 238 #define SW_PAD_CTL_LD15_LD16_LD17                           IOMUXC_(0x188)
 239 #define SW_PAD_CTL_LD12_LD13_LD14                           IOMUXC_(0x18C)
 240 #define SW_PAD_CTL_LD9_LD10_LD11                            IOMUXC_(0x190)
 241 #define SW_PAD_CTL_LD6_LD7_LD8                              IOMUXC_(0x194)
 242 #define SW_PAD_CTL_LD3_LD4_LD5                              IOMUXC_(0x198)
 243 #define SW_PAD_CTL_LD0_LD1_LD2                              IOMUXC_(0x19C)
 244 #define SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1        IOMUXC_(0x1A0)
 245 #define SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP            IOMUXC_(0x1A4)
 246 #define SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7   IOMUXC_(0x1A8)
 247 #define SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4   IOMUXC_(0x1AC)
 248 #define SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1     IOMUXC_(0x1B0)
 249 #define SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP         IOMUXC_(0x1B4)
 250 #define SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP                   IOMUXC_(0x1B8)
 251 #define SW_PAD_CTL_TRSTB_DE_B_SJC_MOD                       IOMUXC_(0x1BC)
 252 #define SW_PAD_CTL_TMS_TDI_TDO                              IOMUXC_(0x1C0)
 253 #define SW_PAD_CTL_KEY_COL7_RTCK_TCK                        IOMUXC_(0x1C4)
 254 #define SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6               IOMUXC_(0x1C8)
 255 #define SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3               IOMUXC_(0x1CC)
 256 #define SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0               IOMUXC_(0x1D0)
 257 #define SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5               IOMUXC_(0x1D4)
 258 #define SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2               IOMUXC_(0x1D8)
 259 #define SW_PAD_CTL_RTS2_CTS2_BATT_LINE                      IOMUXC_(0x1DC)
 260 #define SW_PAD_CTL_DTR_DCE2_RXD2_TXD2                       IOMUXC_(0x1E0)
 261 #define SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1                IOMUXC_(0x1E4)
 262 #define SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1                IOMUXC_(0x1E8)
 263 #define SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1                   IOMUXC_(0x1EC)
 264 #define SW_PAD_CTL_RXD1_TXD1_RTS1                           IOMUXC_(0x1F0)
 265 #define SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY       IOMUXC_(0x1F4)
 266 #define SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1           IOMUXC_(0x1F8)
 267 #define SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI      IOMUXC_(0x1FC)
 268 #define SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS             IOMUXC_(0x200)
 269 #define SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO               IOMUXC_(0x204)
 270 #define SW_PAD_CTL_STXD6_SRXD6_SCK6                         IOMUXC_(0x208)
 271 #define SW_PAD_CTL_SRXD5_SCK5_SFS5                          IOMUXC_(0x20C)
 272 #define SW_PAD_CTL_SCK4_SFS4_STXD5                          IOMUXC_(0x210)
 273 #define SW_PAD_CTL_SFS3_STXD4_SRXD4                         IOMUXC_(0x214)
 274 #define SW_PAD_CTL_STXD3_SRXD3_SCK3                         IOMUXC_(0x218)
 275 #define SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT               IOMUXC_(0x21C)
 276 #define SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC             IOMUXC_(0x220)
 277 #define SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15                  IOMUXC_(0x224)
 278 #define SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12                  IOMUXC_(0x228)
 279 #define SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9                     IOMUXC_(0x22C)
 280 #define SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6                     IOMUXC_(0x230)
 281 #define SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT                 IOMUXC_(0x234)
 282 #define SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B                    IOMUXC_(0x238)
 283 #define SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2                   IOMUXC_(0x23C)
 284 #define SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1                 IOMUXC_(0x240)
 285 #define SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B              IOMUXC_(0x244)
 286 #define SW_PAD_CTL_D2_D1_D0                                 IOMUXC_(0x248)
 287 #define SW_PAD_CTL_D5_D4_D3                                 IOMUXC_(0x24C)
 288 #define SW_PAD_CTL_D8_D7_D6                                 IOMUXC_(0x250)
 289 #define SW_PAD_CTL_D11_D10_D9                               IOMUXC_(0x254)
 290 #define SW_PAD_CTL_D14_D13_D12                              IOMUXC_(0x258)
 291 #define SW_PAD_CTL_NFCE_B_NFRB_D15                          IOMUXC_(0x25C)
 292 #define SW_PAD_CTL_NFALE_NFCLE_NFWP_B                       IOMUXC_(0x260)
 293 #define SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B                      IOMUXC_(0x264)
 294 #define SW_PAD_CTL_SDQS0_SDQS1_SDQS2                        IOMUXC_(0x268)
 295 #define SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B                     IOMUXC_(0x26C)
 296 #define SW_PAD_CTL_CAS_SDWE_SDCKE0                          IOMUXC_(0x270)
 297 #define SW_PAD_CTL_BCLK_RW_RAS                              IOMUXC_(0x274)
 298 #define SW_PAD_CTL_CS5_ECB_LBA                              IOMUXC_(0x278)
 299 #define SW_PAD_CTL_CS2_CS3_CS4                              IOMUXC_(0x27C)
 300 #define SW_PAD_CTL_OE_CS0_CS1                               IOMUXC_(0x280)
 301 #define SW_PAD_CTL_DQM3_EB0_EB1                             IOMUXC_(0x284)
 302 #define SW_PAD_CTL_DQM0_DQM1_DQM2                           IOMUXC_(0x288)
 303 #define SW_PAD_CTL_SD29_SD30_SD31                           IOMUXC_(0x28C)
 304 #define SW_PAD_CTL_SD26_SD27_SD28                           IOMUXC_(0x290)
 305 #define SW_PAD_CTL_SD23_SD24_SD25                           IOMUXC_(0x294)
 306 #define SW_PAD_CTL_SD20_SD21_SD22                           IOMUXC_(0x298)
 307 #define SW_PAD_CTL_SD17_SD18_SD19                           IOMUXC_(0x29C)
 308 #define SW_PAD_CTL_SD14_SD15_SD16                           IOMUXC_(0x2A0)
 309 #define SW_PAD_CTL_SD11_SD12_SD13                           IOMUXC_(0x2A4)
 310 #define SW_PAD_CTL_SD8_SD9_SD10                             IOMUXC_(0x2A8)
 311 #define SW_PAD_CTL_SD5_SD6_SD7                              IOMUXC_(0x2AC)
 312 #define SW_PAD_CTL_SD2_SD3_SD4                              IOMUXC_(0x2B0)
 313 #define SW_PAD_CTL_SDBA0_SD0_SD1                            IOMUXC_(0x2B4)
 314 #define SW_PAD_CTL_A24_A25_SDBA1                            IOMUXC_(0x2B8)
 315 #define SW_PAD_CTL_A21_A22_A23                              IOMUXC_(0x2BC)
 316 #define SW_PAD_CTL_A18_A19_A20                              IOMUXC_(0x2C0)
 317 #define SW_PAD_CTL_A15_A16_A17                              IOMUXC_(0x2C4)
 318 #define SW_PAD_CTL_A12_A13_A14                              IOMUXC_(0x2C8)
 319 #define SW_PAD_CTL_A10_MA10_A11                             IOMUXC_(0x2CC)
 320 #define SW_PAD_CTL_A7_A8_A9                                 IOMUXC_(0x2D0)
 321 #define SW_PAD_CTL_A4_A5_A6                                 IOMUXC_(0x2D4)
 322 #define SW_PAD_CTL_A1_A2_A3                                 IOMUXC_(0x2D8)
 323 #define SW_PAD_CTL_VPG0_VPG1_A0                             IOMUXC_(0x2DC)
 324 #define SW_PAD_CTL_VSTBY_DVFS0_DVFS1                        IOMUXC_(0x2E0)
 325 #define SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL               IOMUXC_(0x2E4)
 326 #define SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3         IOMUXC_(0x2E8)
 327 #define SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0                    IOMUXC_(0x2EC)
 328 #define SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B                   IOMUXC_(0x2F0)
 329 #define SW_PAD_CTL_SVEN0_STX0_SRX0                          IOMUXC_(0x2F4)
 330 #define SW_PAD_CTL_GPIO3_1_SCLK0_SRST0                      IOMUXC_(0x2F8)
 331 #define SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0                  IOMUXC_(0x2FC)
 332 #define SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4                  IOMUXC_(0x300)
 333 #define SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1                     IOMUXC_(0x304)
 334 #define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST             IOMUXC_(0x308)
 335
 336 /* SW_PAD_CTL flags */
 337 #define SW_PAD_CTL_LOOPBACK                         (1 << 9)
 338 #define SW_PAD_CTL_DISABLE_PULL_UP_DOWN_AND_KEEPER  (0 << 7)
 339 #if 0 /* Same as 0 */
 340 #define SW_PAD_CTL_DISABLE_PULL_UP_DOWN_AND_KEEPER  (1 << 7)
 341 #endif
 342 #define SW_PAD_CTL_ENABLE_KEEPER                    (2 << 7)
 343 #define SW_PAD_CTL_ENABLE_PULL_UP_OR_PULL_DOWN      (3 << 7)
 344 #define SW_PAD_CTL_100K_PULL_DOWN                   (0 << 5)
 345 #define SW_PAD_CTL_100K_PULL_UP                     (1 << 5)
 346 #if 0 /* Completeness */
 347 #define SW_PAD_CTL_47K_PULL_UP                      (2 << 5) /* Not in IMX31/L */
 348 #define SW_PAD_CTL_22K_PULL_UP                      (3 << 5) /* Not in IMX31/L */
 349 #endif
 350 #define SW_PAD_CTL_IPP_HYS_STD                      (0 << 4)
 351 #define SW_PAD_CTL_IPP_HYS_SCHIMDT                  (1 << 4)
 352 #define SW_PAD_CTL_IPP_ODE_CMOS                     (0 << 3)
 353 #define SW_PAD_CTL_IPP_ODE_OPEN                     (1 << 3)
 354 #define SW_PAD_CTL_IPP_DSE_STD                      (0 << 1)
 355 #define SW_PAD_CTL_IPP_DSE_HIGH                     (1 << 1)
 356 #define SW_PAD_CTL_IPP_DSE_MAX                      (2 << 1)
 357 #if 0 /* Same as 2 */
 358 #define SW_PAD_CTL_IPP_DSE_MAX                      (3 << 1)
 359 #endif
 360 #define SW_PAD_CTL_IPP_SRE_SLOW                     (0 << 0)
 361 #define SW_PAD_CTL_IPP_SRE_FAST                     (1 << 0)
 362
 363 /* Shift above flags into one of the three fields in each register */
 364 #define SW_PAD_CTL_FLD_0(x)                         ((x) << 0)
 365 #define SW_PAD_CTL_FLD_1(x)                         ((x) << 10)
 366 #define SW_PAD_CTL_FLD_2(x)                         ((x) << 20)
 367
 368 /* IPU */
 369 #define IPU_CONF                (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
 370 #define IPU_CHA_BUF0_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
 371 #define IPU_CHA_BUF1_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
 372 #define IPU_CHA_DB_MODE_SEL     (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
 373 #define IPU_CHA_CUR_BUF         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
 374 #define IPU_FS_PROC_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
 375 #define IPU_FS_DISP_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
 376 #define IPU_TASKS_STAT          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
 377 #define IPU_IMA_ADDR            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
 378 #define IPU_IMA_DATA            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
 379 #define IPU_INT_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
 380 #define IPU_INT_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
 381 #define IPU_INT_CTRL_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
 382 #define IPU_INT_CTRL_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
 383 #define IPU_INT_CTRL_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
 384 #define IPU_INT_STAT_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
 385 #define IPU_INT_STAT_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
 386 #define IPU_INT_STAT_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
 387 #define IPU_INT_STAT_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
 388 #define IPU_INT_STAT_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
 389 #define IPU_BRK_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
 390 #define IPU_BRK_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
 391 #define IPU_BRK_STAT            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
 392 #define IPU_DIAGB_CTRL          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
 393
 394
 395 /* ATA */
 396 #define ATA_TIME_OFF            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
 397 #define ATA_TIME_ON             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
 398 #define ATA_TIME_1              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
 399 #define ATA_TIME_2W             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
 400     /* PIO */
 401 #define ATA_TIME_2R             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
 402 #define ATA_TIME_AX             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
 403 #define ATA_TIME_4              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
 404 #define ATA_TIME_9              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
 405     /* MDMA */
 406 #define ATA_TIME_M              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
 407 #define ATA_TIME_JN             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
 408 #define ATA_TIME_D              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
 409 #define ATA_TIME_K              (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
 410     /* UDMA */
 411 #define ATA_TIME_ACK            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
 412 #define ATA_TIME_ENV            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
 413 #define ATA_TIME_PIO_RDX        (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
 414 #define ATA_TIME_ZAH            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
 415 #define ATA_TIME_MLIX           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
 416 #define ATA_TIME_DVH            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
 417 #define ATA_TIME_DZFS           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
 418 #define ATA_TIME_DVS            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
 419 #define ATA_TIME_CVS            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
 420 #define ATA_TIME_SS             (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
 421 #define ATA_TIME_CYC            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
 422     /* */
 423 #define ATA_FIFO_DATA_32        (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
 424 #define ATA_FIFO_DATA_16        (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
 425 #define ATA_FIFO_FILL           (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
 426     /* Actually ATA_CONTROL but conflicts arise */
 427 #define ATA_INTF_CONTROL        (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
 428 #define ATA_INTERRUPT_PENDING   (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
 429 #define ATA_INTERRUPT_ENABLE    (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
 430 #define ATA_INTERRUPT_CLEAR     (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
 431 #define ATA_FIFO_ALARM          (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
 432 #define ATA_DRIVE_DATA          (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
 433 #define ATA_DRIVE_FEATURES      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
 434 #define ATA_DRIVE_SECTOR_COUNT  (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
 435 #define ATA_DRIVE_SECTOR_NUM    (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
 436 #define ATA_DRIVE_CYL_LOW       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
 437 #define ATA_DRIVE_CYL_HIGH      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
 438 #define ATA_DRIVE_CYL_HEAD      (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
 439 #define ATA_DRIVE_STATUS        (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
 440 #define ATA_DRIVE_COMMAND       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
 441 #define ATA_ALT_DRIVE_STATUS    (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
 442 #define ATA_DRIVE_CONTROL       (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
 443
 444 /* ATA_INTF_CONTROL flags */
 445 #define ATA_FIFO_RST            (1 << 7)
 446 #define ATA_ATA_RST             (1 << 6)
 447 #define ATA_FIFO_TX_EN          (1 << 5)
 448 #define ATA_FIFO_RCV_EN         (1 << 4)
 449 #define ATA_DMA_PENDING         (1 << 3)
 450 #define ATA_DMA_ULTRA_SELECTED  (1 << 2)
 451 #define ATA_DMA_WRITE           (1 << 1)
 452 #define ATA_IORDY_EN            (1 << 0)
 453
 454 /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
 455 #define ATA_INTRQ1              (1 << 7)
 456 #define ATA_FIFO_UNDERFLOW      (1 << 6)
 457 #define ATA_FIFO_OVERFLOW       (1 << 5)
 458 #define ATA_CONTROLLER_IDLE     (1 << 4)
 459 #define ATA_INTRQ2              (1 << 3)
 460
 461 /* EPIT */
 462 #define EPITCR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
 463 #define EPITSR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
 464 #define EPITLR1                 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
 465 #define EPITCMPR1               (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
 466 #define EPITCNT1                (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
 467
 468 #define EPITCR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
 469 #define EPITSR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
 470 #define EPITLR2                 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
 471 #define EPITCMPR2               (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
 472 #define EPITCNT2                (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
 473
 474 #define EPITCR_CLKSRC_OFF               (0 << 24)
 475 #define EPITCR_CLKSRC_IPG_CLK           (1 << 24)
 476 #define EPITCR_CLKSRC_IPG_CLK_HIGHFREQ  (2 << 24)
 477 #define EPITCR_CLKSRC_IPG_CLK_32K       (3 << 24)
 478 #define EPITCR_OM_DISCONNECTED          (0 << 22)
 479 #define EPITCR_OM_TOGGLE                (1 << 22)
 480 #define EPITCR_OM_CLEAR                 (2 << 22)
 481 #define EPITCR_OM_SET                   (3 << 22)
 482 #define EPITCR_STOPEN                   (1 << 21)
 483 #define EPITCR_DOZEN                    (1 << 20)
 484 #define EPITCR_WAITEN                   (1 << 19)
 485 #define EPITCR_DBGEN                    (1 << 18)
 486 #define EPITCR_IOVW                     (1 << 17)
 487 #define EPITCR_SWR                      (1 << 16)
 488 #define EPITCR_PRESCALER(n)             ((n) << 4) /* Divide by n+1 */
 489 #define EPITCR_RLD                      (1 << 3)
 490 #define EPITCR_OCIEN                    (1 << 2)
 491 #define EPITCR_ENMOD                    (1 << 1)
 492 #define EPITCR_EN                       (1 << 0)
 493
 494 #define EPITSR_OCIF                     (1 << 0)
 495
 496 /* GPIO */
 497 #define GPIO_DR_I               0x00 /* Offset - 0x00 */
 498 #define GPIO_GDIR_I             0x01 /* Offset - 0x04 */
 499 #define GPIO_PSR_I              0x02 /* Offset - 0x08 */
 500 #define GPIO_ICR1_I             0x03 /* Offset - 0x0C */
 501 #define GPIO_ICR2_I             0x04 /* Offset - 0x10 */
 502 #define GPIO_IMR_I              0x05 /* Offset - 0x14 */
 503 #define GPIO_ISR_I              0x06 /* Offset - 0x18 */
 504
 505 #define GPIO1_DR                (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_DR_I])
 506 #define GPIO1_GDIR              (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_GDIR_I])
 507 #define GPIO1_PSR               (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_PSR_I])
 508 #define GPIO1_ICR1              (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ICR1_I])
 509 #define GPIO1_ICR2              (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ICR2_I])
 510 #define GPIO1_IMR               (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_IMR_I])
 511 #define GPIO1_ISR               (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ISR_I])
 512
 513 #define GPIO2_DR                (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_DR_I])
 514 #define GPIO2_GDIR              (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_GDIR_I])
 515 #define GPIO2_PSR               (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_PSR_I])
 516 #define GPIO2_ICR1              (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ICR1_I])
 517 #define GPIO2_ICR2              (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ICR2_I])
 518 #define GPIO2_IMR               (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_IMR_I])
 519 #define GPIO2_ISR               (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ISR_I])
 520
 521 #define GPIO3_DR                (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_DR_I])
 522 #define GPIO3_GDIR              (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_GDIR_I])
 523 #define GPIO3_PSR               (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_PSR_I])
 524 #define GPIO3_ICR1              (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ICR1_I])
 525 #define GPIO3_ICR2              (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ICR2_I])
 526 #define GPIO3_IMR               (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_IMR_I])
 527 #define GPIO3_ISR               (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ISR_I])
 528
 529 /* CSPI */
 530 #define CSPI_RXDATA_I           0x00 /* Offset - 0x00  */
 531 #define CSPI_TXDATA_I           0x01 /* Offset - 0x04  */
 532 #define CSPI_CONREG_I           0x02 /* Offset - 0x08  */
 533 #define CSPI_INTREG_I           0x03 /* Offset - 0x0C  */
 534 #define CSPI_DMAREG_I           0x04 /* Offset - 0x10  */
 535 #define CSPI_STATREG_I          0x05 /* Offset - 0x14  */
 536 #define CSPI_PERIODREG_I        0x06 /* Offset - 0x18  */
 537 #define CSPI_TESTREG_I          0x70 /* Offset - 0x1C0 */
 538
 539 #define CSPI_RXDATA1            (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_RXDATA_I])
 540 #define CSPI_TXDATA1            (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_TXDATA_I])
 541 #define CSPI_CONREG1            (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_CONREG_I])
 542 #define CSPI_INTREG1            (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_INTREG_I])
 543 #define CSPI_DMAREG1            (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_DMAREG_I])
 544 #define CSPI_STATREG1           (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_STATREG_I])
 545 #define CSPI_PERIODREG1         (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_PERIODREG_I])
 546 #define CSPI_TESTREG1           (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_TESTREG_I])
 547
 548 #define CSPI_RXDATA2            (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_RXDATA_I])
 549 #define CSPI_TXDATA2            (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_TXDATA_I])
 550 #define CSPI_CONREG2            (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_CONREG_I])
 551 #define CSPI_INTREG2            (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_INTREG_I])
 552 #define CSPI_DMAREG2            (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_DMAREG_I])
 553 #define CSPI_STATREG2           (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_STATREG_I])
 554 #define CSPI_PERIODREG2         (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_PERIODREG_I])
 555 #define CSPI_TESTREG2           (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_TESTREG_I])
 556
 557 #define CSPI_RXDATA3            (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_RXDATA_I])
 558 #define CSPI_TXDATA3            (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_TXDATA_I])
 559 #define CSPI_CONREG3            (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_CONREG_I])
 560 #define CSPI_INTREG3            (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_INTREG_I])
 561 #define CSPI_DMAREG3            (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_DMAREG_I])
 562 #define CSPI_STATREG3           (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_STATREG_I])
 563 #define CSPI_PERIODREG3         (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_PERIODREG_I])
 564 #define CSPI_TESTREG3           (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_TESTREG_I])
 565
 566 /* CSPI CONREG flags/fields */
 567 #define CSPI_CONREG_CHIP_SELECT_SS0     (0 << 24)
 568 #define CSPI_CONREG_CHIP_SELECT_SS1     (1 << 24)
 569 #define CSPI_CONREG_CHIP_SELECT_SS2     (2 << 24)
 570 #define CSPI_CONREG_CHIP_SELECT_SS3     (3 << 24)
 571 #define CSPI_CONREG_CHIP_SELECT_MASK    (3 << 24)
 572 #define CSPI_CONREG_DRCTL_DONT_CARE     (0 << 20)
 573 #define CSPI_CONREG_DRCTL_TRIG_FALLING  (1 << 20)
 574 #define CSPI_CONREG_DRCTL_TRIG_LOW      (2 << 20)
 575 #define CSPI_CONREG_DRCTL_TRIG_RSV      (3 << 20)
 576 #define CSPI_CONREG_DRCTL_MASK          (3 << 20)
 577 #define CSPI_CONREG_DATA_RATE_DIV_4     (0 << 16)
 578 #define CSPI_CONREG_DATA_RATE_DIV_8     (1 << 16)
 579 #define CSPI_CONREG_DATA_RATE_DIV_16    (2 << 16)
 580 #define CSPI_CONREG_DATA_RATE_DIV_32    (3 << 16)
 581 #define CSPI_CONREG_DATA_RATE_DIV_64    (4 << 16)
 582 #define CSPI_CONREG_DATA_RATE_DIV_128   (5 << 16)
 583 #define CSPI_CONREG_DATA_RATE_DIV_256   (6 << 16)
 584 #define CSPI_CONREG_DATA_RATE_DIV_512   (7 << 16)
 585 #define CSPI_CONREG_DATA_RATE_DIV_MASK  (7 << 16)
 586 #define CSPI_BITCOUNT(n)                ((n) << 8)
 587 #define CSPI_CONREG_SSPOL               (1 << 7)
 588 #define CSPI_CONREG_SSCTL               (1 << 6)
 589 #define CSPI_CONREG_PHA                 (1 << 6)
 590 #define CSPI_CONREG_POL                 (1 << 4)
 591 #define CSPI_CONREG_SMC                 (1 << 3)
 592 #define CSPI_CONREG_XCH                 (1 << 2)
 593 #define CSPI_CONREG_MODE                (1 << 1)
 594 #define CSPI_CONREG_EN                  (1 << 0)
 595
 596 /* CSPI INTREG flags */
 597 #define CSPI_INTREG_TCEN                (1 << 8)
 598 #define CSPI_INTREG_BOEN                (1 << 7)
 599 #define CSPI_INTREG_ROEN                (1 << 6)
 600 #define CSPI_INTREG_RFEN                (1 << 5)
 601 #define CSPI_INTREG_RHEN                (1 << 4)
 602 #define CSPI_INTREG_RREN                (1 << 3)
 603 #define CSPI_INTREG_TFEN                (1 << 2)
 604 #define CSPI_INTREG_THEN                (1 << 1)
 605 #define CSPI_INTREG_TEEN                (1 << 0)
 606
 607 /* CSPI DMAREG flags */
 608 #define CSPI_DMAREG_RFDEN               (1 << 5)
 609 #define CSPI_DMAREG_RHDEN               (1 << 4)
 610 #define CSPI_DMAREG_THDEN               (1 << 1)
 611 #define CSPI_DMAREG_TEDEN               (1 << 0)
 612
 613 /* CSPI STATREG flags */
 614 #define CSPI_STATREG_TC                 (1 << 8) /* w1c */
 615 #define CSPI_STATREG_BO                 (1 << 7) /* w1c */
 616 #define CSPI_STATREG_RO                 (1 << 6)
 617 #define CSPI_STATREG_RF                 (1 << 5)
 618 #define CSPI_STATREG_RH                 (1 << 4)
 619 #define CSPI_STATREG_RR                 (1 << 3)
 620 #define CSPI_STATREG_TF                 (1 << 2)
 621 #define CSPI_STATREG_TH                 (1 << 1)
 622 #define CSPI_STATREG_TE                 (1 << 0)
 623
 624 /* CSPI PERIODREG flags */
 625 #define CSPI_PERIODREG_CSRC             (1 << 15)
 626
 627 /* CSPI TESTREG flags */
 628 #define CSPI_TESTREG_SWAP               (1 << 15)
 629 #define CSPI_TESTREG_LBC                (1 << 14)
 630
 631 /* RTC */
 632 #define RTC_HOURMIN             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
 633 #define RTC_SECONDS             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
 634 #define RTC_ALRM_HM             (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
 635 #define RTC_ALRM_SEC            (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
 636 #define RTC_CTL                 (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
 637 #define RTC_ISR                 (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
 638 #define RTC_IENR                (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
 639 #define RTC_STPWCH              (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
 640 #define RTC_DAYR                (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
 641 #define RTC_DAYALARM            (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
 642
 643 /* Keypad */
 644 #define KPP_KPCR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
 645 #define KPP_KPSR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
 646 #define KPP_KDDR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
 647 #define KPP_KPDR                (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
 648
 649 /* KPP_KPSR bits */
 650 #define KPP_KPSR_KRIE           (1 << 9)
 651 #define KPP_KPSR_KDIE           (1 << 8)
 652 #define KPP_KPSR_KRSS           (1 << 3)
 653 #define KPP_KPSR_KDSC           (1 << 2)
 654 #define KPP_KPSR_KPKR           (1 << 1)
 655 #define KPP_KPSR_KPKD           (1 << 0)
 656
 657 /* ROMPATCH and AVIC */
 658 #define ROMPATCH_BASE_ADDR      0x60000000
 659
 660 /* Since AVIC vector registers are NOT used, we reserve some for various
 661  * purposes. Copied from Linux source code. */
 662 #define CHIP_REV_1_0            0x10
 663 #define CHIP_REV_2_0            0x20
 664 #define SYSTEM_REV_ID_REG       (AVIC_BASE_ADDR + AVIC_VEC_1)
 665 #define SYSTEM_REV_ID_MAG       0xF00C
 666
 667 /*
 668  * NAND, SDRAM, WEIM, M3IF, EMI controllers
 669  */
 670 #define EXT_MEM_CTRL_BASE       0xB8000000
 671 #define NFC_BASE                EXT_MEM_CTRL_BASE
 672 #define ESDCTL_BASE             0xB8001000
 673 #define WEIM_BASE_ADDR          0xB8002000
 674 #define WEIM_CTRL_CS0           (WEIM_BASE_ADDR+0x00)
 675 #define WEIM_CTRL_CS1           (WEIM_BASE_ADDR+0x10)
 676 #define WEIM_CTRL_CS2           (WEIM_BASE_ADDR+0x20)
 677 #define WEIM_CTRL_CS3           (WEIM_BASE_ADDR+0x30)
 678 #define WEIM_CTRL_CS4           (WEIM_BASE_ADDR+0x40)
 679 #define M3IF_BASE               0xB8003000
 680 #define PCMCIA_CTL_BASE         0xB8004000
 681
 682 /*
 683  * Memory regions and CS
 684  */
 685 #define IPU_MEM_BASE_ADDR       0x70000000
 686 #define CSD0_BASE_ADDR          0x80000000
 687 #define CSD1_BASE_ADDR          0x90000000
 688 #define CS0_BASE_ADDR           0xA0000000
 689 #define CS1_BASE_ADDR           0xA8000000
 690 #define CS2_BASE_ADDR           0xB0000000
 691 #define CS3_BASE_ADDR           0xB2000000
 692 #define CS4_BASE_ADDR           0xB4000000
 693 #define CS4_BASE_PSRAM          0xB5000000
 694 #define CS5_BASE_ADDR           0xB6000000
 695 #define PCMCIA_MEM_BASE_ADDR    0xC0000000
 696
 697 #define INTERNAL_ROM_VA         0xF0000000
 698
 699 /*
 700  * SDRAM
 701  */
 702 #define RAM_BANK0_BASE          SDRAM_BASE_ADDR
 703
 704 /*
 705  * IRQ Controller Register Definitions.
 706  */
 707 #define AVIC_BASE_ADDR         0x68000000
 708 #define INTCNTL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
 709 #define NIMASK                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
 710 #define INTENNUM               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
 711 #define INTDISNUM              (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
 712 #define INTENABLEH             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
 713 #define INTENABLEL             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
 714 #define INTTYPEH               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
 715 #define INTTYPEL               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
 716 #define NIPRIORITY(n)          (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
 717 #define NIPRIORITY7            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
 718 #define NIPRIORITY6            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
 719 #define NIPRIORITY5            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
 720 #define NIPRIORITY4            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
 721 #define NIPRIORITY3            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
 722 #define NIPRIORITY2            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
 723 #define NIPRIORITY1            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
 724 #define NIPRIORITY0            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
 725 #define NIVECSR                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
 726 #define FIVECSR                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
 727 #define INTSRCH                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
 728 #define INTSRCL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
 729 #define INTFRCH                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
 730 #define INTFRCL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
 731 #define NIPNDH                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
 732 #define NIPNDL                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
 733 #define FIPNDH                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
 734 #define FIPNDL                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
 735 #define VECTOR_BASE_ADDR       (AVIC_BASE_ADDR+0x100)
 736 #define VECTOR(n)              (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
 737
 738 /* The vectors go all the way up to 63. 4 bytes for each */
 739 #define INTCNTL_ABFLAG         (1 << 25)
 740 #define INTCNTL_ABFEN          (1 << 24)
 741 #define INTCNTL_NIDIS          (1 << 22)
 742 #define INTCNTL_FIDIS          (1 << 21)
 743 #define INTCNTL_NIAD           (1 << 20)
 744 #define INTCNTL_FIAD           (1 << 19)
 745 #define INTCNTL_NM             (1 << 18)
 746
 747 /* L210 */
 748 #define L2CC_BASE_ADDR                  0x30000000
 749 #define L2_CACHE_LINE_SIZE              32
 750 #define L2_CACHE_CTL_REG                0x100
 751 #define L2_CACHE_AUX_CTL_REG            0x104
 752 #define L2_CACHE_SYNC_REG               0x730
 753 #define L2_CACHE_INV_LINE_REG           0x770
 754 #define L2_CACHE_INV_WAY_REG            0x77C
 755 #define L2_CACHE_CLEAN_LINE_REG         0x7B0
 756 #define L2_CACHE_CLEAN_INV_LINE_REG     0x7F0
 757
 758 #define L2CC_CACHE_SYNC                 (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
 759
 760 /* CCM */
 761 #define CLKCTL_CCMR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
 762 #define CLKCTL_PDR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
 763 #define CLKCTL_PDR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
 764 #define CLKCTL_RCSR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
 765 #define CLKCTL_MPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
 766 #define CLKCTL_UPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
 767 #define CLKCTL_SPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
 768 #define CLKCTL_COSR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
 769 #define CLKCTL_CGR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
 770 #define CLKCTL_CGR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
 771 #define CLKCTL_CGR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
 772 #define CLKCTL_WIMR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
 773 #define CLKCTL_LDC                      (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
 774 #define CLKCTL_DCVR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
 775 #define CLKCTL_DCVR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
 776 #define CLKCTL_DCVR2                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
 777 #define CLKCTL_DCVR3                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
 778 #define CLKCTL_LTR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
 779 #define CLKCTL_LTR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
 780 #define CLKCTL_LTR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
 781 #define CLKCTL_LTR3                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
 782 #define CLKCTL_LTBR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
 783 #define CLKCTL_LTBR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
 784 #define CLKCTL_PMCR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
 785 #define CLKCTL_PMCR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
 786 #define CLKCTL_PDR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
 787
 788 #define CGR0_SD_MMC1(cg)                ((cg) << 0*2)
 789 #define CGR0_SD_MMC2(cg)                ((cg) << 1*2)
 790 #define CGR0_GPT(cg)                    ((cg) << 2*2)
 791 #define CGR0_EPIT1(cg)                  ((cg) << 3*2)
 792 #define CGR0_EPIT2(cg)                  ((cg) << 4*2)
 793 #define CGR0_IIM(cg)                    ((cg) << 5*2)
 794 #define CGR0_ATA(cg)                    ((cg) << 6*2)
 795 #define CGR0_SDMA(cg)                   ((cg) << 7*2)
 796 #define CGR0_CSPI3(cg)                  ((cg) << 8*2)
 797 #define CGR0_RNG(cg)                    ((cg) << 9*2)
 798 #define CGR0_UART1(cg)                  ((cg) << 10*2)
 799 #define CGR0_UART2(cg)                  ((cg) << 11*2)
 800 #define CGR0_SSI1(cg)                   ((cg) << 12*2)
 801 #define CGR0_I2C1(cg)                   ((cg) << 13*2)
 802 #define CGR0_I2C2(cg)                   ((cg) << 14*2)
 803 #define CGR0_I2C3(cg)                   ((cg) << 15*2)
 804
 805 #define CGR1_HANTRO(cg)                 ((cg) << 0*2)
 806 #define CGR1_MEMSTICK1(cg)              ((cg) << 1*2)
 807 #define CGR1_MEMSTICK2(cg)              ((cg) << 2*2)
 808 #define CGR1_CSI(cg)                    ((cg) << 3*2)
 809 #define CGR1_RTC(cg)                    ((cg) << 4*2)
 810 #define CGR1_WDOG(cg)                   ((cg) << 5*2)
 811 #define CGR1_PWM(cg)                    ((cg) << 6*2)
 812 #define CGR1_SIM(cg)                    ((cg) << 7*2)
 813 #define CGR1_ECT(cg)                    ((cg) << 8*2)
 814 #define CGR1_USBOTG(cg)                 ((cg) << 9*2)
 815 #define CGR1_KPP(cg)                    ((cg) << 10*2)
 816 #define CGR1_IPU(cg)                    ((cg) << 11*2)
 817 #define CGR1_UART3(cg)                  ((cg) << 12*2)
 818 #define CGR1_UART4(cg)                  ((cg) << 13*2)
 819 #define CGR1_UART5(cg)                  ((cg) << 14*2)
 820 #define CGR1_1_WIRE(cg)                 ((cg) << 15*2)
 821
 822 #define CGR2_SSI2(cg)                   ((cg) << 0*2)
 823 #define CGR2_CSPI1(cg)                  ((cg) << 1*2)
 824 #define CGR2_CSPI2(cg)                  ((cg) << 2*2)
 825 #define CGR2_GACC(cg)                   ((cg) << 3*2)
 826 #define CGR2_EMI(cg)                    ((cg) << 4*2)
 827 #define CGR2_RTIC(cg)                   ((cg) << 5*2)
 828 #define CGR2_FIR(cg)                    ((cg) << 6*2)
 829
 830 #define WIM_GPIO3                       (1 << 0)
 831 #define WIM_GPIO2                       (1 << 1)
 832 #define WIM_GPIO1                       (1 << 2)
 833 #define WIM_PCMCIA                      (1 << 3)
 834 #define WIM_WDT                         (1 << 4)
 835 #define WIM_USB_OTG                     (1 << 5)
 836 #define WIM_IPI_INT_UH2                 (1 << 6)
 837 #define WIM_IPI_INT_UH1                 (1 << 7)
 838 #define WIM_IPI_INT_UART5_ANDED         (1 << 8)
 839 #define WIM_IPI_INT_UART4_ANDED         (1 << 9)
 840 #define WIM_IPI_INT_UART3_ANDED         (1 << 10)
 841 #define WIM_IPI_INT_UART2_ANDED         (1 << 11)
 842 #define WIM_IPI_INT_UART1_ANDED         (1 << 12)
 843 #define WIM_IPI_INT_SIM_DATA_IRQ        (1 << 13)
 844 #define WIM_IPI_INT_SDHC2               (1 << 14)
 845 #define WIM_IPI_INT_SDHC1               (1 << 15)
 846 #define WIM_IPI_INT_RTC                 (1 << 16)
 847 #define WIM_IPI_INT_PWM                 (1 << 17)
 848 #define WIM_IPI_INT_KPP                 (1 << 18)
 849 #define WIM_IPI_INT_IIM                 (1 << 19)
 850 #define WIM_IPI_INT_GPT                 (1 << 20)
 851 #define WIM_IPI_INT_FIR                 (1 << 21)
 852 #define WIM_IPI_INT_EPIT2               (1 << 22)
 853 #define WIM_IPI_INT_EPIT1               (1 << 23)
 854 #define WIM_IPI_INT_CSPI2               (1 << 24)
 855 #define WIM_IPI_INT_CSPI1               (1 << 25)
 856 #define WIM_IPI_INT_POWER_FAIL          (1 << 26)
 857 #define WIM_IPI_INT_CSPI3               (1 << 27)
 858 #define WIM_RESERVED28                  (1 << 28)
 859 #define WIM_RESERVED29                  (1 << 29)
 860 #define WIM_RESERVED30                  (1 << 30)
 861 #define WIM_RESERVED31                  (1 << 31)
 862
 863 /* WEIM - CS0 */
 864 #define CSCRU                           0x00
 865 #define CSCRL                           0x04
 866 #define CSCRA                           0x08
 867
 868 /* ESDCTL */
 869 #define ESDCTL_ESDCTL0                  0x00
 870 #define ESDCTL_ESDCFG0                  0x04
 871 #define ESDCTL_ESDCTL1                  0x08
 872 #define ESDCTL_ESDCFG1                  0x0C
 873 #define ESDCTL_ESDMISC                  0x10
 874
 875 /* More UART 1 Register defines */
 876 #define URXD1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
 877 #define UTXD1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
 878 #define UCR1_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
 879 #define UCR2_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
 880 #define UCR3_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
 881 #define UCR4_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
 882 #define UFCR1                           (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
 883 #define USR1_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
 884 #define USR2_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
 885 #define UTS1                            (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
 886
 887 /*
 888  * UART Control Register 0 Bit Fields.
 889  */
 890 #define EUARTUCR1_ADEN      (1 << 15)   // Auto detect interrupt
 891 #define EUARTUCR1_ADBR      (1 << 14)   // Auto detect baud rate
 892 #define EUARTUCR1_TRDYEN    (1 << 13)   // Transmitter ready interrupt enable
 893 #define EUARTUCR1_IDEN      (1 << 12)   // Idle condition interrupt
 894 #define EUARTUCR1_RRDYEN    (1 << 9)    // Recv ready interrupt enable
 895 #define EUARTUCR1_RDMAEN    (1 << 8)    // Recv ready DMA enable
 896 #define EUARTUCR1_IREN      (1 << 7)    // Infrared interface enable
 897 #define EUARTUCR1_TXMPTYEN  (1 << 6)    // Transimitter empt  interrupt enable
 898 #define EUARTUCR1_RTSDEN    (1 << 5)    // RTS delta interrupt enable
 899 #define EUARTUCR1_SNDBRK    (1 << 4)    // Send break
 900 #define EUARTUCR1_TDMAEN    (1 << 3)    // Transmitter ready DMA enable
 901 #define EUARTUCR1_DOZE      (1 << 1)    // Doze
 902 #define EUARTUCR1_UARTEN    (1 << 0)    // UART enabled
 903 #define EUARTUCR2_ESCI      (1 << 15)   // Escape seq interrupt enable
 904 #define EUARTUCR2_IRTS      (1 << 14)   // Ignore RTS pin
 905 #define EUARTUCR2_CTSC      (1 << 13)   // CTS pin control
 906 #define EUARTUCR2_CTS       (1 << 12)   // Clear to send
 907 #define EUARTUCR2_ESCEN     (1 << 11)   // Escape enable
 908 #define EUARTUCR2_PREN      (1 << 8)    // Parity enable
 909 #define EUARTUCR2_PROE      (1 << 7)    // Parity odd/even
 910 #define EUARTUCR2_STPB      (1 << 6)    // Stop
 911 #define EUARTUCR2_WS        (1 << 5)    // Word size
 912 #define EUARTUCR2_RTSEN     (1 << 4)    // Request to send interrupt enable
 913 #define EUARTUCR2_ATEN      (1 << 3)    // Aging timer enable
 914 #define EUARTUCR2_TXEN      (1 << 2)    // Transmitter enabled
 915 #define EUARTUCR2_RXEN      (1 << 1)    // Receiver enabled
 916 #define EUARTUCR2_SRST_     (1 << 0)    // SW reset
 917 #define EUARTUCR3_PARERREN  (1 << 12)   // Parity enable
 918 #define EUARTUCR3_FRAERREN  (1 << 11)   // Frame error interrupt enable
 919 #define EUARTUCR3_ADNIMP    (1 << 7)    // Autobaud detection not improved
 920 #define EUARTUCR3_RXDSEN    (1 << 6)    // Receive status interrupt  enable
 921 #define EUARTUCR3_AIRINTEN  (1 << 5)    // Async IR wake interrupt enable
 922 #define EUARTUCR3_AWAKEN    (1 << 4)    // Async wake interrupt enable
 923 #define EUARTUCR3_RXDMUXSEL (1 << 2)    // RXD muxed input selected
 924 #define EUARTUCR3_INVT      (1 << 1)    // Inverted Infrared transmission
 925 #define EUARTUCR3_ACIEN     (1 << 0)    // Autobaud counter interrupt  enable
 926 #define EUARTUCR4_CTSTL_32  (32 << 10)  // CTS trigger level (32 chars)
 927 #define EUARTUCR4_INVR      (1 << 9)    // Inverted infrared reception
 928 #define EUARTUCR4_ENIRI     (1 << 8)    // Serial infrared interrupt enable
 929 #define EUARTUCR4_WKEN      (1 << 7)    // Wake interrupt enable
 930 #define EUARTUCR4_IRSC      (1 << 5)    // IR special case
 931 #define EUARTUCR4_LPBYP     (1 << 4)    // Low power bypass
 932 #define EUARTUCR4_TCEN      (1 << 3)    // Transmit complete interrupt  enable
 933 #define EUARTUCR4_BKEN      (1 << 2)    // Break condition interrupt enable
 934 #define EUARTUCR4_OREN      (1 << 1)    // Receiver overrun interrupt enable
 935 #define EUARTUCR4_DREN      (1 << 0)    // Recv data ready interrupt enable
 936 #define EUARTUFCR_RXTL_SHF  0           // Receiver trigger level shift
 937 #define EUARTUFCR_RFDIV_1   (5 << 7)    // Reference freq divider (div> 1)
 938 #define EUARTUFCR_RFDIV_2   (4 << 7)    // Reference freq divider (div> 2)
 939 #define EUARTUFCR_RFDIV_3   (3 << 7)    // Reference freq  divider (div 3)
 940 #define EUARTUFCR_RFDIV_4   (2 << 7)    // Reference freq divider (div 4)
 941 #define EUARTUFCR_RFDIV_5   (1 << 7)    // Reference freq divider (div 5)
 942 #define EUARTUFCR_RFDIV_6   (0 << 7)    // Reference freq divider (div 6)
 943 #define EUARTUFCR_RFDIV_7   (6 << 7)    // Reference freq divider (div 7)
 944 #define EUARTUFCR_TXTL_SHF  10          // Transmitter trigger level shift
 945 #define EUARTUSR1_PARITYERR (1 << 15)   // Parity error interrupt flag
 946 #define EUARTUSR1_RTSS      (1 << 14)   // RTS pin status
 947 #define EUARTUSR1_TRDY      (1 << 13)   // Transmitter ready interrupt/dma flag
 948 #define EUARTUSR1_RTSD      (1 << 12)   // RTS delta
 949 #define EUARTUSR1_ESCF      (1 << 11)   // Escape seq interrupt flag
 950 #define EUARTUSR1_FRAMERR   (1 << 10)   // Frame error interrupt flag
 951 #define EUARTUSR1_RRDY      (1 << 9)    // Receiver ready  interrupt/dma flag
 952 #define EUARTUSR1_AGTIM     (1 << 8)    // Aging timeout interrupt status
 953 #define EUARTUSR1_RXDS      (1 << 6)    // Receiver idle interrupt flag
 954 #define EUARTUSR1_AIRINT    (1 << 5)    // Async IR wake interrupt flag
 955 #define EUARTUSR1_AWAKE     (1 << 4)    // Aysnc wake interrupt flag
 956 #define EUARTUSR2_ADET      (1 << 15)   // Auto baud rate detect  complete
 957 #define EUARTUSR2_TXFE      (1 << 14)   // Transmit buffer FIFO empty
 958 #define EUARTUSR2_IDLE      (1 << 12)   // Idle condition
 959 #define EUARTUSR2_ACST      (1 << 11)   // Autobaud counter stopped
 960 #define EUARTUSR2_IRINT     (1 << 8)    // Serial infrared interrupt flag
 961 #define EUARTUSR2_WAKE      (1 << 7)    // Wake
 962 #define EUARTUSR2_RTSF      (1 << 4)    // RTS edge interrupt flag
 963 #define EUARTUSR2_TXDC      (1 << 3)    // Transmitter complete
 964 #define EUARTUSR2_BRCD      (1 << 2)    // Break condition
 965 #define EUARTUSR2_ORE       (1 << 1)    // Overrun error
 966 #define EUARTUSR2_RDR       (1 << 0)    // Recv data ready
 967 #define EUARTUTS_FRCPERR    (1 << 13)   // Force parity error
 968 #define EUARTUTS_LOOP       (1 << 12)   // Loop tx and rx
 969 #define EUARTUTS_TXEMPTY    (1 << 6)    // TxFIFO empty
 970 #define EUARTUTS_RXEMPTY    (1 << 5)    // RxFIFO empty
 971 #define EUARTUTS_TXFULL     (1 << 4)    // TxFIFO full
 972 #define EUARTUTS_RXFULL     (1 << 3)    // RxFIFO full
 973 #define EUARTUTS_SOFTRST    (1 << 0)    // Software reset
 974
 975 #define L2CC_ENABLED
 976
 977 /* Assuming 26MHz input clock */
 978 /*                         PD          MFD           MFI          MFN */
 979 #define MPCTL_PARAM_208  ((1 << 26) + (0   << 16) + (8  << 10) + (0 << 0))
 980 #define MPCTL_PARAM_399  ((0 << 26) + (51  << 16) + (7  << 10) + (35 << 0))
 981 #define MPCTL_PARAM_532  ((0 << 26) + (51  << 16) + (10 << 10) + (12 << 0))
 982
 983 /* UPCTL                   PD             MFD              MFI          MFN */
 984 #define UPCTL_PARAM_288  (((1-1) << 26) + ((13-1) << 16) + (5  << 10) + (7  << 0))
 985 #define UPCTL_PARAM_240  (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
 986
 987 /* PDR0 */
 988 #define PDR0_208_104_52     0xFF870D48  /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
 989 #define PDR0_399_66_66      0xFF872B28  /* ARM=399MHz, HCLK=IPG=66.5MHz */
 990 #define PDR0_399_133_66     0xFF871650  /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
 991 #define PDR0_532_133_66     0xFF871E58  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
 992 #define PDR0_665_83_66      0xFF873D78  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
 993 #define PDR0_665_133_66     0xFF872660  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
 994
 995 #define PBC_BASE            CS4_BASE_ADDR    /* Peripheral Bus Controller */
 996
 997 #define PBC_BSTAT2                  0x2
 998 #define PBC_BCTRL1                  0x4
 999 #define PBC_BCTRL1_CLR              0x6
1000 #define PBC_BCTRL2                  0x8
1001 #define PBC_BCTRL2_CLR              0xA
1002 #define PBC_BCTRL3                  0xC
1003 #define PBC_BCTRL3_CLR              0xE
1004 #define PBC_BCTRL4                  0x10
1005 #define PBC_BCTRL4_CLR              0x12
1006 #define PBC_BSTAT1                  0x14
1007 #define MX31EVB_CS_LAN_BASE         (CS4_BASE_ADDR + 0x00020000 +  0x300)
1008 #define MX31EVB_CS_UART_BASE        (CS4_BASE_ADDR + 0x00010000)
1009
1010 #define REDBOOT_IMAGE_SIZE              0x40000
1011
1012 #define SDRAM_WORKAROUND_FULL_PAGE
1013
1014 #define ARMHIPG_208_52_52         /* ARM: 208MHz, HCLK=IPG=52MHz*/
1015 #define ARMHIPG_52_52_52          /* ARM: 52MHz, HCLK=IPG=52MHz*/
1016 #define ARMHIPG_399_66_66
1017 #define ARMHIPG_399_133_66
1018
1019 /* MX31 EVB SDRAM is from 0x80000000, 64M */
1020 #define SDRAM_BASE_ADDR                 CSD0_BASE_ADDR
1021 #define SDRAM_SIZE                      0x04000000
1022
1023 #define UART_WIDTH_32         /* internal UART is 32bit access only */
1024 #define EXT_UART_x16
1025
1026 #define UART_WIDTH_32         /* internal UART is 32bit access only */
1027
1028 #define FLASH_BURST_MODE_ENABLE 1
1029 #define SDRAM_COMPARE_CONST1    0x55555555
1030 #define SDRAM_COMPARE_CONST2    0xAAAAAAAA
1031 #define UART_FIFO_CTRL          0x881
1032 #define TIMEOUT                 1000
1033 #define writel(v,a)             (*(REG32_PTR_T)(a) = (v))
1034 #define readl(a)                (*(REG32_PTR_T)(a))
1035 #define writew(v,a)             (*(REG16_PTR_T)(a) = (v))
1036 #define readw(a)                (*(REG16_PTR_T)(a))
1037
1038 #define USB_BASE                OTG_BASE_ADDR
1039
1040 #endif /* __IMX31L_H__ */