FS#8961 - Anti-Aliased Fonts.
[kugel-rb.git] / firmware / export / imx31l.h
blobdea5588e59e4b5f2dca034e90d4b224829246819
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2006 by James Espinoza
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
21 #ifndef __IMX31L_H__
22 #define __IMX31L_H__
24 /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
26 #define REG8_PTR_T volatile unsigned char *
27 #define REG16_PTR_T volatile unsigned short *
28 #define REG32_PTR_T volatile unsigned long *
30 /* Place in the section with the framebuffer */
31 #define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEM*0x100000) - TTB_SIZE)
32 #define TTB_SIZE (0x4000)
33 #define IRAM_SIZE (0x4000)
34 #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
35 #define FRAME_SIZE (240*320*2)
36 /* Rockbox framebuffer address, not retail OS */
37 #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
38 #define FRAME ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR))
40 #define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon))
41 /* USBOTG */
42 #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
43 #define USB_NUM_ENDPOINTS 8
44 #define USB_DEVBSS_ATTR DEVBSS_ATTR
45 #define USB_BASE OTG_BASE_ADDR
48 * AIPS 1
50 #define IRAM_BASE_ADDR 0x1fffc000
51 #define L2CC_BASE_ADDR 0x30000000
52 #define AIPS1_BASE_ADDR 0x43F00000
53 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
54 #define MAX_BASE_ADDR 0x43F04000
55 #define EVTMON_BASE_ADDR 0x43F08000
56 #define CLKCTL_BASE_ADDR 0x43F0C000
57 #define ETB_SLOT4_BASE_ADDR 0x43F10000
58 #define ETB_SLOT5_BASE_ADDR 0x43F14000
59 #define ECT_CTIO_BASE_ADDR 0x43F18000
60 #define I2C1_BASE_ADDR 0x43F80000
61 #define I2C3_BASE_ADDR 0x43F84000
62 #define OTG_BASE_ADDR 0x43F88000
63 #define ATA_BASE_ADDR 0x43F8C000
64 #define UART1_BASE_ADDR 0x43F90000
65 #define UART2_BASE_ADDR 0x43F94000
66 #define I2C2_BASE_ADDR 0x43F98000
67 #define OWIRE_BASE_ADDR 0x43F9C000
68 #define SSI1_BASE_ADDR 0x43FA0000
69 #define CSPI1_BASE_ADDR 0x43FA4000
70 #define KPP_BASE_ADDR 0x43FA8000
71 #define IOMUXC_BASE_ADDR 0x43FAC000
72 #define UART4_BASE_ADDR 0x43FB0000
73 #define UART5_BASE_ADDR 0x43FB4000
74 #define ECT_IP1_BASE_ADDR 0x43FB8000
75 #define ECT_IP2_BASE_ADDR 0x43FBC000
78 * SPBA
80 #define SPBA_BASE_ADDR 0x50000000
81 #define MMC_SDHC1_BASE_ADDR 0x50004000
82 #define MMC_SDHC2_BASE_ADDR 0x50008000
83 #define UART3_BASE_ADDR 0x5000C000
84 #define CSPI2_BASE_ADDR 0x50010000
85 #define SSI2_BASE_ADDR 0x50014000
86 #define SIM_BASE_ADDR 0x50018000
87 #define IIM_BASE_ADDR 0x5001C000
88 #define ATA_DMA_BASE_ADDR 0x50020000
89 #define SPBA_CTRL_BASE_ADDR 0x5003C000
92 * AIPS 2
94 #define AIPS2_BASE_ADDR 0x53F00000
95 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
96 #define CCM_BASE_ADDR 0x53F80000
97 #define CSPI3_BASE_ADDR 0x53F84000
98 #define FIRI_BASE_ADDR 0x53F8C000
99 #define GPT1_BASE_ADDR 0x53F90000
100 #define EPIT1_BASE_ADDR 0x53F94000
101 #define EPIT2_BASE_ADDR 0x53F98000
102 #define GPIO3_BASE_ADDR 0x53FA4000
103 #define SCC_BASE 0x53FAC000
104 #define SCM_BASE 0x53FAE000
105 #define SMN_BASE 0x53FAF000
106 #define RNGA_BASE_ADDR 0x53FB0000
107 #define IPU_CTRL_BASE_ADDR 0x53FC0000
108 #define AUDMUX_BASE 0x53FC4000
109 #define MPEG4_ENC_BASE 0x53FC8000
110 #define GPIO1_BASE_ADDR 0x53FCC000
111 #define GPIO2_BASE_ADDR 0x53FD0000
112 #define SDMA_BASE_ADDR 0x53FD4000
113 #define RTC_BASE_ADDR 0x53FD8000
114 #define WDOG_BASE_ADDR 0x53FDC000
115 #define PWM_BASE_ADDR 0x53FE0000
116 #define RTIC_BASE_ADDR 0x53FEC000
118 #define WDOG1_BASE_ADDR WDOG_BASE_ADDR
119 #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
121 /* IIM */
122 #define IIM_PREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x20))
123 #define IIM_PREV_SIG (0x1f << 3)
124 #define IIM_PREV_SIG_IMX31 (0x01 << 3) /* i.MX31 */
125 #define IIM_SREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x24))
126 #define IIM_SREV_SREV (0xff << 0)
127 #define IIM_SREV_1_0 0x00 /* i.MX31/L 1.0, L38W */
128 #define IIM_SREV_1_1 0x10 /* i.MX31 1.1, 2L38W */
129 #define IIM_SREV_1_1L 0x11 /* i.MX31L 1.1, 2L38W */
130 #define IIM_SREV_1_15 0x12 /* i.MX31 1.15, 2L38W/3L38W */
131 #define IIM_SREV_1_15L 0x13 /* i.MX31L 1.15, 2L38W/3L38W */
132 #define IIM_SREV_1_2 0x14 /* i.MX31 1.2, 3L38W, M45G */
133 #define IIM_SREV_1_2L 0x15 /* i.MX31L 1.2, 3L38W, M45G */
134 #define IIM_SREV_2_0_1 0x28 /* i.MX31 2.0/2.0.1, M91E */
135 #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */
137 /* IOMUXC */
138 #define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o)))
140 /* GPR */
141 #define IOMUXC_GPR IOMUXC_(0x008)
143 /* SW_MUX_CTL */
144 #define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD IOMUXC_(0x00C)
145 #define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x010)
146 #define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK IOMUXC_(0x014)
147 #define SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 IOMUXC_(0x018)
148 #define SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x01C)
149 #define SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS IOMUXC_(0x020)
150 #define SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ IOMUXC_(0x024)
151 #define SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x028)
152 #define SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I IOMUXC_(0x02C)
153 #define SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 IOMUXC_(0x030)
154 #define SW_MUX_CTL_LD11_LD12_LD13_LD14 IOMUXC_(0x034)
155 #define SW_MUX_CTL_LD7_LD8_LD9_LD10 IOMUXC_(0x038)
156 #define SW_MUX_CTL_LD3_LD4_LD5_LD6 IOMUXC_(0x03C)
157 #define SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 IOMUXC_(0x040)
158 #define SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 IOMUXC_(0x044)
159 #define SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK IOMUXC_(0x048)
160 #define SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x04C)
161 #define SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 IOMUXC_(0x050)
162 #define SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK IOMUXC_(0x054)
163 #define SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD IOMUXC_(0x058)
164 #define SW_MUX_CTL_RTCK_TCK_TMS_TDI IOMUXC_(0x05C)
165 #define SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 IOMUXC_(0x060)
166 #define SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x064)
167 #define SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 IOMUXC_(0x068)
168 #define SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 IOMUXC_(0x06C)
169 #define SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE IOMUXC_(0x070)
170 #define SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 IOMUXC_(0x074)
171 #define SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 IOMUXC_(0x078)
172 #define SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x07C)
173 #define SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 IOMUXC_(0x080)
174 #define SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 IOMUXC_(0x084)
175 #define SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x088)
176 #define SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 IOMUXC_(0x08C)
177 #define SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 IOMUXC_(0x090)
178 #define SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 IOMUXC_(0x094)
179 #define SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 IOMUXC_(0x098)
180 #define SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 IOMUXC_(0x09C)
181 #define SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x0A0)
182 #define SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC IOMUXC_(0x0A4)
183 #define SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 IOMUXC_(0x0A8)
184 #define SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x0AC)
185 #define SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 IOMUXC_(0x0B0)
186 #define SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE IOMUXC_(0x0B4)
187 #define SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x0B8)
188 #define SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON IOMUXC_(0x0BC)
189 #define SW_MUX_CTL_D2_D1_D0_PC_CD1_B IOMUXC_(0x0C0)
190 #define SW_MUX_CTL_D6_D5_D4_D3 IOMUXC_(0x0C4)
191 #define SW_MUX_CTL_D10_D9_D8_D7 IOMUXC_(0x0C8)
192 #define SW_MUX_CTL_D14_D13_D12_D11 IOMUXC_(0x0CC)
193 #define SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 IOMUXC_(0x0D0)
194 #define SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE IOMUXC_(0x0D4)
195 #define SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 IOMUXC_(0x0D8)
196 #define SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x0DC)
197 #define SW_MUX_CTL_RW_RAS_CAS_SDWE IOMUXC_(0x0E0)
198 #define SW_MUX_CTL_CS5_ECB_LBA_BCLK IOMUXC_(0x0E4)
199 #define SW_MUX_CTL_CS1_CS2_CS3_CS4 IOMUXC_(0x0E8)
200 #define SW_MUX_CTL_EB0_EB1_OE_CS0 IOMUXC_(0x0EC)
201 #define SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 IOMUXC_(0x0F0)
202 #define SW_MUX_CTL_SD28_SD29_SD30_SD31 IOMUXC_(0x0F4)
203 #define SW_MUX_CTL_SD24_SD25_SD26_SD27 IOMUXC_(0x0F8)
204 #define SW_MUX_CTL_SD20_SD21_SD22_SD23 IOMUXC_(0x0FC)
205 #define SW_MUX_CTL_SD16_SD17_SD18_SD19 IOMUXC_(0x100)
206 #define SW_MUX_CTL_SD12_SD13_SD14_SD15 IOMUXC_(0x104)
207 #define SW_MUX_CTL_SD8_SD9_SD10_SD11 IOMUXC_(0x108)
208 #define SW_MUX_CTL_SD4_SD5_SD6_SD7 IOMUXC_(0x10C)
209 #define SW_MUX_CTL_SD0_SD1_SD2_SD3 IOMUXC_(0x110)
210 #define SW_MUX_CTL_A24_A25_SDBA1_SDBA0 IOMUXC_(0x114)
211 #define SW_MUX_CTL_A20_A21_A22_A23 IOMUXC_(0x118)
212 #define SW_MUX_CTL_A16_A17_A18_A19 IOMUXC_(0x11C)
213 #define SW_MUX_CTL_A12_A13_A14_A15 IOMUXC_(0x120)
214 #define SW_MUX_CTL_A9_A10_MA10_A11 IOMUXC_(0x124)
215 #define SW_MUX_CTL_A5_A6_A7_A8 IOMUXC_(0x128)
216 #define SW_MUX_CTL_A1_A2_A3_A4 IOMUXC_(0x12C)
217 #define SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 IOMUXC_(0x130)
218 #define SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 IOMUXC_(0x134)
219 #define SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 IOMUXC_(0x138)
220 #define SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x13C)
221 #define SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH IOMUXC_(0x140)
222 #define SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 IOMUXC_(0x144)
223 #define SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x148)
224 #define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 IOMUXC_(0x14C)
225 #define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO IOMUXC_(0x150)
227 #define SW_MUX_OUT (0x7 << 4)
228 #define SW_MUX_OUT_GPIO_DR (0x0 << 4)
229 #define SW_MUX_OUT_FUNCTIONAL (0x1 << 4)
230 #define SW_MUX_OUT_ALT1 (0x2 << 4)
231 #define SW_MUX_OUT_ALT2 (0x3 << 4)
232 #define SW_MUX_OUT_ALT3 (0x4 << 4)
233 #define SW_MUX_OUT_ALT4 (0x5 << 4)
234 #define SW_MUX_OUT_ALT5 (0x6 << 4)
235 #define SW_MUX_OUT_ALT6 (0x7 << 4)
237 #define SW_MUX_IN (0xf << 0)
238 #define SW_MUX_IN_NO_INPUTS (0x0 << 0)
239 #define SW_MUX_IN_GPIO_PSR_ISR (0x1 << 0)
240 #define SW_MUX_IN_FUNCTIONAL (0x2 << 0)
241 #define SW_MUX_IN_ALT1 (0x4 << 0)
242 #define SW_MUX_IN_ALT2 (0x8 << 0)
244 /* Masks for each signal field */
245 #define SW_MUX_CTL_SIG1 (0x7f << 0)
246 #define SW_MUX_CTL_SIG2 (0x7f << 8)
247 #define SW_MUX_CTL_SIG3 (0x7f << 16)
248 #define SW_MUX_CTL_SIG4 (0x7f << 24)
249 /* Shift above flags into one of the four fields in each register */
250 #define SW_MUX_CTL_SIG1_POS (0)
251 #define SW_MUX_CTL_SIG2_POS (8)
252 #define SW_MUX_CTL_SIG3_POS (16)
253 #define SW_MUX_CTL_SIG4_POS (24)
255 /* SW_PAD_CTL */
256 #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154)
257 #define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY IOMUXC_(0x158)
258 #define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x15C)
259 #define SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B IOMUXC_(0x160)
260 #define SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR IOMUXC_(0x164)
261 #define SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3 IOMUXC_(0x168)
262 #define SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x16C)
263 #define SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL IOMUXC_(0x170)
264 #define SW_PAD_CTL_READ_VSYNC3_CONTRAST IOMUXC_(0x174)
265 #define SW_PAD_CTL_SER_RS_PAR_RS_WRITE IOMUXC_(0x178)
266 #define SW_PAD_CTL_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x17C)
267 #define SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO IOMUXC_(0x180)
268 #define SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT IOMUXC_(0x184)
269 #define SW_PAD_CTL_LD15_LD16_LD17 IOMUXC_(0x188)
270 #define SW_PAD_CTL_LD12_LD13_LD14 IOMUXC_(0x18C)
271 #define SW_PAD_CTL_LD9_LD10_LD11 IOMUXC_(0x190)
272 #define SW_PAD_CTL_LD6_LD7_LD8 IOMUXC_(0x194)
273 #define SW_PAD_CTL_LD3_LD4_LD5 IOMUXC_(0x198)
274 #define SW_PAD_CTL_LD0_LD1_LD2 IOMUXC_(0x19C)
275 #define SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1 IOMUXC_(0x1A0)
276 #define SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP IOMUXC_(0x1A4)
277 #define SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7 IOMUXC_(0x1A8)
278 #define SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x1AC)
279 #define SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1 IOMUXC_(0x1B0)
280 #define SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP IOMUXC_(0x1B4)
281 #define SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP IOMUXC_(0x1B8)
282 #define SW_PAD_CTL_TRSTB_DE_B_SJC_MOD IOMUXC_(0x1BC)
283 #define SW_PAD_CTL_TMS_TDI_TDO IOMUXC_(0x1C0)
284 #define SW_PAD_CTL_KEY_COL7_RTCK_TCK IOMUXC_(0x1C4)
285 #define SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6 IOMUXC_(0x1C8)
286 #define SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x1CC)
287 #define SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0 IOMUXC_(0x1D0)
288 #define SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5 IOMUXC_(0x1D4)
289 #define SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2 IOMUXC_(0x1D8)
290 #define SW_PAD_CTL_RTS2_CTS2_BATT_LINE IOMUXC_(0x1DC)
291 #define SW_PAD_CTL_DTR_DCE2_RXD2_TXD2 IOMUXC_(0x1E0)
292 #define SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1 IOMUXC_(0x1E4)
293 #define SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1 IOMUXC_(0x1E8)
294 #define SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x1EC)
295 #define SW_PAD_CTL_RXD1_TXD1_RTS1 IOMUXC_(0x1F0)
296 #define SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY IOMUXC_(0x1F4)
297 #define SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1 IOMUXC_(0x1F8)
298 #define SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x1FC)
299 #define SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS IOMUXC_(0x200)
300 #define SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO IOMUXC_(0x204)
301 #define SW_PAD_CTL_STXD6_SRXD6_SCK6 IOMUXC_(0x208)
302 #define SW_PAD_CTL_SRXD5_SCK5_SFS5 IOMUXC_(0x20C)
303 #define SW_PAD_CTL_SCK4_SFS4_STXD5 IOMUXC_(0x210)
304 #define SW_PAD_CTL_SFS3_STXD4_SRXD4 IOMUXC_(0x214)
305 #define SW_PAD_CTL_STXD3_SRXD3_SCK3 IOMUXC_(0x218)
306 #define SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x21C)
307 #define SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC IOMUXC_(0x220)
308 #define SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15 IOMUXC_(0x224)
309 #define SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12 IOMUXC_(0x228)
310 #define SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x22C)
311 #define SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6 IOMUXC_(0x230)
312 #define SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT IOMUXC_(0x234)
313 #define SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B IOMUXC_(0x238)
314 #define SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x23C)
315 #define SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1 IOMUXC_(0x240)
316 #define SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B IOMUXC_(0x244)
317 #define SW_PAD_CTL_D2_D1_D0 IOMUXC_(0x248)
318 #define SW_PAD_CTL_D5_D4_D3 IOMUXC_(0x24C)
319 #define SW_PAD_CTL_D8_D7_D6 IOMUXC_(0x250)
320 #define SW_PAD_CTL_D11_D10_D9 IOMUXC_(0x254)
321 #define SW_PAD_CTL_D14_D13_D12 IOMUXC_(0x258)
322 #define SW_PAD_CTL_NFCE_B_NFRB_D15 IOMUXC_(0x25C)
323 #define SW_PAD_CTL_NFALE_NFCLE_NFWP_B IOMUXC_(0x260)
324 #define SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B IOMUXC_(0x264)
325 #define SW_PAD_CTL_SDQS0_SDQS1_SDQS2 IOMUXC_(0x268)
326 #define SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x26C)
327 #define SW_PAD_CTL_CAS_SDWE_SDCKE0 IOMUXC_(0x270)
328 #define SW_PAD_CTL_BCLK_RW_RAS IOMUXC_(0x274)
329 #define SW_PAD_CTL_CS5_ECB_LBA IOMUXC_(0x278)
330 #define SW_PAD_CTL_CS2_CS3_CS4 IOMUXC_(0x27C)
331 #define SW_PAD_CTL_OE_CS0_CS1 IOMUXC_(0x280)
332 #define SW_PAD_CTL_DQM3_EB0_EB1 IOMUXC_(0x284)
333 #define SW_PAD_CTL_DQM0_DQM1_DQM2 IOMUXC_(0x288)
334 #define SW_PAD_CTL_SD29_SD30_SD31 IOMUXC_(0x28C)
335 #define SW_PAD_CTL_SD26_SD27_SD28 IOMUXC_(0x290)
336 #define SW_PAD_CTL_SD23_SD24_SD25 IOMUXC_(0x294)
337 #define SW_PAD_CTL_SD20_SD21_SD22 IOMUXC_(0x298)
338 #define SW_PAD_CTL_SD17_SD18_SD19 IOMUXC_(0x29C)
339 #define SW_PAD_CTL_SD14_SD15_SD16 IOMUXC_(0x2A0)
340 #define SW_PAD_CTL_SD11_SD12_SD13 IOMUXC_(0x2A4)
341 #define SW_PAD_CTL_SD8_SD9_SD10 IOMUXC_(0x2A8)
342 #define SW_PAD_CTL_SD5_SD6_SD7 IOMUXC_(0x2AC)
343 #define SW_PAD_CTL_SD2_SD3_SD4 IOMUXC_(0x2B0)
344 #define SW_PAD_CTL_SDBA0_SD0_SD1 IOMUXC_(0x2B4)
345 #define SW_PAD_CTL_A24_A25_SDBA1 IOMUXC_(0x2B8)
346 #define SW_PAD_CTL_A21_A22_A23 IOMUXC_(0x2BC)
347 #define SW_PAD_CTL_A18_A19_A20 IOMUXC_(0x2C0)
348 #define SW_PAD_CTL_A15_A16_A17 IOMUXC_(0x2C4)
349 #define SW_PAD_CTL_A12_A13_A14 IOMUXC_(0x2C8)
350 #define SW_PAD_CTL_A10_MA10_A11 IOMUXC_(0x2CC)
351 #define SW_PAD_CTL_A7_A8_A9 IOMUXC_(0x2D0)
352 #define SW_PAD_CTL_A4_A5_A6 IOMUXC_(0x2D4)
353 #define SW_PAD_CTL_A1_A2_A3 IOMUXC_(0x2D8)
354 #define SW_PAD_CTL_VPG0_VPG1_A0 IOMUXC_(0x2DC)
355 #define SW_PAD_CTL_VSTBY_DVFS0_DVFS1 IOMUXC_(0x2E0)
356 #define SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL IOMUXC_(0x2E4)
357 #define SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3 IOMUXC_(0x2E8)
358 #define SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x2EC)
359 #define SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B IOMUXC_(0x2F0)
360 #define SW_PAD_CTL_SVEN0_STX0_SRX0 IOMUXC_(0x2F4)
361 #define SW_PAD_CTL_GPIO3_1_SCLK0_SRST0 IOMUXC_(0x2F8)
362 #define SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x2FC)
363 #define SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4 IOMUXC_(0x300)
364 #define SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1 IOMUXC_(0x304)
365 #define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST IOMUXC_(0x308)
367 /* SW_PAD_CTL flags */
368 #define SW_PAD_CTL_LOOPBACK (0x1 << 9) /* Route output to input */
369 /* Pullup, pulldown and keeper enable */
370 #define SW_PAD_CTL_PUE_PKE (0x3 << 7)
371 #define SW_PAD_CTL_PUE_PKE_DISABLE (0x0 << 7)
372 #define SW_PAD_CTL_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */
373 #define SW_PAD_CTL_PUE_PKE_KEEPER (0x2 << 7)
374 #define SW_PAD_CTL_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */
375 /* Pullup/down resistance */
376 #define SW_PAD_CTL_PUS (0x3 << 5)
377 #define SW_PAD_CTL_PUS_DOWN_100K (0x0 << 5)
378 #define SW_PAD_CTL_PUS_UP_100K (0x1 << 5)
379 #if 0 /* Completeness */
380 #define SW_PAD_CTL_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */
381 #define SW_PAD_CTL_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */
382 #endif
383 #define SW_PAD_CTL_HYS (0x1 << 4) /* Schmitt trigger input */
384 #define SW_PAD_CTL_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/
385 #define SW_PAD_CTL_DSE (0x3 << 1)
386 #define SW_PAD_CTL_DSE_STD (0x0 << 1) /* Drive strength */
387 #define SW_PAD_CTL_DSE_HIGH (0x1 << 1)
388 #define SW_PAD_CTL_DSE_MAX (0x2 << 1)
389 #define SW_PAD_CTL_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */
390 #define SW_PAD_CTL_SRE (0x1 << 0) /* Slew rate, 1=fast */
392 /* Masks for each IO field */
393 #define SW_PAD_CTL_IO1 (0x3ff << 0)
394 #define SW_PAD_CTL_IO2 (0x3ff << 10)
395 #define SW_PAD_CTL_IO3 (0x3ff << 20)
397 /* Shift above flags into one of the three fields in each register */
398 #define SW_PAD_CTL_IO1_POS (0)
399 #define SW_PAD_CTL_IO2_POS (10)
400 #define SW_PAD_CTL_IO3_POS (20)
402 /* RNGA */
403 #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))
405 #define RNGA_CONTROL_SLEEP (1 << 4)
407 /* IPU */
408 #define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
409 #define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
410 #define IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
411 #define IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
412 #define IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
413 #define IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
414 #define IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
415 #define IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
416 #define IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
417 #define IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
418 #define IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
419 #define IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
420 #define IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
421 #define IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
422 #define IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
423 #define IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
424 #define IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
425 #define IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
426 #define IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
427 #define IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
428 #define IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
429 #define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
430 #define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
431 #define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
432 #define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4))
433 #define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8))
434 #define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC))
435 #define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0))
439 /* ATA */
440 #define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
441 #define ATA_TIME_ON (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
442 /* PIO */
443 #define ATA_TIME_1 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
444 #define ATA_TIME_2W (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
445 #define ATA_TIME_2R (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
446 #define ATA_TIME_AX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
447 #define ATA_TIME_PIO_RDX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x06))
448 #define ATA_TIME_4 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
449 #define ATA_TIME_9 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
450 /* MDMA */
451 #define ATA_TIME_M (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
452 #define ATA_TIME_JN (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
453 #define ATA_TIME_D (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
454 #define ATA_TIME_K (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
455 /* UDMA */
456 #define ATA_TIME_ACK (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
457 #define ATA_TIME_ENV (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
458 #define ATA_TIME_RPX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
459 #define ATA_TIME_ZAH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
460 #define ATA_TIME_MLIX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
461 #define ATA_TIME_DVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
462 #define ATA_TIME_DZFS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
463 #define ATA_TIME_DVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
464 #define ATA_TIME_CVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
465 #define ATA_TIME_SS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
466 #define ATA_TIME_CYC (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
467 /* */
468 #define ATA_FIFO_DATA_32 (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
469 #define ATA_FIFO_DATA_16 (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
470 #define ATA_FIFO_FILL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
471 /* Actually ATA_CONTROL but conflicts arise */
472 #define ATA_INTF_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
473 #define ATA_INTERRUPT_PENDING (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
474 #define ATA_INTERRUPT_ENABLE (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
475 #define ATA_INTERRUPT_CLEAR (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
476 #define ATA_FIFO_ALARM (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
477 #define ATA_DRIVE_DATA (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
478 #define ATA_DRIVE_FEATURES (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
479 #define ATA_DRIVE_SECTOR_COUNT (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
480 #define ATA_DRIVE_SECTOR_NUM (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
481 #define ATA_DRIVE_CYL_LOW (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
482 #define ATA_DRIVE_CYL_HIGH (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
483 #define ATA_DRIVE_CYL_HEAD (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
484 #define ATA_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
485 #define ATA_DRIVE_COMMAND (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
486 #define ATA_ALT_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
487 #define ATA_DRIVE_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
489 /* ATA_INTF_CONTROL flags */
490 #define ATA_FIFO_RST (1 << 7)
491 #define ATA_ATA_RST (1 << 6)
492 #define ATA_FIFO_TX_EN (1 << 5)
493 #define ATA_FIFO_RCV_EN (1 << 4)
494 #define ATA_DMA_PENDING (1 << 3)
495 #define ATA_DMA_ULTRA_SELECTED (1 << 2)
496 #define ATA_DMA_WRITE (1 << 1)
497 #define ATA_IORDY_EN (1 << 0)
499 /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
500 #define ATA_INTRQ1 (1 << 7) /* INTRQ to the DMA */
501 #define ATA_FIFO_UNDERFLOW (1 << 6)
502 #define ATA_FIFO_OVERFLOW (1 << 5)
503 #define ATA_CONTROLLER_IDLE (1 << 4)
504 #define ATA_INTRQ2 (1 << 3) /* INTRQ to the MCU */
506 /* EPIT */
507 #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
508 #define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
509 #define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
510 #define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
511 #define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
513 #define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
514 #define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
515 #define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
516 #define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
517 #define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
519 #define EPITCR_CLKSRC_OFF (0 << 24)
520 #define EPITCR_CLKSRC_IPG_CLK (1 << 24)
521 #define EPITCR_CLKSRC_IPG_CLK_HIGHFREQ (2 << 24)
522 #define EPITCR_CLKSRC_IPG_CLK_32K (3 << 24)
523 #define EPITCR_OM_DISCONNECTED (0 << 22)
524 #define EPITCR_OM_TOGGLE (1 << 22)
525 #define EPITCR_OM_CLEAR (2 << 22)
526 #define EPITCR_OM_SET (3 << 22)
527 #define EPITCR_STOPEN (1 << 21)
528 #define EPITCR_DOZEN (1 << 20)
529 #define EPITCR_WAITEN (1 << 19)
530 #define EPITCR_DBGEN (1 << 18)
531 #define EPITCR_IOVW (1 << 17)
532 #define EPITCR_SWR (1 << 16)
533 #define EPITCR_PRESCALER (0xfff << 4) /* Divide by n+1 */
534 #define EPITCR_PRESCALER_POS (4)
535 #define EPITCR_RLD (1 << 3)
536 #define EPITCR_OCIEN (1 << 2)
537 #define EPITCR_ENMOD (1 << 1)
538 #define EPITCR_EN (1 << 0)
540 #define EPITSR_OCIF (1 << 0)
542 /* GPT */
543 #define GPTCR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x00))
544 #define GPTPR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x04))
545 #define GPTSR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x08))
546 #define GPTIR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x0C))
547 #define GPTOCR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x10))
548 #define GPTOCR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x14))
549 #define GPTOCR3 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x18))
550 #define GPTICR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x1C))
551 #define GPTICR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x20))
552 #define GPTCNT (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x24))
554 /* GPTCR */
555 #define GPTCR_FO3 (0x1 << 31)
556 #define GPTCR_FO2 (0x1 << 30)
557 #define GPTCR_FO1 (0x1 << 29)
559 #define GPTCR_OM3 (0x7 << 26)
560 #define GPTCR_OM3_DISCONNECTED (0x0 << 26)
561 #define GPTCR_OM3_TOGGLE (0x1 << 26)
562 #define GPTCR_OM3_CLEAR (0x2 << 26)
563 #define GPTCR_OM3_SET (0x3 << 26)
564 #define GPTCR_OM3_SINGLE_COUNT (0x4 << 26)
565 /* 0x5-0x7 same as 0x4 */
567 #define GPTCR_OM2 (0x7 << 23)
568 #define GPTCR_OM2_DISCONNECTED (0x0 << 23)
569 #define GPTCR_OM2_TOGGLE (0x1 << 23)
570 #define GPTCR_OM2_CLEAR (0x2 << 23)
571 #define GPTCR_OM2_SET (0x3 << 23)
572 #define GPTCR_OM2_SINGLE_COUNT (0x4 << 23)
574 /* 0x5-0x7 same as 0x4 */
575 #define GPTCR_OM1 (0x7 << 20)
576 #define GPTCR_OM1_DISCONNECTED (0x0 << 20)
577 #define GPTCR_OM1_TOGGLE (0x1 << 20)
578 #define GPTCR_OM1_CLEAR (0x2 << 20)
579 #define GPTCR_OM1_SET (0x3 << 20)
580 #define GPTCR_OM1_SINGLE_COUNT (0x4 << 20)
582 /* 0x5-0x7 same as 0x4 */
583 #define GPTCR_IM2 (0x3 << 18)
584 #define GPTCR_IM2_DISABLED (0x0 << 18)
585 #define GPTCR_IM2_RISING (0x1 << 18)
586 #define GPTCR_IM2_FALLING (0x2 << 18)
587 #define GPTCR_IM2_BOTH (0x3 << 18)
589 #define GPTCR_IM1 (0x3 << 16)
590 #define GPTCR_IM1_DISABLED (0x0 << 16)
591 #define GPTCR_IM1_RISING (0x1 << 16)
592 #define GPTCR_IM1_FALLING (0x2 << 16)
593 #define GPTCR_IM1_BOTH (0x3 << 16)
595 #define GPTCR_SWR (0x1 << 15)
596 #define GPTCR_FRR (0x1 << 9)
598 #define GPTCR_CLKSRC (0x7 << 6)
599 #define GPTCR_CLKSRC_NONE (0x0 << 6)
600 #define GPTCR_CLKSRC_IPG_CLK (0x1 << 6)
601 #define GPTCR_CLKSRC_IPG_CLK_HIGHFREQ (0x2 << 6)
602 #define GPTCR_CLKSRC_IPG_CLK_32K (0x4 << 6)
603 /* Other values not defined */
605 #define GPTCR_STOPEN (0x1 << 5)
606 #define GPTCR_DOZEN (0x1 << 4)
607 #define GPTCR_WAITEN (0x1 << 3)
608 #define GPTCR_DBGEN (0x1 << 2)
609 #define GPTCR_ENMODE (0x1 << 1)
610 #define GPTCR_EN (0x1 << 0)
612 /* GPTSR */
613 #define GPTSR_ROV (0x1 << 5)
614 #define GPTSR_IF2 (0x1 << 4)
615 #define GPTSR_IF1 (0x1 << 3)
616 #define GPTSR_OF3 (0x1 << 2)
617 #define GPTSR_OF2 (0x1 << 1)
618 #define GPTSR_OF1 (0x1 << 0)
620 /* GPTIR */
621 #define GPTIR_ROV (0x1 << 5)
622 #define GPTIR_IF2IE (0x1 << 4)
623 #define GPTIR_IF1IE (0x1 << 3)
624 #define GPTIR_OF3IE (0x1 << 2)
625 #define GPTIR_OF2IE (0x1 << 1)
626 #define GPTIR_OF1IE (0x1 << 0)
628 /* GPIO */
629 #define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
630 #define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
631 #define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
632 #define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
633 #define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
634 #define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
635 #define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
637 #define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
638 #define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
639 #define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
640 #define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
641 #define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
642 #define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
643 #define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
645 #define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
646 #define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
647 #define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
648 #define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
649 #define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
650 #define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
651 #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
653 /* CSPI */
654 #define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
655 #define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
656 #define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
657 #define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
658 #define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
659 #define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
660 #define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
661 #define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
663 #define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
664 #define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
665 #define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
666 #define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
667 #define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
668 #define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
669 #define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
670 #define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
672 #define CSPI_RXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00))
673 #define CSPI_TXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04))
674 #define CSPI_CONREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08))
675 #define CSPI_INTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C))
676 #define CSPI_DMAREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10))
677 #define CSPI_STATREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14))
678 #define CSPI_PERIODREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18))
679 #define CSPI_TESTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0))
681 /* CSPI CONREG flags/fields */
682 #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24)
683 #define CSPI_CONREG_CHIP_SELECT_SS1 (1 << 24)
684 #define CSPI_CONREG_CHIP_SELECT_SS2 (2 << 24)
685 #define CSPI_CONREG_CHIP_SELECT_SS3 (3 << 24)
686 #define CSPI_CONREG_CHIP_SELECT_MASK (3 << 24)
687 #define CSPI_CONREG_DRCTL_DONT_CARE (0 << 20)
688 #define CSPI_CONREG_DRCTL_TRIG_FALLING (1 << 20)
689 #define CSPI_CONREG_DRCTL_TRIG_LOW (2 << 20)
690 #define CSPI_CONREG_DRCTL_TRIG_RSV (3 << 20)
691 #define CSPI_CONREG_DRCTL_MASK (3 << 20)
692 #define CSPI_CONREG_DATA_RATE_DIV_4 (0 << 16)
693 #define CSPI_CONREG_DATA_RATE_DIV_8 (1 << 16)
694 #define CSPI_CONREG_DATA_RATE_DIV_16 (2 << 16)
695 #define CSPI_CONREG_DATA_RATE_DIV_32 (3 << 16)
696 #define CSPI_CONREG_DATA_RATE_DIV_64 (4 << 16)
697 #define CSPI_CONREG_DATA_RATE_DIV_128 (5 << 16)
698 #define CSPI_CONREG_DATA_RATE_DIV_256 (6 << 16)
699 #define CSPI_CONREG_DATA_RATE_DIV_512 (7 << 16)
700 #define CSPI_CONREG_DATA_RATE_DIV_MASK (7 << 16)
701 #define CSPI_BITCOUNT(n) ((n) << 8)
702 #define CSPI_CONREG_SSPOL (1 << 7)
703 #define CSPI_CONREG_SSCTL (1 << 6)
704 #define CSPI_CONREG_PHA (1 << 6)
705 #define CSPI_CONREG_POL (1 << 4)
706 #define CSPI_CONREG_SMC (1 << 3)
707 #define CSPI_CONREG_XCH (1 << 2)
708 #define CSPI_CONREG_MODE (1 << 1)
709 #define CSPI_CONREG_EN (1 << 0)
711 /* CSPI INTREG flags */
712 #define CSPI_INTREG_TCEN (1 << 8)
713 #define CSPI_INTREG_BOEN (1 << 7)
714 #define CSPI_INTREG_ROEN (1 << 6)
715 #define CSPI_INTREG_RFEN (1 << 5)
716 #define CSPI_INTREG_RHEN (1 << 4)
717 #define CSPI_INTREG_RREN (1 << 3)
718 #define CSPI_INTREG_TFEN (1 << 2)
719 #define CSPI_INTREG_THEN (1 << 1)
720 #define CSPI_INTREG_TEEN (1 << 0)
722 /* CSPI DMAREG flags */
723 #define CSPI_DMAREG_RFDEN (1 << 5)
724 #define CSPI_DMAREG_RHDEN (1 << 4)
725 #define CSPI_DMAREG_THDEN (1 << 1)
726 #define CSPI_DMAREG_TEDEN (1 << 0)
728 /* CSPI STATREG flags */
729 #define CSPI_STATREG_TC (1 << 8) /* w1c */
730 #define CSPI_STATREG_BO (1 << 7) /* w1c */
731 #define CSPI_STATREG_RO (1 << 6)
732 #define CSPI_STATREG_RF (1 << 5)
733 #define CSPI_STATREG_RH (1 << 4)
734 #define CSPI_STATREG_RR (1 << 3)
735 #define CSPI_STATREG_TF (1 << 2)
736 #define CSPI_STATREG_TH (1 << 1)
737 #define CSPI_STATREG_TE (1 << 0)
739 /* CSPI PERIODREG flags */
740 #define CSPI_PERIODREG_CSRC (1 << 15)
742 /* CSPI TESTREG flags */
743 #define CSPI_TESTREG_SWAP (1 << 15)
744 #define CSPI_TESTREG_LBC (1 << 14)
746 /* I2C */
747 #define I2C_IADR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x0))
748 #define I2C_IFDR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x4))
749 #define I2C_I2CR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x8))
750 #define I2C_I2SR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0xC))
751 #define I2C_I2DR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x10))
753 #define I2C_IADR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x0))
754 #define I2C_IFDR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x4))
755 #define I2C_I2CR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x8))
756 #define I2C_I2SR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0xC))
757 #define I2C_I2DR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x10))
759 #define I2C_IADR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x0))
760 #define I2C_IFDR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x4))
761 #define I2C_I2CR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x8))
762 #define I2C_I2SR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0xC))
763 #define I2C_I2DR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x10))
765 /* IADR - [7:1] Address */
767 /* IFDR */
768 #define I2C_IFDR_DIV30 0x00
769 #define I2C_IFDR_DIV32 0x01
770 #define I2C_IFDR_DIV36 0x02
771 #define I2C_IFDR_DIV42 0x03
772 #define I2C_IFDR_DIV48 0x04
773 #define I2C_IFDR_DIV52 0x05
774 #define I2C_IFDR_DIV60 0x06
775 #define I2C_IFDR_DIV72 0x07
776 #define I2C_IFDR_DIV80 0x08
777 #define I2C_IFDR_DIV88 0x09
778 #define I2C_IFDR_DIV104 0x0a
779 #define I2C_IFDR_DIV128 0x0b
780 #define I2C_IFDR_DIV144 0x0c
781 #define I2C_IFDR_DIV160 0x0d
782 #define I2C_IFDR_DIV192 0x0e
783 #define I2C_IFDR_DIV240 0x0f
784 #define I2C_IFDR_DIV288 0x10
785 #define I2C_IFDR_DIV320 0x11
786 #define I2C_IFDR_DIV384 0x12
787 #define I2C_IFDR_DIV480 0x13
788 #define I2C_IFDR_DIV576 0x14
789 #define I2C_IFDR_DIV640 0x15
790 #define I2C_IFDR_DIV768 0x16
791 #define I2C_IFDR_DIV960 0x17
792 #define I2C_IFDR_DIV1152 0x18
793 #define I2C_IFDR_DIV1280 0x19
794 #define I2C_IFDR_DIV1536 0x1a
795 #define I2C_IFDR_DIV1920 0x1b
796 #define I2C_IFDR_DIV2304 0x1c
797 #define I2C_IFDR_DIV2560 0x1d
798 #define I2C_IFDR_DIV3072 0x1e
799 #define I2C_IFDR_DIV3840 0x1f
800 #define I2C_IFDR_DIV22 0x20
801 #define I2C_IFDR_DIV24 0x21
802 #define I2C_IFDR_DIV26 0x22
803 #define I2C_IFDR_DIV28 0x23
804 #define I2C_IFDR_DIV32_2 0x24
805 #define I2C_IFDR_DIV36_2 0x25
806 #define I2C_IFDR_DIV40 0x26
807 #define I2C_IFDR_DIV44 0x27
808 #define I2C_IFDR_DIV48_2 0x28
809 #define I2C_IFDR_DIV56 0x29
810 #define I2C_IFDR_DIV64 0x2a
811 #define I2C_IFDR_DIV72_2 0x2b
812 #define I2C_IFDR_DIV80_2 0x2c
813 #define I2C_IFDR_DIV96 0x2d
814 #define I2C_IFDR_DIV112 0x2e
815 #define I2C_IFDR_DIV128_2 0x2f
816 #define I2C_IFDR_DIV160_2 0x30
817 #define I2C_IFDR_DIV192_2 0x31
818 #define I2C_IFDR_DIV224 0x32
819 #define I2C_IFDR_DIV256 0x33
820 #define I2C_IFDR_DIV320_2 0x34
821 #define I2C_IFDR_DIV384_2 0x35
822 #define I2C_IFDR_DIV448 0x36
823 #define I2C_IFDR_DIV512 0x37
824 #define I2C_IFDR_DIV640_2 0x38
825 #define I2C_IFDR_DIV768_2 0x39
826 #define I2C_IFDR_DIV896 0x3a
827 #define I2C_IFDR_DIV1024 0x3b
828 #define I2C_IFDR_DIV1280_2 0x3c
829 #define I2C_IFDR_DIV1536_2 0x3d
830 #define I2C_IFDR_DIV1792 0x3e
831 #define I2C_IFDR_DIV2048 0x3f
833 /* I2CR */
834 #define I2C_I2CR_IEN (1 << 7)
835 #define I2C_I2CR_IIEN (1 << 6)
836 #define I2C_I2CR_MSTA (1 << 5)
837 #define I2C_I2CR_MTX (1 << 4)
838 #define I2C_I2CR_TXAK (1 << 3)
839 #define I2C_I2CR_RSATA (1 << 2)
841 /* I2SR */
842 #define I2C_I2SR_ICF (1 << 7)
843 #define I2C_I2SR_IAAS (1 << 6)
844 #define I2C_I2SR_IBB (1 << 5)
845 #define I2C_I2SR_IAL (1 << 4)
846 #define I2C_I2SR_SRW (1 << 2)
847 #define I2C_I2SR_IIF (1 << 1)
848 #define I2C_I2SR_RXAK (1 << 0)
850 /* I2DR - [7:0] Data */
852 /* AUDMUX */
853 #define AUDMUX_PTCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x00))
854 #define AUDMUX_PDCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x04))
855 #define AUDMUX_PTCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x08))
856 #define AUDMUX_PDCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x0C))
857 #define AUDMUX_PTCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x10))
858 #define AUDMUX_PDCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x14))
859 #define AUDMUX_PTCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x18))
860 #define AUDMUX_PDCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x1C))
861 #define AUDMUX_PTCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x20))
862 #define AUDMUX_PDCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x24))
863 #define AUDMUX_PTCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x28))
864 #define AUDMUX_PDCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x2C))
865 #define AUDMUX_PTCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x30))
866 #define AUDMUX_PDCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x34))
867 #define AUDMUX_CNMCR (*(REG32_PTR_T)(AUDMUX_BASE+0x38))
869 #define AUDMUX_PTCR_TFS_DIR (1 << 31)
871 #define AUDMUX_PTCR_TFSEL (0xf << 27)
872 #define AUDMUX_PTCR_TFSEL_TXFS (0x0 << 27)
873 #define AUDMUX_PTCR_TFSEL_RXFS (0x8 << 27)
874 #define AUDMUX_PTCR_TFSEL_PORT1 (0x0 << 27)
875 #define AUDMUX_PTCR_TFSEL_PORT2 (0x1 << 27)
876 #define AUDMUX_PTCR_TFSEL_PORT3 (0x2 << 27)
877 #define AUDMUX_PTCR_TFSEL_PORT4 (0x3 << 27)
878 #define AUDMUX_PTCR_TFSEL_PORT5 (0x4 << 27)
879 #define AUDMUX_PTCR_TFSEL_PORT6 (0x5 << 27)
880 #define AUDMUX_PTCR_TFSEL_PORT7 (0x6 << 27)
882 #define AUDMUX_PTCR_TCLKDIR (1 << 26)
884 #define AUDMUX_PTCR_TCSEL (0xf << 22)
885 #define AUDMUX_PTCR_TCSEL_TXFS (0x0 << 22)
886 #define AUDMUX_PTCR_TCSEL_RXFS (0x8 << 22)
887 #define AUDMUX_PTCR_TCSEL_PORT1 (0x0 << 22)
888 #define AUDMUX_PTCR_TCSEL_PORT2 (0x1 << 22)
889 #define AUDMUX_PTCR_TCSEL_PORT3 (0x2 << 22)
890 #define AUDMUX_PTCR_TCSEL_PORT4 (0x3 << 22)
891 #define AUDMUX_PTCR_TCSEL_PORT5 (0x4 << 22)
892 #define AUDMUX_PTCR_TCSEL_PORT6 (0x5 << 22)
893 #define AUDMUX_PTCR_TCSEL_PORT7 (0x6 << 22)
895 #define AUDMUX_PTCR_RFS_DIR (1 << 21)
897 #define AUDMUX_PTCR_RFSSEL (0xf << 17)
898 #define AUDMUX_PTCR_RFSSEL_TXFS (0x0 << 17)
899 #define AUDMUX_PTCR_RFSSEL_RXFS (0x8 << 17)
900 #define AUDMUX_PTCR_RFSSEL_PORT1 (0x0 << 17)
901 #define AUDMUX_PTCR_RFSSEL_PORT2 (0x1 << 17)
902 #define AUDMUX_PTCR_RFSSEL_PORT3 (0x2 << 17)
903 #define AUDMUX_PTCR_RFSSEL_PORT4 (0x3 << 17)
904 #define AUDMUX_PTCR_RFSSEL_PORT5 (0x4 << 17)
905 #define AUDMUX_PTCR_RFSSEL_PORT6 (0x5 << 17)
906 #define AUDMUX_PTCR_RFSSEL_PORT7 (0x6 << 17)
908 #define AUDMUX_PTCR_RCLKDIR (1 << 16)
910 #define AUDMUX_PTCR_RCSEL (0xf << 12)
911 #define AUDMUX_PTCR_RCSEL_TXFS (0x0 << 12)
912 #define AUDMUX_PTCR_RCSEL_RXFS (0x8 << 12)
913 #define AUDMUX_PTCR_RCSEL_PORT1 (0x0 << 12)
914 #define AUDMUX_PTCR_RCSEL_PORT2 (0x1 << 12)
915 #define AUDMUX_PTCR_RCSEL_PORT3 (0x2 << 12)
916 #define AUDMUX_PTCR_RCSEL_PORT4 (0x3 << 12)
917 #define AUDMUX_PTCR_RCSEL_PORT5 (0x4 << 12)
918 #define AUDMUX_PTCR_RCSEL_PORT6 (0x5 << 12)
919 #define AUDMUX_PTCR_RCSEL_PORT7 (0x6 << 12)
920 #define AUDMUX_PTCR_SYN (1 << 11)
922 #define AUDMUX_PDCR_RXDSEL (0x7 << 13)
923 #define AUDMUX_PDCR_RXDSEL_PORT1 (0 << 13)
924 #define AUDMUX_PDCR_RXDSEL_PORT2 (1 << 13)
925 #define AUDMUX_PDCR_RXDSEL_PORT3 (2 << 13)
926 #define AUDMUX_PDCR_RXDSEL_PORT4 (3 << 13)
927 #define AUDMUX_PDCR_RXDSEL_PORT5 (4 << 13)
928 #define AUDMUX_PDCR_RXDSEL_PORT6 (5 << 13)
929 #define AUDMUX_PDCR_RXDSEL_PORT7 (6 << 13)
930 #define AUDMUX_PDCR_TXRXEN (1 << 12)
932 #define AUDMUX_CNMCR_BEN (1 << 18)
933 #define AUDMUX_CNMCR_FSPOL (1 << 17)
934 #define AUDMUX_CNMCR_CLKPOL (1 << 16)
936 #define AUDMUX_CNMCR_CNTHI (0xff << 8)
937 #define AUDMUX_CNMCR_CNTHI_POS (8)
939 #define AUDMUX_CNMCR_CNTLOW (0xff << 0)
940 #define AUDMUX_CNMCR_CNTLOW_POS (0)
942 /* SSI */
943 #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00))
944 #define SSI_STX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x04))
945 #define SSI_SRX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x08))
946 #define SSI_SRX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x0C))
947 #define SSI_SCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x10))
948 #define SSI_SISR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x14))
949 #define SSI_SIER1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x18))
950 #define SSI_STCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x1C))
951 #define SSI_SRCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x20))
952 #define SSI_STCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x24))
953 #define SSI_SRCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x28))
954 #define SSI_SFCSR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x2C))
955 #define SSI_SACNT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x38))
956 #define SSI_SACADD1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x3C))
957 #define SSI_SACDAT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x40))
958 #define SSI_SATAG1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x44))
959 #define SSI_STMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x48))
960 #define SSI_SRMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x4C))
962 #define SSI_STX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x00))
963 #define SSI_STX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x04))
964 #define SSI_SRX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x08))
965 #define SSI_SRX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x0C))
966 #define SSI_SCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x10))
967 #define SSI_SISR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x14))
968 #define SSI_SIER2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x18))
969 #define SSI_STCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x1C))
970 #define SSI_SRCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x20))
971 #define SSI_STCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x24))
972 #define SSI_SRCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x28))
973 #define SSI_SFCSR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x2C))
974 #define SSI_SACNT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x38))
975 #define SSI_SACADD2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x3C))
976 #define SSI_SACDAT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x40))
977 #define SSI_SATAG2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x44))
978 #define SSI_STMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x48))
979 #define SSI_SRMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x4C))
981 /* SSI SCR */
982 #define SSI_SCR_CLK_IST (0x1 << 9)
983 #define SSI_SCR_TCHN_EN (0x1 << 8)
984 #define SSI_SCR_SYS_CLK_EN (0x1 << 7)
986 #define SSI_SCR_I2S_MODE (0x3 << 5)
987 #define SSI_SCR_I2S_MODE_NORMAL (0x0 << 5)
988 #define SSI_SCR_I2S_MODE_MASTER (0x1 << 5)
989 #define SSI_SCR_I2S_MODE_SLAVE (0x2 << 5)
990 #define SSI_SCR_I2S_MODE_NOR2 (0x3 << 5)
992 #define SSI_SCR_SYN (0x1 << 4)
993 #define SSI_SCR_NET (0x1 << 3)
994 #define SSI_SCR_RE (0x1 << 2)
995 #define SSI_SCR_TE (0x1 << 1)
996 #define SSI_SCR_SSIEN (0x1 << 0)
998 /* SSI SISR */
999 #define SSI_SISR_CMDAU (0x1 << 18)
1000 #define SSI_SISR_CMDDU (0x1 << 17)
1001 #define SSI_SISR_RXT (0x1 << 16)
1002 #define SSI_SISR_RDR1 (0x1 << 15)
1003 #define SSI_SISR_RDR0 (0x1 << 14)
1004 #define SSI_SISR_TDE1 (0x1 << 13)
1005 #define SSI_SISR_TDE0 (0x1 << 12)
1006 #define SSI_SISR_ROE1 (0x1 << 11)
1007 #define SSI_SISR_ROE0 (0x1 << 10)
1008 #define SSI_SISR_TUE1 (0x1 << 9)
1009 #define SSI_SISR_TUE0 (0x1 << 8)
1010 #define SSI_SISR_TFS (0x1 << 7)
1011 #define SSI_SISR_RFS (0x1 << 6)
1012 #define SSI_SISR_TLS (0x1 << 5)
1013 #define SSI_SISR_RLS (0x1 << 4)
1014 #define SSI_SISR_RFF1 (0x1 << 3)
1015 #define SSI_SISR_RFF2 (0x1 << 2)
1016 #define SSI_SISR_TFE1 (0x1 << 1)
1017 #define SSI_SISR_TFE0 (0x1 << 0)
1019 /* SSI SIER */
1020 #define SSI_SIER_RDMAE (0x1 << 22)
1021 #define SSI_SIER_RIE (0x1 << 21)
1022 #define SSI_SIER_TDMAE (0x1 << 20)
1023 #define SSI_SIER_TIE (0x1 << 19)
1024 #define SSI_SIER_CMDAU (0x1 << 18)
1025 #define SSI_SIER_CMDDU (0x1 << 17)
1026 #define SSI_SIER_RXT (0x1 << 16)
1027 #define SSI_SIER_RDR1 (0x1 << 15)
1028 #define SSI_SIER_RDR0 (0x1 << 14)
1029 #define SSI_SIER_TDE1 (0x1 << 13)
1030 #define SSI_SIER_TDE0 (0x1 << 12)
1031 #define SSI_SIER_ROE1 (0x1 << 11)
1032 #define SSI_SIER_ROE0 (0x1 << 10)
1033 #define SSI_SIER_TUE1 (0x1 << 9)
1034 #define SSI_SIER_TUE0 (0x1 << 8)
1035 #define SSI_SIER_TFS (0x1 << 7)
1036 #define SSI_SIER_RFS (0x1 << 6)
1037 #define SSI_SIER_TLS (0x1 << 5)
1038 #define SSI_SIER_RLS (0x1 << 4)
1039 #define SSI_SIER_RFF1 (0x1 << 3)
1040 #define SSI_SIER_RFF0 (0x1 << 2)
1041 #define SSI_SIER_TFE1 (0x1 << 1)
1042 #define SSI_SIER_TFE0 (0x1 << 0)
1044 /* SSI STCR */
1045 #define SSI_STCR_TXBIT0 (0x1 << 9)
1046 #define SSI_STCR_TFEN1 (0x1 << 8)
1047 #define SSI_STCR_TFEN0 (0x1 << 7)
1048 #define SSI_STCR_TFDIR (0x1 << 6)
1049 #define SSI_STCR_TXDIR (0x1 << 5)
1050 #define SSI_STCR_TSHFD (0x1 << 4)
1051 #define SSI_STCR_TSCKP (0x1 << 3)
1052 #define SSI_STCR_TFSI (0x1 << 2)
1053 #define SSI_STCR_TFSL (0x1 << 1)
1054 #define SSI_STCR_TEFS (0x1 << 0)
1056 /* SSI SRCR */
1057 #define SSI_SRCR_RXEXT (0x1 << 10)
1058 #define SSI_SRCR_RXBIT0 (0x1 << 9)
1059 #define SSI_SRCR_RFEN1 (0x1 << 8)
1060 #define SSI_SRCR_RFEN0 (0x1 << 7)
1061 #define SSI_SRCR_RFDIR (0x1 << 6)
1062 #define SSI_SRCR_RXDIR (0x1 << 5)
1063 #define SSI_SRCR_RSHFD (0x1 << 4)
1064 #define SSI_SRCR_RSCKP (0x1 << 3)
1065 #define SSI_SRCR_RFSI (0x1 << 2)
1066 #define SSI_SRCR_RFSL (0x1 << 1)
1067 #define SSI_SRCR_REFS (0x1 << 0)
1069 /* SSI STCCR/SRCCR */
1070 #define SSI_STRCCR_DIV2 (0x1 << 18)
1071 #define SSI_STRCCR_PSR (0x1 << 17)
1073 #define SSI_STRCCR_WL (0xf << 13)
1074 #define SSI_STRCCR_WL8 (0x3 << 13)
1075 #define SSI_STRCCR_WL10 (0x4 << 13)
1076 #define SSI_STRCCR_WL12 (0x5 << 13)
1077 #define SSI_STRCCR_WL16 (0x7 << 13)
1078 #define SSI_STRCCR_WL18 (0x8 << 13)
1079 #define SSI_STRCCR_WL20 (0x9 << 13)
1080 #define SSI_STRCCR_WL22 (0xa << 13)
1081 #define SSI_STRCCR_WL24 (0xb << 13)
1083 #define SSI_STRCCR_DC (0x1f << 8)
1084 #define SSI_STRCCR_DC_POS (8)
1086 #define SSI_STRCCR_PM (0xf << 0)
1087 #define SSI_STRCCR_PM_POS (0)
1089 /* SSI SFCSR */
1090 #define SSI_SFCSR_RFCNT1 (0xf << 28)
1091 #define SSI_SFCSR_RFCNT1_POS (28)
1093 #define SSI_SFCSR_TFCNT1 (0xf << 24)
1094 #define SSI_SFCSR_TFCNN1_POS (24)
1096 #define SSI_SFCSR_RFWM1 (0xf << 20)
1097 #define SSI_SFCSR_RFWM1_POS (20)
1099 #define SSI_SFCSR_TFWM1 (0xf << 16)
1100 #define SSI_SFCSR_TFWM1_POS (16)
1102 #define SSI_SFCSR_RFCNT0 (0xf << 12)
1103 #define SSI_SFCSR_RFCNT0_POS (12)
1105 #define SSI_SFCSR_TFCNT0 (0xf << 8)
1106 #define SSI_SFCSR_TFCNT0_POS (8)
1108 #define SSI_SFCSR_RFWM0 (0xf << 4)
1109 #define SSI_SFCSR_RFWM0_POS (4)
1111 #define SSI_SFCSR_TFWM0 (0xf << 0)
1112 #define SSI_SFCSR_TFWM0_POS (0)
1114 /* SACNT */
1115 #define SSI_SACNT_FRDIV (0x3f << 5)
1116 #define SSI_SACNT_FRDIV_POS (5)
1118 #define SSI_SACNT_WR (0x1 << 4)
1119 #define SSI_SACNT_RD (0x1 << 3)
1120 #define SSI_SACNT_TIF (0x1 << 2)
1121 #define SSI_SACNT_FV (0x1 << 1)
1122 #define SSI_SACNT_AC97EN (0x1 << 0)
1124 /* RTC */
1125 #define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
1126 #define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
1127 #define RTC_ALRM_HM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
1128 #define RTC_ALRM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
1129 #define RTC_CTL (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
1130 #define RTC_ISR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
1131 #define RTC_IENR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
1132 #define RTC_STPWCH (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
1133 #define RTC_DAYR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
1134 #define RTC_DAYALARM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
1136 /* Watchdog */
1137 #define WDOG_WCR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x00))
1138 #define WDOG_WSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x02))
1139 #define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04))
1141 #define WDOG_WCR_WT (0xff << 8)
1142 #define WDOG_WCR_WT_POS (8)
1144 #define WDOG_WCR_WOE (0x1 << 6)
1145 #define WDOG_WCR_WDA (0x1 << 5)
1146 #define WDOG_WCR_SRS (0x1 << 4)
1147 #define WDOG_WCR_WRE (0x1 << 3)
1148 #define WDOG_WCR_WDE (0x1 << 2)
1149 #define WDOG_WCR_WDBG (0x1 << 1)
1150 #define WDOG_WCR_WDZST (0x1 << 0)
1152 #define WDOG_WRSR_JRST (0x1 << 5)
1153 #define WDOG_WRSR_PWR (0x1 << 4)
1154 #define WDOG_WRSR_EXT (0x1 << 3)
1155 #define WDOG_WRSR_CMON (0x1 << 2)
1156 #define WDOG_WRSR_TOUT (0x1 << 1)
1157 #define WDOG_WRSR_SFTW (0x1 << 0)
1159 /* Keypad */
1160 #define KPP_KPCR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
1161 #define KPP_KPSR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
1162 #define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
1163 #define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
1165 /* KPP_KPSR bits */
1166 #define KPP_KPSR_KRIE (1 << 9)
1167 #define KPP_KPSR_KDIE (1 << 8)
1168 #define KPP_KPSR_KRSS (1 << 3)
1169 #define KPP_KPSR_KDSC (1 << 2)
1170 #define KPP_KPSR_KPKR (1 << 1)
1171 #define KPP_KPSR_KPKD (1 << 0)
1173 /* SDHC */
1174 #define SDHC1_CLOCK_CONTROL (*(REG32_PTR_T)(MMC_SDHC1_BASE_ADDR+0x00))
1175 #define SDHC2_CLOCK_CONTROL (*(REG32_PTR_T)(MMC_SDHC2_BASE_ADDR+0x00))
1177 /* SDHC bits */
1178 #define STOP_CLK (1 << 0)
1180 /* ROMPATCH and AVIC */
1181 #define ROMPATCH_BASE_ADDR 0x60000000
1183 /* Since AVIC vector registers are NOT used, we reserve some for various
1184 * purposes. Copied from Linux source code. */
1185 #define CHIP_REV_1_0 0x10
1186 #define CHIP_REV_2_0 0x20
1187 #define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1)
1188 #define SYSTEM_REV_ID_MAG 0xF00C
1191 * NAND, SDRAM, WEIM, M3IF, EMI controllers
1193 #define EXT_MEM_CTRL_BASE 0xB8000000
1194 #define NFC_BASE EXT_MEM_CTRL_BASE
1195 #define ESDCTL_BASE 0xB8001000
1196 #define WEIM_BASE_ADDR 0xB8002000
1197 #define WEIM_CTRL_CS0 (WEIM_BASE_ADDR+0x00)
1198 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR+0x10)
1199 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR+0x20)
1200 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR+0x30)
1201 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR+0x40)
1202 #define M3IF_BASE 0xB8003000
1203 #define PCMCIA_CTL_BASE 0xB8004000
1206 * Memory regions and CS
1208 #define IPU_MEM_BASE_ADDR 0x70000000
1209 #define CSD0_BASE_ADDR 0x80000000
1210 #define CSD1_BASE_ADDR 0x90000000
1211 #define CS0_BASE_ADDR 0xA0000000
1212 #define CS1_BASE_ADDR 0xA8000000
1213 #define CS2_BASE_ADDR 0xB0000000
1214 #define CS3_BASE_ADDR 0xB2000000
1215 #define CS4_BASE_ADDR 0xB4000000
1216 #define CS4_BASE_PSRAM 0xB5000000
1217 #define CS5_BASE_ADDR 0xB6000000
1218 #define PCMCIA_MEM_BASE_ADDR 0xC0000000
1220 #define INTERNAL_ROM_VA 0xF0000000
1223 * SDRAM
1225 #define RAM_BANK0_BASE SDRAM_BASE_ADDR
1228 * IRQ Controller Register Definitions.
1230 #define AVIC_BASE_ADDR 0x68000000
1231 #define AVIC_INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
1232 #define AVIC_NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
1233 #define AVIC_INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
1234 #define AVIC_INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
1235 #define AVIC_INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
1236 #define AVIC_INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
1237 #define AVIC_INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
1238 #define AVIC_INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
1239 #define AVIC_NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
1240 #define AVIC_NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
1241 #define AVIC_NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
1242 #define AVIC_NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
1243 #define AVIC_NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
1244 #define AVIC_NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
1245 #define AVIC_NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
1246 #define AVIC_NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
1247 #define AVIC_NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
1248 #define AVIC_NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
1249 #define AVIC_FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
1250 #define AVIC_INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
1251 #define AVIC_INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
1252 #define AVIC_INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
1253 #define AVIC_INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
1254 #define AVIC_NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
1255 #define AVIC_NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
1256 #define AVIC_FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
1257 #define AVIC_FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
1258 #define AVIC_VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
1259 #define AVIC_VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
1261 /* The vectors go all the way up to 63. 4 bytes for each */
1262 #define AVIC_INTCNTL_ABFLAG (1 << 25)
1263 #define AVIC_INTCNTL_ABFEN (1 << 24)
1264 #define AVIC_INTCNTL_NIDIS (1 << 22)
1265 #define AVIC_INTCNTL_FIDIS (1 << 21)
1266 #define AVIC_INTCNTL_NIAD (1 << 20)
1267 #define AVIC_INTCNTL_FIAD (1 << 19)
1268 #define AVIC_INTCNTL_NM (1 << 18)
1270 /* L210 */
1271 #define L2CC_BASE_ADDR 0x30000000
1272 #define L2_CACHE_LINE_SIZE 32
1273 #define L2_CACHE_CTL_REG 0x100
1274 #define L2_CACHE_AUX_CTL_REG 0x104
1275 #define L2_CACHE_SYNC_REG 0x730
1276 #define L2_CACHE_INV_LINE_REG 0x770
1277 #define L2_CACHE_INV_WAY_REG 0x77C
1278 #define L2_CACHE_CLEAN_LINE_REG 0x7B0
1279 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
1281 #define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
1283 /* CCM */
1284 #define CCM_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
1285 #define CCM_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
1286 #define CCM_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
1287 #define CCM_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
1288 #define CCM_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
1289 #define CCM_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
1290 #define CCM_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
1291 #define CCM_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
1292 #define CCM_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
1293 #define CCM_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
1294 #define CCM_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
1295 #define CCM_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
1296 #define CCM_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
1297 #define CCM_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
1298 #define CCM_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
1299 #define CCM_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
1300 #define CCM_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
1301 #define CCM_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
1302 #define CCM_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
1303 #define CCM_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
1304 #define CCM_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
1305 #define CCM_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
1306 #define CCM_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
1307 #define CCM_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
1308 #define CCM_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
1309 #define CCM_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
1311 /* CCMR */
1312 #define CCM_CCMR_L2PG (0x1 << 29)
1313 #define CCM_CCMR_VSTBY (0x1 << 28)
1314 #define CCM_CCMR_WBEN (0x1 << 27)
1315 #define CCM_CCMR_FPMF (0x1 << 26)
1316 #define CCM_CCMR_CSCS (0x1 << 25)
1317 #define CCM_CCMR_PERCS (0x1 << 24)
1319 #define CCM_CCMR_SSI2S (0x3 << 21)
1320 #define CCM_CCMR_SSI2S_MCU_CLK (0x0 << 21)
1321 #define CCM_CCMR_SSI2S_USB_CLK (0x1 << 21)
1322 #define CCM_CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */
1324 #define CCM_CCMR_SSI1S (0x3 << 18)
1325 #define CCM_CCMR_SSI1S_MCU_CLK (0x0 << 18)
1326 #define CCM_CCMR_SSI1S_USB_CLK (0x1 << 18)
1327 #define CCM_CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */
1329 #define CCM_CCMR_RAMW (0x3 << 16)
1330 #define CCM_CCMR_RAMW_0ARM_0ALTMS (0x0 << 16)
1331 #define CCM_CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */
1332 #define CCM_CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */
1333 #define CCM_CCMR_RAMW_1ARM_1ALTMS (0x3 << 16)
1335 #define CCM_CCMR_LPM (0x3 << 14)
1336 #define CCM_CCMR_LPM_WAIT_MODE (0x0 << 14)
1337 #define CCM_CCMR_LPM_DOZE_MODE (0x1 << 14)
1338 #define CCM_CCMR_LPM_SRM (0x2 << 14) /* State retention mode */
1339 #define CCM_CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */
1341 #define CCM_CCMR_FIRS (0x3 << 11)
1342 #define CCM_CCMR_FIRS_MCU_CLK (0x0 << 11)
1343 #define CCM_CCMR_FIRS_USB_CLK (0x1 << 11)
1344 #define CCM_CCMR_FIRS_SERIAL_CLK (0x2 << 11)
1346 #define CCM_CCMR_WAMO (0x1 << 10)
1347 #define CCM_CCMR_UPE (0x1 << 9)
1348 #define CCM_CCMR_SPE (0x1 << 8)
1349 #define CCM_CCMR_MDS (0x1 << 7)
1351 #define CCM_CCMR_ROMW (0x3 << 5)
1352 #define CCM_CCMR_ROMW_0ARM_0ALTMS (0x0 << 5)
1353 #define CCM_CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */
1354 #define CCM_CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */
1355 #define CCM_CCMR_ROMW_1ARM_1ALTMS (0x3 << 5)
1357 #define CCM_CCMR_SBYCS (0x1 << 4)
1358 #define CCM_CCMR_MPE (0x1 << 3)
1360 #define CCM_CCMR_PRCS (0x3 << 1)
1361 #define CCM_CCMR_PRCS_FPM (0x1 << 1)
1362 #define CCM_CCMR_PRCS_CKIH (0x2 << 1)
1364 #define CCM_CCMR_FPME (0x1 << 0)
1366 /* PDR0 */
1367 #define CCM_PDR0_CSI_PODF (0x1ff << 23)
1368 #define CCM_PDR0_CSI_PODF_POS (23)
1370 #define CCM_PDR0_PER_PODF (0x1f << 16)
1371 #define CCM_PDR0_PER_PODF_POS (16)
1373 #define CCM_PDR0_HSP_PODF (0x7 << 11)
1374 #define CCM_PDR0_HSP_PODF_POS (11)
1376 #define CCM_PDR0_NFC_PODF (0x7 << 8)
1377 #define CCM_PDR0_NFC_PODF_POS (8)
1379 #define CCM_PDR0_IPG_PODF (0x3 << 6)
1380 #define CCM_PDR0_IPG_PODF_POS (6)
1382 #define CCM_PDR0_MAX_PODF (0x7 << 3)
1383 #define CCM_PDR0_MAX_PODF_POS (3)
1385 #define CCM_PDR0_MCU_PODF (0x7 << 0)
1386 #define CCM_PDR0_MCU_PODF_POS (0)
1388 /* PDR1 */
1389 #define CCM_PDR1_USB_PRDF (0x3 << 30)
1390 #define CCM_PDR1_USB_PRDF_POS (30)
1392 #define CCM_PDR1_USB_PODF (0x7 << 27)
1393 #define CCM_PDR1_USB_PODF_POS (27)
1395 #define CCM_PDR1_FIRI_PRE_PODF (0x7 << 24)
1396 #define CCM_PDR1_FIRI_PRE_PODF_POS (24)
1398 #define CCM_PDR1_FIRI_PODF (0x3f << 18)
1399 #define CCM_PDR1_FIRI_PODF_POS (18)
1401 #define CCM_PDR1_SSI2_PRE_PODF (0x7 << 15)
1402 #define CCM_PDR1_SSI2_PRE_PODF_POS (15)
1404 #define CCM_PDR1_SSI2_PODF (0x3f << 9)
1405 #define CCM_PDR1_SSI2_PODF_POS (9)
1407 #define CCM_PDR1_SSI1_PRE_PODF (0x7 << 6)
1408 #define CCM_PDR1_SSI1_PRE_PODF_POS (6)
1410 #define CCM_PDR1_SSI1_PODF (0x3f << 0)
1411 #define CCM_PDR1_SSI1_PODF_POS (0)
1413 #define CCM_WIMR0_GPIO3 (1 << 0)
1414 #define CCM_WIMR0_GPIO2 (1 << 1)
1415 #define CCM_WIMR0_GPIO1 (1 << 2)
1416 #define CCM_WIMR0_PCMCIA (1 << 3)
1417 #define CCM_WIMR0_WDT (1 << 4)
1418 #define CCM_WIMR0_USB_OTG (1 << 5)
1419 #define CCM_WIMR0_IPI_INT_UH2 (1 << 6)
1420 #define CCM_WIMR0_IPI_INT_UH1 (1 << 7)
1421 #define CCM_WIMR0_IPI_INT_UART5_ANDED (1 << 8)
1422 #define CCM_WIMR0_IPI_INT_UART4_ANDED (1 << 9)
1423 #define CCM_WIMR0_IPI_INT_UART3_ANDED (1 << 10)
1424 #define CCM_WIMR0_IPI_INT_UART2_ANDED (1 << 11)
1425 #define CCM_WIMR0_IPI_INT_UART1_ANDED (1 << 12)
1426 #define CCM_WIMR0_IPI_INT_SIM_DATA_IRQ (1 << 13)
1427 #define CCM_WIMR0_IPI_INT_SDHC2 (1 << 14)
1428 #define CCM_WIMR0_IPI_INT_SDHC1 (1 << 15)
1429 #define CCM_WIMR0_IPI_INT_RTC (1 << 16)
1430 #define CCM_WIMR0_IPI_INT_PWM (1 << 17)
1431 #define CCM_WIMR0_IPI_INT_KPP (1 << 18)
1432 #define CCM_WIMR0_IPI_INT_IIM (1 << 19)
1433 #define CCM_WIMR0_IPI_INT_GPT (1 << 20)
1434 #define CCM_WIMR0_IPI_INT_FIR (1 << 21)
1435 #define CCM_WIMR0_IPI_INT_EPIT2 (1 << 22)
1436 #define CCM_WIMR0_IPI_INT_EPIT1 (1 << 23)
1437 #define CCM_WIMR0_IPI_INT_CSPI2 (1 << 24)
1438 #define CCM_WIMR0_IPI_INT_CSPI1 (1 << 25)
1439 #define CCM_WIMR0_IPI_INT_POWER_FAIL (1 << 26)
1440 #define CCM_WIMR0_IPI_INT_CSPI3 (1 << 27)
1441 #define CCM_WIMR0_RESERVED28 (1 << 28)
1442 #define CCM_WIMR0_RESERVED29 (1 << 29)
1443 #define CCM_WIMR0_RESERVED30 (1 << 30)
1444 #define CCM_WIMR0_RESERVED31 (1 << 31)
1446 /* WEIM - CS0 */
1447 #define CSCRU 0x00
1448 #define CSCRL 0x04
1449 #define CSCRA 0x08
1451 /* ESDCTL */
1452 #define ESDCTL_ESDCTL0 0x00
1453 #define ESDCTL_ESDCFG0 0x04
1454 #define ESDCTL_ESDCTL1 0x08
1455 #define ESDCTL_ESDCFG1 0x0C
1456 #define ESDCTL_ESDMISC 0x10
1458 /* More UART 1 Register defines */
1459 #define URXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
1460 #define UTXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
1461 #define UCR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
1462 #define UCR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
1463 #define UCR3_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
1464 #define UCR4_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
1465 #define UFCR1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
1466 #define USR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
1467 #define USR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
1468 #define UTS1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
1470 #define UCR1_2 (*(REG32_PTR_T)(UART2_BASE_ADDR+0x80))
1471 #define UCR1_3 (*(REG32_PTR_T)(UART3_BASE_ADDR+0x80))
1472 #define UCR1_4 (*(REG32_PTR_T)(UART4_BASE_ADDR+0x80))
1473 #define UCR1_5 (*(REG32_PTR_T)(UART5_BASE_ADDR+0x80))
1476 * UART Control Register 0 Bit Fields.
1478 #define EUARTUCR1_ADEN (1 << 15) // Auto detect interrupt
1479 #define EUARTUCR1_ADBR (1 << 14) // Auto detect baud rate
1480 #define EUARTUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
1481 #define EUARTUCR1_IDEN (1 << 12) // Idle condition interrupt
1482 #define EUARTUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
1483 #define EUARTUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
1484 #define EUARTUCR1_IREN (1 << 7) // Infrared interface enable
1485 #define EUARTUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
1486 #define EUARTUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
1487 #define EUARTUCR1_SNDBRK (1 << 4) // Send break
1488 #define EUARTUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
1489 #define EUARTUCR1_DOZE (1 << 1) // Doze
1490 #define EUARTUCR1_UARTEN (1 << 0) // UART enabled
1491 #define EUARTUCR2_ESCI (1 << 15) // Escape seq interrupt enable
1492 #define EUARTUCR2_IRTS (1 << 14) // Ignore RTS pin
1493 #define EUARTUCR2_CTSC (1 << 13) // CTS pin control
1494 #define EUARTUCR2_CTS (1 << 12) // Clear to send
1495 #define EUARTUCR2_ESCEN (1 << 11) // Escape enable
1496 #define EUARTUCR2_PREN (1 << 8) // Parity enable
1497 #define EUARTUCR2_PROE (1 << 7) // Parity odd/even
1498 #define EUARTUCR2_STPB (1 << 6) // Stop
1499 #define EUARTUCR2_WS (1 << 5) // Word size
1500 #define EUARTUCR2_RTSEN (1 << 4) // Request to send interrupt enable
1501 #define EUARTUCR2_ATEN (1 << 3) // Aging timer enable
1502 #define EUARTUCR2_TXEN (1 << 2) // Transmitter enabled
1503 #define EUARTUCR2_RXEN (1 << 1) // Receiver enabled
1504 #define EUARTUCR2_SRST_ (1 << 0) // SW reset
1505 #define EUARTUCR3_PARERREN (1 << 12) // Parity enable
1506 #define EUARTUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
1507 #define EUARTUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
1508 #define EUARTUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
1509 #define EUARTUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
1510 #define EUARTUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
1511 #define EUARTUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
1512 #define EUARTUCR3_INVT (1 << 1) // Inverted Infrared transmission
1513 #define EUARTUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
1514 #define EUARTUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
1515 #define EUARTUCR4_INVR (1 << 9) // Inverted infrared reception
1516 #define EUARTUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
1517 #define EUARTUCR4_WKEN (1 << 7) // Wake interrupt enable
1518 #define EUARTUCR4_IRSC (1 << 5) // IR special case
1519 #define EUARTUCR4_LPBYP (1 << 4) // Low power bypass
1520 #define EUARTUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
1521 #define EUARTUCR4_BKEN (1 << 2) // Break condition interrupt enable
1522 #define EUARTUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
1523 #define EUARTUCR4_DREN (1 << 0) // Recv data ready interrupt enable
1524 #define EUARTUFCR_RXTL_SHF 0 // Receiver trigger level shift
1525 #define EUARTUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
1526 #define EUARTUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
1527 #define EUARTUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
1528 #define EUARTUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
1529 #define EUARTUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
1530 #define EUARTUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
1531 #define EUARTUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
1532 #define EUARTUFCR_TXTL_SHF 10 // Transmitter trigger level shift
1533 #define EUARTUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
1534 #define EUARTUSR1_RTSS (1 << 14) // RTS pin status
1535 #define EUARTUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
1536 #define EUARTUSR1_RTSD (1 << 12) // RTS delta
1537 #define EUARTUSR1_ESCF (1 << 11) // Escape seq interrupt flag
1538 #define EUARTUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
1539 #define EUARTUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
1540 #define EUARTUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
1541 #define EUARTUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
1542 #define EUARTUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
1543 #define EUARTUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
1544 #define EUARTUSR2_ADET (1 << 15) // Auto baud rate detect complete
1545 #define EUARTUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
1546 #define EUARTUSR2_IDLE (1 << 12) // Idle condition
1547 #define EUARTUSR2_ACST (1 << 11) // Autobaud counter stopped
1548 #define EUARTUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
1549 #define EUARTUSR2_WAKE (1 << 7) // Wake
1550 #define EUARTUSR2_RTSF (1 << 4) // RTS edge interrupt flag
1551 #define EUARTUSR2_TXDC (1 << 3) // Transmitter complete
1552 #define EUARTUSR2_BRCD (1 << 2) // Break condition
1553 #define EUARTUSR2_ORE (1 << 1) // Overrun error
1554 #define EUARTUSR2_RDR (1 << 0) // Recv data ready
1555 #define EUARTUTS_FRCPERR (1 << 13) // Force parity error
1556 #define EUARTUTS_LOOP (1 << 12) // Loop tx and rx
1557 #define EUARTUTS_TXEMPTY (1 << 6) // TxFIFO empty
1558 #define EUARTUTS_RXEMPTY (1 << 5) // RxFIFO empty
1559 #define EUARTUTS_TXFULL (1 << 4) // TxFIFO full
1560 #define EUARTUTS_RXFULL (1 << 3) // RxFIFO full
1561 #define EUARTUTS_SOFTRST (1 << 0) // Software reset
1563 /* SDMA */
1564 #define SDMA_MC0PTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x000))
1565 #define SDMA_INTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x004))
1566 #define SDMA_STOP_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x008))
1567 #define SDMA_HSTART (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x00C))
1568 #define SDMA_EVTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x010))
1569 #define SDMA_DSPOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x014))
1570 #define SDMA_HOSTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x018))
1571 #define SDMA_EVTPEND (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x01C))
1572 #define SDMA_DSPENBL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x020))
1573 #define SDMA_RESET (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x024))
1574 #define SDMA_EVTERR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x028))
1575 #define SDMA_INTRMSK (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x02C))
1576 #define SDMA_PSW (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x030))
1577 #define SDMA_EVTERRDBG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x034))
1578 #define SDMA_CONFIG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x038))
1579 #define SDMA_ONCE_ENB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x040))
1580 #define SDMA_ONCE_DATA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x044))
1581 #define SDMA_ONCE_INSTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x048))
1582 #define SDMA_ONCE_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x04C))
1583 #define SDMA_ONCE_CMD (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x050))
1584 #define SDMA_EVT_MIRROR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x054))
1585 #define SDMA_ILLINSTADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x058))
1586 #define SDMA_CHN0ADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x05C))
1587 #define SDMA_ONCE_RTB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x060))
1588 #define SDMA_XTRIG_CONF1 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x070))
1589 #define SDMA_XTRIG_CONF2 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x074))
1591 /* SDMA_CHNENBL: 0x080 - 0x0FC */
1592 #define SDMA_CHNENBL(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x080))[n]) /* 0..31 */
1594 /* SDMA_CHNPRI: 0x100 - 0x17C */
1595 #define SDMA_CHNPRI(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x100))[n]) /* 0..31 */
1597 #define SDMA_ONCE_COUNT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x200))
1598 #define SDMA_ONCE_ECTL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x204))
1599 #define SDMA_ONCE_EAA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x208))
1600 #define SDMA_ONCE_EAB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x20C))
1601 #define SDMA_ONCE_EAM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x210))
1602 #define SDMA_ONCE_ED (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x214))
1603 #define SDMA_ONCE_EDM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x218))
1604 #define SDMA_ONCE_PCMATCH (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x21C))
1606 /* SDMA_RESET */
1607 #define SDMA_RESET_RESCHED (0x1 << 1)
1608 #define SDMA_RESET_RESET (0x1 << 0)
1610 /* SDMA_PSW */
1611 #define SDMA_PSW_NCP (0x7 << 13)
1612 #define SDMA_PSW_NCR (0x1f << 8)
1613 #define SDMA_PSW_CCP (0x7 << 5)
1614 #define SDMA_PSW_CCR (0x1f << 0)
1616 /* SDMA_CONFIG */
1617 #define SDMA_CONFIG_DSPDMA (0x1 << 12)
1618 #define SDMA_CONFIG_RTDOBS (0x1 << 11)
1619 #define SDMA_CONFIG_ACR (0x1 << 4)
1620 #define SDMA_CONFIG_CSM (0x3 << 0)
1621 #define SDMA_CONFIG_CSM_STATIC (0x0 << 0)
1622 #define SDMA_CONFIG_CSM_DYNAMIC_LOW_POWER (0x1 << 0)
1623 #define SDMA_CONFIG_CSM_DYNAMIC_NO_LOOP (0x2 << 0)
1624 #define SDMA_CONFIG_CSM_DYNAMIC (0x3 << 0)
1626 /* SDMA_ONCE_ENB */
1627 #define SDMA_ONCE_ENB_ENB (0x1 << 0)
1629 /* SDMA_ONCE_STAT */
1630 #define SDMA_ONCE_STAT_PST (0xf << 12)
1631 #define SDMA_ONCE_STAT_PST_PROGRAM (0x0 << 12)
1632 #define SDMA_ONCE_STAT_PST_DATA (0x1 << 12)
1633 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW (0x2 << 12)
1634 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP (0x3 << 12)
1635 #define SDMA_ONCE_STAT_PST_DEBUG (0x4 << 12)
1636 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT (0x5 << 12)
1637 #define SDMA_ONCE_STAT_PST_SLEEP (0x6 << 12)
1638 #define SDMA_ONCE_STAT_PST_SAVE (0x7 << 12)
1639 #define SDMA_ONCE_STAT_PST_PROGRAM_IN_SLEEP (0x8 << 12)
1640 #define SDMA_ONCE_STAT_PST_DATA_IN_SLEEP (0x9 << 12)
1641 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_SLEEP (0xa << 12)
1642 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP_IN_SLEEP (0xb << 12)
1643 #define SDMA_ONCE_STAT_PST_DEBUG_IN_SLEEP (0xc << 12)
1644 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT_IN_SLEEP (0xd << 12)
1645 #define SDMA_ONCE_STAT_PST_SLEEP_AFTER_RESET (0xe << 12)
1646 #define SDMA_ONCE_STAT_PST_RESTORE (0xf << 12)
1647 #define SDMA_ONCE_STAT_RCV (0x1 << 11)
1648 #define SDMA_ONCE_STAT_EDR (0x1 << 10)
1649 #define SDMA_ONCE_STAT_ODR (0x1 << 9)
1650 #define SDMA_ONCE_STAT_SWB (0x1 << 8)
1651 #define SDMA_ONCE_STAT_MST (0x1 << 7)
1652 #define SDMA_ONCE_STAT_ECDR (0x7 << 0)
1653 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRA_COND (0x1 << 0)
1654 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRB_COND (0x1 << 1)
1655 #define SDMA_ONCE_STAT_ECDR_MATCHED_DATA_COND (0x1 << 2)
1657 /* SDMA_ONCE_CMD */
1658 #define SDMA_ONCE_CMD_RSTATUS 0x0
1659 #define SDMA_ONCE_CMD_DMOV 0x1
1660 #define SDMA_ONCE_CMD_EXEC_ONCE 0x2
1661 #define SDMA_ONCE_CMD_RUN_CORE 0x3
1662 #define SDMA_ONCE_CMD_EXEC_CORE 0x4
1663 #define SDMA_ONCE_CMD_DEBUG_RQST 0x5
1664 #define SDMA_ONCE_CMD_RBUFFER 0x6
1665 /* 7-15 reserved */
1667 /* SDMA_CHN0ADDR */
1668 #define SDMA_CHN0ADDR_SMSZ (0x1 << 14)
1669 /* 13:0 = 0x0050 by default (std. boot code) */
1671 /* SDMA_EVT_MIRROR */
1672 #define SDMA_EVT_MIRROR_EVENTS(n) (0x1 << (n))
1674 /* SDMA_XTRIG_CONF1 */
1675 #define SDMA_XTRIG_CONF1_CNF3 (0x1 << 30)
1676 #define SDMA_XTRIG_CONF1_NUM3 (0x1f << 24)
1677 #define SDMA_XTRIG_CONF1_CNF2 (0x1 << 22)
1678 #define SDMA_XTRIG_CONF1_NUM2 (0x1f << 16)
1679 #define SDMA_XTRIG_CONF1_CNF1 (0x1 << 14)
1680 #define SDMA_XTRIG_CONF1_NUM1 (0x1f << 8)
1681 #define SDMA_XTRIG_CONF1_CNF0 (0x1 << 6)
1682 #define SDMA_XTRIG_CONF1_NUM0 (0x1f << 0)
1684 /* SDMA_XTRIG_CONF2 */
1685 #define SDMA_XTRIG_CONF2_CNF7 (0x1 << 30)
1686 #define SDMA_XTRIG_CONF2_NUM7 (0x1f << 24)
1687 #define SDMA_XTRIG_CONF2_CNF6 (0x1 << 22)
1688 #define SDMA_XTRIG_CONF2_NUM6 (0x1f << 16)
1689 #define SDMA_XTRIG_CONF2_CNF5 (0x1 << 14)
1690 #define SDMA_XTRIG_CONF2_NUM5 (0x1f << 8)
1691 #define SDMA_XTRIG_CONF2_CNF4 (0x1 << 6)
1692 #define SDMA_XTRIG_CONF2_NUM4 (0x1f << 0)
1694 /* SDMA_CHNENBL(n) */
1695 #define SDMA_CHNENBL_ENBL(n) (0x1 << (n))
1698 #define L2CC_ENABLED
1700 /* Assuming 26MHz input clock */
1701 /* PD MFD MFI MFN */
1702 #define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0))
1703 #define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0))
1704 #define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0))
1706 /* UPCTL PD MFD MFI MFN */
1707 #define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
1708 #define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
1710 /* PDR0 */
1711 #define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
1712 #define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
1713 #define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
1714 #define PDR0_532_133_66 0xFF871E58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1715 #define PDR0_665_83_66 0xFF873D78 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1716 #define PDR0_665_133_66 0xFF872660 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1718 #define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
1720 #define PBC_BSTAT2 0x2
1721 #define PBC_BCTRL1 0x4
1722 #define PBC_BCTRL1_CLR 0x6
1723 #define PBC_BCTRL2 0x8
1724 #define PBC_BCTRL2_CLR 0xA
1725 #define PBC_BCTRL3 0xC
1726 #define PBC_BCTRL3_CLR 0xE
1727 #define PBC_BCTRL4 0x10
1728 #define PBC_BCTRL4_CLR 0x12
1729 #define PBC_BSTAT1 0x14
1730 #define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
1731 #define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
1733 #define REDBOOT_IMAGE_SIZE 0x40000
1735 #define SDRAM_WORKAROUND_FULL_PAGE
1737 #define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/
1738 #define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/
1739 #define ARMHIPG_399_66_66
1740 #define ARMHIPG_399_133_66
1742 /* MX31 EVB SDRAM is from 0x80000000, 64M */
1743 #define SDRAM_BASE_ADDR CSD0_BASE_ADDR
1744 #define SDRAM_SIZE 0x04000000
1746 #define UART_WIDTH_32 /* internal UART is 32bit access only */
1747 #define EXT_UART_x16
1749 #define UART_WIDTH_32 /* internal UART is 32bit access only */
1751 #define FLASH_BURST_MODE_ENABLE 1
1752 #define SDRAM_COMPARE_CONST1 0x55555555
1753 #define SDRAM_COMPARE_CONST2 0xAAAAAAAA
1754 #define UART_FIFO_CTRL 0x881
1755 #define TIMEOUT 1000
1757 /* Timer frequency */
1758 /* timer is based on ipg_clk */
1759 #define TIMER_FREQ (66000000)
1761 #endif /* __IMX31L_H__ */