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eltan/security: Remove some preprocessor guards
2019-11-06
Xiang
W
a
n
g
lib: add calculate cr
c
byte by byte
Signed-off-by:
Xiang Wang
<merle@hardenedlinux.org>
commit
|
commitdiff
|
tree
2019-10-16
Xiang
Wang
soc/sifiv
e
/fu540: test
and fix c
o
de of
fu540 s
p
i
Signed-off-by:
Xiang Wang
<merle@hardenedlinux.org>
commit
|
commitdiff
|
tree
2019-08-12
Xia
n
g
W
ang
soc/sifive/fu
5
4
0
: a
d
d c
o
de f
o
r spi and
m
a
p
flas
h
to
.
.
.
Signed-off-by:
Xiang Wang
<merle@hardenedlinux.org>
commit
|
commitdiff
|
tree
2019-08-03
Xiang Wang
riscv: add support for Ope
n
S
B
I
Signed-off-by:
Xiang Wang
<merle@hardenedlinux.org>
commit
|
commitdiff
|
tree
2019-06-23
Xia
n
g Wang
r
iscv: wo
r
karoun
d
se
l
fboot putti
n
g the core
b
oo
t
table
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-06-23
X
i
a
n
g Wang
riscv: use mret to invok
e
M-mo
d
e payload and disable
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-06-23
Xiang
W
ang
riscv
:
Fix MENTRY_FRAME_SIZE to fit diffe
r
e
n
t machine
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-06-21
X
iang Wang
Documentatioa
n
: update
stage handoff p
r
otocol
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-03-28
Xiang
W
a
n
g
payload: Only
d
isplay `FIT support` on ARM64 p
l
atforms
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-03-18
X
iang Wang
s
r
c/mb/sifive
/
hifive-u
n
le
a
shed: i
n
iti
a
lize
Gigab
i
t
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-02-28
Xiang Wa
n
g
src/mb/sifive/hifive-unleashed: re
p
l
a
ce fdt
i
n m
a
skrom
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-02-02
Xiang Wang
riscv: Simplify payload handling
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-12-19
X
i
ang Wang
mb/s
i
five/hifive-unleas
h
e
d
: remov
e
t
he definition of
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-11-22
Xiang Wa
n
g
riscv: fi
x
bug of sifiv
e
-gp
t
.
p
y
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-11-05
Xiang
Wang
risc
v
: ad
d
support for superv
i
sor binary interface
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-11-05
Xiang Wang
r
i
scv: add su
p
p
o
rt to b
l
ock smp
i
n
each stage
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-11-05
Xiang
W
ang
r
iscv
:
add support
s
mp_pause / smp_resume
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-10-11
Xi
a
ng Wang
riscv: add physica
l
m
e
mory
p
rotection
(PMP
)
support
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-16
Xian
g
W
ang
riscv: don
'
t
w
rite to mstatus
.
XS
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-10
X
i
ang
W
ang
riscv: update mi
s
aligned memory access except
i
on ha
n
dling
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-10
Xiang Wang
soc/sifi
v
e
/fu5
4
0: add CLINT s
u
pport
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-10
Xiang Wang
riscv: update mt
i
me in
i
tia
l
ization
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-05
X
iang Wan
g
riscv:
a
d
d entry
a
s
sembl
y
fil
e
for RAMSTAGE
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-05
X
i
ang Wang
riscv:
add su
p
port t
o
check
machine leng
t
h at
r
u
nti
m
e
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-04
Xi
a
ng Wang
ris
c
v: add spin
lock
s
up
p
or
t
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-04
Xiang
W
a
n
g
riscv: A
d
d DE
F
I
N
E_MPRV
_
RE
A
D_MXR t
o
r
e
ad execution
-
onl
y
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-02
Xian
g
Wang
riscv: separa
t
ely define stac
k
locat
i
o
ns at
differen
t
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-08-30
Xiang
W
ang
r
iscv: update
t
h
e definit
i
on
of intptr_t/uintptr_t
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-08-11
Xiang Wang
util
/
lint: Remove register na
m
e identified as a misspelle
d
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-08-01
X
iang Wan
g
ris
c
v: r
e
mov
e
redundancy in
Makefile
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-07-31
Xiang
Wang
riscv: fix issues (timestrap &
P
R
Iu64)
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-07-30
Xiang Wang
riscv: delete
s
rc/arch/riscv/prologue
.
inc
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-07-18
Xian
g
Wan
g
r
i
s
cv
:
a
d
d CAR interface
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-07-17
X
ia
n
g Wang
ri
s
cv: add support
f
o
r modifyin
g
com
p
iler opti
o
ns
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-07-12
X
i
ang
Wan
g
riscv: add in
c
lude/arch/smp/ dir
e
cto
r
y
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-07-11
Xiang Wang
riscv:
a
dd su
p
port to c
h
eck ISA
extension
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-07-06
Xi
a
ng Wang
riscv: use __riscv_ato
m
ic to check
s
upport
A
extension
commit
|
commitdiff
|
tree