| commit | 22e0c560bb565642d52e4e0f8bab000c8d06f0b8 | |
| author | Xiang Wang <wxjstz@126.com> | |
| Wed, 15 Aug 2018 08:27:05 +0000 (15 16:27 +0800) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 5 Nov 2018 09:04:01 +0000 (5 09:04 +0000) | ||
| tree | a960e9bc01d3d4d9ddb65ba828b64d39a64baade | treesnapshot (tar.gz zip) |
| parent | 26f725efc235b282e20aa678f8e683a014920b71 | commitdiff |
riscv: add support for supervisor binary interface (SBI)
SBI is runtime service for OS. For an introduction, please refer to
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md
Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
SBI is runtime service for OS. For an introduction, please refer to
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md
Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| src/arch/riscv/Makefile.inc | diffblobblamehistory | |
| src/arch/riscv/include/sbi.h | [new file with mode: 0644] | blob |
| src/arch/riscv/include/vm.h | diffblobblamehistory | |
| src/arch/riscv/sbi.c | [new file with mode: 0644] | blob |
| src/arch/riscv/trap_handler.c | diffblobblamehistory |