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soc/intel/apollolake: Improve cold boot and S3 resume
2018-11-05
Xiang Wang
riscv: add su
p
por
t
f
o
r s
u
pe
r
v
i
sor binary inte
r
face
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
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commitdiff
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tree
2018-11-05
Xi
a
ng Wang
r
i
s
cv: add
support to
b
lock smp in each stage
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
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commitdiff
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tree
2018-11-05
Xiang Wan
g
riscv:
add supp
o
rt smp_pause / sm
p
_resume
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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commitdiff
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tree
2018-10-11
Xian
g
Wang
ris
c
v: add physic
a
l memory protec
t
ion (PMP) suppor
t
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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tree
2018-09-16
Xiang Wang
riscv: don't write
t
o mstatus
.
XS
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
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commitdiff
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tree
2018-09-10
Xiang Wang
ri
s
cv: update mis
a
ligned me
m
ory access exception handling
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2018-09-10
X
i
ang Wang
soc/
s
ifive/fu54
0
: add CLIN
T
sup
p
ort
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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tree
2018-09-10
Xiang Wang
riscv: update mtime in
i
tializa
t
ion
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2018-09-05
Xia
n
g
W
ang
risc
v
: add en
t
ry assembly file for RAMSTAGE
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2018-09-05
X
ian
g
W
a
ng
r
i
sc
v
: add suppo
r
t
t
o che
c
k ma
c
hine length
a
t runti
m
e
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-04
X
iang Wang
riscv: add spin lock support
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2018-09-04
Xiang Wang
riscv: Add DEFINE_
M
PRV_READ_MXR to
r
ea
d
execut
i
on-only
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2018-09-02
Xiang
Wang
ri
s
cv:
separa
t
ely
define stack
l
ocatio
n
s at different
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-08-30
X
ian
g
Wang
ri
s
cv:
update the definition of
intptr_t/u
i
ntptr_t
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2018-08-11
Xiang Wang
util/lint: Remo
v
e re
g
ister name identifi
e
d as a mi
s
spelled
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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tree
2018-08-01
Xiang Wan
g
r
i
scv:
r
emove redundancy in Makefile
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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|
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tree
2018-07-31
Xiang Wang
risc
v
:
f
i
x issues (timestrap & PRIu64)
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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|
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tree
2018-07-30
Xiang Wang
riscv:
d
elete
s
rc
/
arch/riscv/prologu
e
.
inc
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
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tree
2018-07-18
Xiang
Wang
r
i
s
c
v: add CA
R
interface
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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2018-07-17
Xiang Wang
ri
s
cv: add support for mod
i
fying compiler
o
ptions
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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2018-07-12
Xi
a
ng Wang
ri
s
cv: add i
n
c
l
ude/arch/sm
p
/
d
i
rectory
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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2018-07-11
Xiang Wang
riscv: add suppor
t
to check ISA extension
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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tree
2018-07-06
Xiang Wang
risc
v
: use _
_
riscv_atomic
to chec
k
suppo
r
t A extension
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