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util/abuild: Clean up the missing_arches check
2019-08-03
Xiang Wan
g
riscv: add supp
o
r
t for O
p
enSB
I
Signed-off-by:
Xiang Wang
<merle@hardenedlinux.org>
commit
|
commitdiff
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tree
2019-06-23
X
ian
g
Wang
r
i
s
cv:
w
orkaround selfboot
putti
n
g t
h
e core
b
oot table
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2019-06-23
Xiang Wang
riscv
:
use mret to invoke M-mod
e
payload
a
nd
d
i
sab
l
e
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2019-06-23
Xiang Wang
riscv: F
i
x MEN
T
RY_
F
RAME_SIZE to fit diff
e
rent machine
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2019-06-21
Xiang Wa
n
g
Documentatioan: update stage
handoff protoc
o
l
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2019-03-28
Xiang Wang
payload:
On
l
y
d
ispl
a
y `FIT support` on ARM
6
4
platforms
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-03-18
X
i
ang Wang
src/mb/sifive/hifive-unle
a
shed: initialize Gigabi
t
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-02-28
Xiang Wa
n
g
src/m
b
/sifive/hifive-
u
nleash
e
d: r
e
place f
d
t
in mas
k
rom
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2019-02-02
Xiang
Wang
ri
s
c
v
: Simplify
p
a
y
load handl
i
ng
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-12-19
Xia
n
g Wang
mb/sifive/hifive
-
unleashed:
remove the defin
i
tion of
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-11-22
Xiang Wang
riscv: fix bug of sif
i
ve-gpt
.
py
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-11-05
Xiang Wang
riscv
:
add support for supervisor binary i
n
terface
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-11-05
Xiang Wang
riscv: add
s
upport to block sm
p
in each stage
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-11-05
Xian
g
W
a
ng
riscv
:
a
d
d
s
upport smp_pause / smp_resume
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-10-11
Xiang Wang
ris
c
v
: add physica
l
memory p
r
otection (PMP) support
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-16
Xiang Wang
riscv: d
o
n't write to mstatus
.
XS
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-10
Xiang W
a
ng
riscv: update misal
i
g
n
ed memory acc
e
ss e
x
c
e
ption handling
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-10
Xiang Wang
soc/s
i
f
ive/fu540: add
CLINT
support
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-10
Xian
g
Wang
ri
s
cv: u
p
date mtime initialization
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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|
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tree
2018-09-05
Xiang
W
a
n
g
r
i
scv: add entry
a
s
s
e
m
bly fi
l
e
for
RAMSTAGE
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
|
tree
2018-09-05
X
iang
W
ang
riscv: a
d
d
supp
o
rt to c
h
eck machine length
at ru
n
time
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
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tree
2018-09-04
X
i
a
ng Wang
riscv: add
spin lock support
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
commitdiff
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tree
2018-09-04
Xiang Wang
r
i
scv: Add D
E
FINE_MPRV_READ_MXR t
o
r
e
a
d
e
xecuti
o
n
-
only
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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|
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|
tree
2018-09-02
X
iang Wang
riscv: separately define stac
k
l
o
cations
at different
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
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tree
2018-08-30
Xiang Wang
riscv:
updat
e
the
d
efinition of intptr_t/uintptr_t
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
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|
tree
2018-08-11
Xian
g
Wang
u
t
il/lint: Re
m
ove reg
i
s
t
er
na
m
e identified
a
s a misspelled
.
.
.
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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|
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2018-08-01
Xi
a
ng Wang
riscv: remove red
u
ndancy in
Makefile
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
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|
tree
2018-07-31
Xiang
Wang
r
iscv: fix is
s
ues (time
s
trap & PRI
u
6
4
)
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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|
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tree
2018-07-30
Xiang Wang
riscv
:
delete src/arch/risc
v
/prologue
.
inc
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
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tree
2018-07-18
Xiang Wa
n
g
riscv: add CAR in
t
e
r
fa
c
e
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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|
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tree
2018-07-17
Xiang Wang
riscv: add support fo
r
m
o
dify
i
ng co
m
piler options
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
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|
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2018-07-12
Xiang Wang
riscv:
add include/arch/smp
/
directory
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
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tree
2018-07-11
Xi
a
ng Wang
r
i
sc
v
: add support to ch
e
ck ISA
ex
t
e
n
sion
Signed-off-by:
Xiang Wang
<wxjstz@126.com>
commit
|
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|
tree
2018-07-06
Xiang W
a
ng
ris
c
v: use __riscv_ato
m
ic to chec
k
suppor
t
A
e
x
tens
i
on
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|
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