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avr: Fix documentation for Bus
[avr-sim.git] / src / Decoder.cpp
blobb7d16364a123f17fd2ccd0b4b3d26485bc9b08f8
1 /*
2 * avr-sim: An atmel AVR simulator
3 * Copyright (C) 2008 Tom Haber
4 *
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "Decoder.h"
20 #include "Instructions.h"
21 #include "DecoderHelp.h"
22
23 namespace avr {
24
25 std::vector<Instruction *> Decoder::lut;
26
27 Decoder::Decoder() {
28 if( lut.size() == 0 ) {
29 const unsigned int num_ops = 0x10000;
30 lut.resize( num_ops );
31 for(unsigned int i = 0; i < num_ops; i++) {
32 lut[i] = lookupOpcode(i);
33 }
34 }
35 }
36
37 bool Decoder::is2WordInstruction( word opcode ) const {
38 return lut[opcode]->is2Word();
39 }
40
41 Instruction * Decoder::lookupOpcode( word opcode ) {
42 int decode;
43
44 switch( opcode ) {
45 /* opcodes with no operands */
46 case 0x9519: return new op::EICALL(opcode); /* 1001 0101 0001 1001 | EICALL */
47 case 0x9419: return new op::EIJMP(opcode); /* 1001 0100 0001 1001 | EIJMP */
48 case 0x95D8: return new op::ELPM(opcode); /* 1001 0101 1101 1000 | ELPM */
49 case 0x95F8: return new op::ESPM(opcode); /* 1001 0101 1111 1000 | ESPM */
50 case 0x9509: return new op::ICALL(opcode); /* 1001 0101 0000 1001 | ICALL */
51 case 0x9409: return new op::IJMP(opcode); /* 1001 0100 0000 1001 | IJMP */
52 case 0x95C8: return new op::LPM(opcode); /* 1001 0101 1100 1000 | LPM */
53 case 0x0000: return new op::NOP(opcode); /* 0000 0000 0000 0000 | NOP */
54 case 0x9508: return new op::RET(opcode); /* 1001 0101 0000 1000 | RET */
55 case 0x9518: return new op::RETI(opcode); /* 1001 0101 0001 1000 | RETI */
56 case 0x9588: return new op::SLEEP(opcode); /* 1001 0101 1000 1000 | SLEEP */
57 case 0x95E8: return new op::SPM(opcode); /* 1001 0101 1110 1000 | SPM */
58 case 0x95A8: return new op::WDR(opcode); /* 1001 0101 1010 1000 | WDR */
59 case 0x9598: return new op::BREAK(opcode); /* 1001 0101 1001 1000 | BREAK */
60 default: {
61 /* opcodes with two 5-bit register (Rd and Rr) operands */
62 decode = opcode & ~(mask_Rd_5 | mask_Rr_5);
63 switch ( decode ) {
64 case 0x1C00: return new op::ADC(opcode); /* 0001 11rd dddd rrrr | ADC or ROL */
65
66 case 0x0C00: return new op::ADD(opcode); /* 0000 11rd dddd rrrr | ADD or LSL */
67 case 0x2000: return new op::AND(opcode); /* 0010 00rd dddd rrrr | AND or TST */
68 case 0x1400: return new op::CP(opcode); /* 0001 01rd dddd rrrr | CP */
69 case 0x0400: return new op::CPC(opcode); /* 0000 01rd dddd rrrr | CPC */
70 case 0x1000: return new op::CPSE(opcode); /* 0001 00rd dddd rrrr | CPSE */
71 case 0x2400: return new op::EOR(opcode); /* 0010 01rd dddd rrrr | EOR or CLR */
72 case 0x2C00: return new op::MOV(opcode); /* 0010 11rd dddd rrrr | MOV */
73 case 0x9C00: return new op::MUL(opcode); /* 1001 11rd dddd rrrr | MUL */
74 case 0x2800: return new op::OR(opcode); /* 0010 10rd dddd rrrr | OR */
75 case 0x0800: return new op::SBC(opcode); /* 0000 10rd dddd rrrr | SBC */
76 case 0x1800: return new op::SUB(opcode); /* 0001 10rd dddd rrrr | SUB */
77 }
78
79 /* opcode with a single register (Rd) as operand */
80 decode = opcode & ~(mask_Rd_5);
81 switch (decode) {
82 case 0x9405: return new op::ASR(opcode); /* 1001 010d dddd 0101 | ASR */
83 case 0x9400: return new op::COM(opcode); /* 1001 010d dddd 0000 | COM */
84 case 0x940A: return new op::DEC(opcode); /* 1001 010d dddd 1010 | DEC */
85 case 0x9006: return new op::ELPM_Z(opcode); /* 1001 000d dddd 0110 | ELPM */
86 case 0x9007: return new op::ELPM_Z_incr(opcode); /* 1001 000d dddd 0111 | ELPM */
87 case 0x9403: return new op::INC(opcode); /* 1001 010d dddd 0011 | INC */
88 case 0x9000: return new op::LDS(opcode); /* 1001 000d dddd 0000 | LDS */
89 case 0x900C: return new op::LD_X(opcode); /* 1001 000d dddd 1100 | LD */
90 case 0x900E: return new op::LD_X_decr(opcode); /* 1001 000d dddd 1110 | LD */
91 case 0x900D: return new op::LD_X_incr(opcode); /* 1001 000d dddd 1101 | LD */
92 case 0x900A: return new op::LD_Y_decr(opcode); /* 1001 000d dddd 1010 | LD */
93 case 0x9009: return new op::LD_Y_incr(opcode); /* 1001 000d dddd 1001 | LD */
94 case 0x9002: return new op::LD_Z_decr(opcode); /* 1001 000d dddd 0010 | LD */
95 case 0x9001: return new op::LD_Z_incr(opcode); /* 1001 000d dddd 0001 | LD */
96 case 0x9004: return new op::LPM_Z(opcode); /* 1001 000d dddd 0100 | LPM */
97 case 0x9005: return new op::LPM_Z_incr(opcode); /* 1001 000d dddd 0101 | LPM */
98 case 0x9406: return new op::LSR(opcode); /* 1001 010d dddd 0110 | LSR */
99 case 0x9401: return new op::NEG(opcode); /* 1001 010d dddd 0001 | NEG */
100 case 0x900F: return new op::POP(opcode); /* 1001 000d dddd 1111 | POP */
101 case 0x920F: return new op::PUSH(opcode); /* 1001 001d dddd 1111 | PUSH */
102 case 0x9407: return new op::ROR(opcode); /* 1001 010d dddd 0111 | ROR */
103 case 0x9200: return new op::STS(opcode); /* 1001 001d dddd 0000 | STS */
104 case 0x920C: return new op::ST_X(opcode); /* 1001 001d dddd 1100 | ST */
105 case 0x920E: return new op::ST_X_decr(opcode); /* 1001 001d dddd 1110 | ST */
106 case 0x920D: return new op::ST_X_incr(opcode); /* 1001 001d dddd 1101 | ST */
107 case 0x920A: return new op::ST_Y_decr(opcode); /* 1001 001d dddd 1010 | ST */
108 case 0x9209: return new op::ST_Y_incr(opcode); /* 1001 001d dddd 1001 | ST */
109 case 0x9202: return new op::ST_Z_decr(opcode); /* 1001 001d dddd 0010 | ST */
110 case 0x9201: return new op::ST_Z_incr(opcode); /* 1001 001d dddd 0001 | ST */
111 case 0x9402: return new op::SWAP(opcode); /* 1001 010d dddd 0010 | SWAP */
112 }
113
114 /* opcodes with a register (Rd) and a constant data (K) as operands */
115 decode = opcode & ~(mask_Rd_4 | mask_K_8);
116 switch ( decode ) {
117 case 0x7000: return new op::ANDI(opcode); /* 0111 KKKK dddd KKKK | CBR or ANDI */
118 case 0x3000: return new op::CPI(opcode); /* 0011 KKKK dddd KKKK | CPI */
119 case 0xE000: return new op::LDI(opcode); /* 1110 KKKK dddd KKKK | LDI or SER */
120 case 0x6000: return new op::ORI(opcode); /* 0110 KKKK dddd KKKK | SBR or ORI */
121 case 0x4000: return new op::SBCI(opcode); /* 0100 KKKK dddd KKKK | SBCI */
122 case 0x5000: return new op::SUBI(opcode); /* 0101 KKKK dddd KKKK | SUBI */
123 }
124
125 /* opcodes with a register (Rd) and a register bit number (b) as operands */
126 decode = opcode & ~(mask_Rd_5 | mask_reg_bit);
127 switch ( decode ) {
128 case 0xF800: return new op::BLD(opcode); /* 1111 100d dddd 0bbb | BLD */
129 case 0xFA00: return new op::BST(opcode); /* 1111 101d dddd 0bbb | BST */
130 case 0xFC00: return new op::SBRC(opcode); /* 1111 110d dddd 0bbb | SBRC */
131 case 0xFE00: return new op::SBRS(opcode); /* 1111 111d dddd 0bbb | SBRS */
132 }
133
134 /* opcodes with a relative 7-bit address (k) and a register bit number (b) as operands */
135 decode = opcode & ~(mask_k_7 | mask_reg_bit);
136 switch ( decode ) {
137 case 0xF400: return new op::BRBC(opcode); /* 1111 01kk kkkk kbbb | BRBC */
138 case 0xF000: return new op::BRBS(opcode); /* 1111 00kk kkkk kbbb | BRBS */
139 }
140
141 /* opcodes with a 6-bit address displacement (q) and a register (Rd) as operands */
142 decode = opcode & ~(mask_Rd_5 | mask_q_displ);
143 switch ( decode ) {
144 case 0x8008: return new op::LDD_Y(opcode); /* 10q0 qq0d dddd 1qqq | LDD */
145 case 0x8000: return new op::LDD_Z(opcode); /* 10q0 qq0d dddd 0qqq | LDD */
146 case 0x8208: return new op::STD_Y(opcode); /* 10q0 qq1d dddd 1qqq | STD */
147 case 0x8200: return new op::STD_Z(opcode); /* 10q0 qq1d dddd 0qqq | STD */
148 }
149
150 /* opcodes with a absolute 22-bit address (k) operand */
151 decode = opcode & ~(mask_k_22);
152 switch ( decode ) {
153 case 0x940E: return new op::CALL(opcode); /* 1001 010k kkkk 111k | CALL */
154 case 0x940C: return new op::JMP(opcode); /* 1001 010k kkkk 110k | JMP */
155 }
156
157 /* opcode with a sreg bit select (s) operand */
158 decode = opcode & ~(mask_sreg_bit);
159 switch ( decode ) {
160 /* BCLR takes place of CL{C,Z,N,V,S,H,T,I} */
161 /* BSET takes place of SE{C,Z,N,V,S,H,T,I} */
162 case 0x9488: return new op::BCLR(opcode); /* 1001 0100 1sss 1000 | BCLR */
163 case 0x9408: return new op::BSET(opcode); /* 1001 0100 0sss 1000 | BSET */
164 }
165
166 /* opcodes with a 6-bit constant (K) and a register (Rd) as operands */
167 decode = opcode & ~(mask_K_6 | mask_Rd_2);
168 switch ( decode ) {
169 case 0x9600: return new op::ADIW(opcode); /* 1001 0110 KKdd KKKK | ADIW */
170 case 0x9700: return new op::SBIW(opcode); /* 1001 0111 KKdd KKKK | SBIW */
171 }
172
173 /* opcodes with a 5-bit IO Addr (A) and register bit number (b) as operands */
174 decode = opcode & ~(mask_A_5 | mask_reg_bit);
175 switch ( decode ) {
176 case 0x9800: return new op::CBI(opcode); /* 1001 1000 AAAA Abbb | CBI */
177 case 0x9A00: return new op::SBI(opcode); /* 1001 1010 AAAA Abbb | SBI */
178 case 0x9900: return new op::SBIC(opcode); /* 1001 1001 AAAA Abbb | SBIC */
179 case 0x9B00: return new op::SBIS(opcode); /* 1001 1011 AAAA Abbb | SBIS */
180 }
181
182 /* opcodes with a 6-bit IO Addr (A) and register (Rd) as operands */
183 decode = opcode & ~(mask_A_6 | mask_Rd_5);
184 switch ( decode ) {
185 case 0xB000: return new op::IN(opcode); /* 1011 0AAd dddd AAAA | IN */
186 case 0xB800: return new op::OUT(opcode); /* 1011 1AAd dddd AAAA | OUT */
187 }
188
189 /* opcodes with a relative 12-bit address (k) operand */
190 decode = opcode & ~(mask_k_12);
191 switch ( decode ) {
192 case 0xD000: return new op::RCALL(opcode); /* 1101 kkkk kkkk kkkk | RCALL */
193 case 0xC000: return new op::RJMP(opcode); /* 1100 kkkk kkkk kkkk | RJMP */
194 }
195
196 /* opcodes with two 4-bit register (Rd and Rr) operands */
197 decode = opcode & ~(mask_Rd_4 | mask_Rr_4);
198 switch ( decode ) {
199 case 0x0100: return new op::MOVW(opcode); /* 0000 0001 dddd rrrr | MOVW */
200 case 0x0200: return new op::MULS(opcode); /* 0000 0010 dddd rrrr | MULS */
201 }
202
203 /* opcodes with two 3-bit register (Rd and Rr) operands */
204 decode = opcode & ~(mask_Rd_3 | mask_Rr_3);
205 switch ( decode ) {
206 case 0x0300: return new op::MULSU(opcode); /* 0000 0011 0ddd 0rrr | MULSU */
207 case 0x0308: return new op::FMUL(opcode); /* 0000 0011 0ddd 1rrr | FMUL */
208 case 0x0380: return new op::FMULS(opcode); /* 0000 0011 1ddd 0rrr | FMULS */
209 case 0x0388: return new op::FMULSU(opcode); /* 0000 0011 1ddd 1rrr | FMULSU */
210 }
211
212 } /* default */
213 } /* first switch */
214
215 //return NULL;
216 return new op::ILLEGAL(opcode);
217 }
218 }
Atmel AVR simulator