src/Decoder.cpp

   1 /*
   2  *      avr-sim: An atmel AVR simulator
   3  *  Copyright (C) 2008  Tom Haber
   4  *
   5  *  This program is free software: you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation, either version 3 of the License, or
   8  *  (at your option) any later version.
   9
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "Decoder.h"
  20 #include "Instructions.h"
  21 #include "DecoderHelp.h"
  22
  23 namespace avr {
  24
  25         Decoder::Decoder() {
  26                 const size_t num_ops = 0x10000;
  27                 lut.resize( num_ops );
  28                 for(size_t i = 0; i < num_ops; i++) {
  29                         lut[i] = lookupOpcode(i);
  30                 }
  31         }
  32
  33         Decoder::~Decoder() {
  34                 for(size_t i = 0; i < lut.size(); i++)
  35                         delete lut[i];
  36                 lut.clear();
  37         }
  38
  39         bool Decoder::is2WordInstruction( word opcode ) const {
  40                 return lut[opcode]->is2Word();
  41         }
  42
  43         Instruction * Decoder::lookupOpcode( word opcode ) {
  44             int decode;
  45
  46             switch( opcode ) {
  47                 /* opcodes with no operands */
  48                 case 0x9519: return new  op::EICALL(opcode);              /* 1001 0101 0001 1001 | EICALL */
  49                 case 0x9419: return new  op::EIJMP(opcode);               /* 1001 0100 0001 1001 | EIJMP */
  50                 case 0x95D8: return new  op::ELPM(opcode);                /* 1001 0101 1101 1000 | ELPM */
  51                 case 0x95F8: return new  op::ESPM(opcode);                /* 1001 0101 1111 1000 | ESPM */
  52                 case 0x9509: return new  op::ICALL(opcode);               /* 1001 0101 0000 1001 | ICALL */
  53                 case 0x9409: return new  op::IJMP(opcode);                /* 1001 0100 0000 1001 | IJMP */
  54                 case 0x95C8: return new  op::LPM(opcode);                 /* 1001 0101 1100 1000 | LPM */
  55                 case 0x0000: return new  op::NOP(opcode);                 /* 0000 0000 0000 0000 | NOP */
  56                 case 0x9508: return new  op::RET(opcode);                 /* 1001 0101 0000 1000 | RET */
  57                 case 0x9518: return new  op::RETI(opcode);                /* 1001 0101 0001 1000 | RETI */
  58                 case 0x9588: return new  op::SLEEP(opcode);               /* 1001 0101 1000 1000 | SLEEP */
  59                 case 0x95E8: return new  op::SPM(opcode);                 /* 1001 0101 1110 1000 | SPM */
  60                 case 0x95A8: return new  op::WDR(opcode);                 /* 1001 0101 1010 1000 | WDR */
  61                 case 0x9598: return new  op::BREAK(opcode);                             /* 1001 0101 1001 1000 | BREAK */
  62                 default: {
  63                  /* opcodes with two 5-bit register (Rd and Rr) operands */
  64                  decode = opcode & ~(mask_Rd_5 | mask_Rr_5);
  65                  switch ( decode ) {
  66                      case 0x1C00: return new  op::ADC(opcode);         /* 0001 11rd dddd rrrr | ADC or ROL */
  67
  68                      case 0x0C00: return new  op::ADD(opcode);         /* 0000 11rd dddd rrrr | ADD or LSL */
  69                      case 0x2000: return new  op::AND(opcode);         /* 0010 00rd dddd rrrr | AND or TST */
  70                      case 0x1400: return new  op::CP(opcode);          /* 0001 01rd dddd rrrr | CP */
  71                      case 0x0400: return new  op::CPC(opcode);         /* 0000 01rd dddd rrrr | CPC */
  72                      case 0x1000: return new  op::CPSE(opcode);        /* 0001 00rd dddd rrrr | CPSE */
  73                      case 0x2400: return new  op::EOR(opcode);         /* 0010 01rd dddd rrrr | EOR or CLR */
  74                      case 0x2C00: return new  op::MOV(opcode);         /* 0010 11rd dddd rrrr | MOV */
  75                      case 0x9C00: return new  op::MUL(opcode);         /* 1001 11rd dddd rrrr | MUL */
  76                      case 0x2800: return new  op::OR(opcode);          /* 0010 10rd dddd rrrr | OR */
  77                      case 0x0800: return new  op::SBC(opcode);         /* 0000 10rd dddd rrrr | SBC */
  78                      case 0x1800: return new  op::SUB(opcode);         /* 0001 10rd dddd rrrr | SUB */
  79                  }
  80
  81                  /* opcode with a single register (Rd) as operand */
  82                  decode = opcode & ~(mask_Rd_5);
  83                  switch (decode) {
  84                      case 0x9405: return new  op::ASR(opcode);         /* 1001 010d dddd 0101 | ASR */
  85                      case 0x9400: return new  op::COM(opcode);         /* 1001 010d dddd 0000 | COM */
  86                      case 0x940A: return new  op::DEC(opcode);         /* 1001 010d dddd 1010 | DEC */
  87                      case 0x9006: return new  op::ELPM_Z(opcode);      /* 1001 000d dddd 0110 | ELPM */
  88                      case 0x9007: return new  op::ELPM_Z_incr(opcode); /* 1001 000d dddd 0111 | ELPM */
  89                      case 0x9403: return new  op::INC(opcode);         /* 1001 010d dddd 0011 | INC */
  90                      case 0x9000: return new  op::LDS(opcode);         /* 1001 000d dddd 0000 | LDS */
  91                      case 0x900C: return new  op::LD_X(opcode);        /* 1001 000d dddd 1100 | LD */
  92                      case 0x900E: return new  op::LD_X_decr(opcode);   /* 1001 000d dddd 1110 | LD */
  93                      case 0x900D: return new  op::LD_X_incr(opcode);   /* 1001 000d dddd 1101 | LD */
  94                      case 0x900A: return new  op::LD_Y_decr(opcode);   /* 1001 000d dddd 1010 | LD */
  95                      case 0x9009: return new  op::LD_Y_incr(opcode);   /* 1001 000d dddd 1001 | LD */
  96                      case 0x9002: return new  op::LD_Z_decr(opcode);   /* 1001 000d dddd 0010 | LD */
  97                      case 0x9001: return new  op::LD_Z_incr(opcode);   /* 1001 000d dddd 0001 | LD */
  98                      case 0x9004: return new  op::LPM_Z(opcode);       /* 1001 000d dddd 0100 | LPM */
  99                      case 0x9005: return new  op::LPM_Z_incr(opcode);  /* 1001 000d dddd 0101 | LPM */
 100                      case 0x9406: return new  op::LSR(opcode);         /* 1001 010d dddd 0110 | LSR */
 101                      case 0x9401: return new  op::NEG(opcode);         /* 1001 010d dddd 0001 | NEG */
 102                      case 0x900F: return new  op::POP(opcode);         /* 1001 000d dddd 1111 | POP */
 103                      case 0x920F: return new  op::PUSH(opcode);        /* 1001 001d dddd 1111 | PUSH */
 104                      case 0x9407: return new  op::ROR(opcode);         /* 1001 010d dddd 0111 | ROR */
 105                      case 0x9200: return new  op::STS(opcode);         /* 1001 001d dddd 0000 | STS */
 106                      case 0x920C: return new  op::ST_X(opcode);        /* 1001 001d dddd 1100 | ST */
 107                      case 0x920E: return new  op::ST_X_decr(opcode);   /* 1001 001d dddd 1110 | ST */
 108                      case 0x920D: return new  op::ST_X_incr(opcode);   /* 1001 001d dddd 1101 | ST */
 109                      case 0x920A: return new  op::ST_Y_decr(opcode);   /* 1001 001d dddd 1010 | ST */
 110                      case 0x9209: return new  op::ST_Y_incr(opcode);   /* 1001 001d dddd 1001 | ST */
 111                      case 0x9202: return new  op::ST_Z_decr(opcode);   /* 1001 001d dddd 0010 | ST */
 112                      case 0x9201: return new  op::ST_Z_incr(opcode);   /* 1001 001d dddd 0001 | ST */
 113                      case 0x9402: return new  op::SWAP(opcode);        /* 1001 010d dddd 0010 | SWAP */
 114                  }
 115
 116                  /* opcodes with a register (Rd) and a constant data (K) as operands */
 117                  decode = opcode & ~(mask_Rd_4 | mask_K_8);
 118                  switch ( decode ) {
 119                      case 0x7000: return new  op::ANDI(opcode);        /* 0111 KKKK dddd KKKK | CBR or ANDI */
 120                      case 0x3000: return new  op::CPI(opcode);         /* 0011 KKKK dddd KKKK | CPI */
 121                      case 0xE000: return new  op::LDI(opcode);         /* 1110 KKKK dddd KKKK | LDI or SER */
 122                      case 0x6000: return new  op::ORI(opcode);         /* 0110 KKKK dddd KKKK | SBR or ORI */
 123                      case 0x4000: return new  op::SBCI(opcode);        /* 0100 KKKK dddd KKKK | SBCI */
 124                      case 0x5000: return new  op::SUBI(opcode);        /* 0101 KKKK dddd KKKK | SUBI */
 125                  }
 126
 127                  /* opcodes with a register (Rd) and a register bit number (b) as operands */
 128                  decode = opcode & ~(mask_Rd_5 | mask_reg_bit);
 129                  switch ( decode ) {
 130                      case 0xF800: return new  op::BLD(opcode);         /* 1111 100d dddd 0bbb | BLD */
 131                      case 0xFA00: return new  op::BST(opcode);         /* 1111 101d dddd 0bbb | BST */
 132                      case 0xFC00: return new  op::SBRC(opcode);        /* 1111 110d dddd 0bbb | SBRC */
 133                      case 0xFE00: return new  op::SBRS(opcode);        /* 1111 111d dddd 0bbb | SBRS */
 134                  }
 135
 136                  /* opcodes with a relative 7-bit address (k) and a register bit number (b) as operands */
 137                  decode = opcode & ~(mask_k_7 | mask_reg_bit);
 138                  switch ( decode ) {
 139                      case 0xF400: return new  op::BRBC(opcode);        /* 1111 01kk kkkk kbbb | BRBC */
 140                      case 0xF000: return new  op::BRBS(opcode);        /* 1111 00kk kkkk kbbb | BRBS */
 141                  }
 142
 143                  /* opcodes with a 6-bit address displacement (q) and a register (Rd) as operands */
 144                  decode = opcode & ~(mask_Rd_5 | mask_q_displ);
 145                  switch ( decode ) {
 146                      case 0x8008: return new  op::LDD_Y(opcode);       /* 10q0 qq0d dddd 1qqq | LDD */
 147                      case 0x8000: return new  op::LDD_Z(opcode);       /* 10q0 qq0d dddd 0qqq | LDD */
 148                      case 0x8208: return new  op::STD_Y(opcode);       /* 10q0 qq1d dddd 1qqq | STD */
 149                      case 0x8200: return new  op::STD_Z(opcode);       /* 10q0 qq1d dddd 0qqq | STD */
 150                  }
 151
 152                  /* opcodes with a absolute 22-bit address (k) operand */
 153                  decode = opcode & ~(mask_k_22);
 154                  switch ( decode ) {
 155                      case 0x940E: return new  op::CALL(opcode);        /* 1001 010k kkkk 111k | CALL */
 156                      case 0x940C: return new  op::JMP(opcode);         /* 1001 010k kkkk 110k | JMP */
 157                  }
 158
 159                  /* opcode with a sreg bit select (s) operand */
 160                  decode = opcode & ~(mask_sreg_bit);
 161                  switch ( decode ) {
 162                      /* BCLR takes place of CL{C,Z,N,V,S,H,T,I} */
 163                      /* BSET takes place of SE{C,Z,N,V,S,H,T,I} */
 164                      case 0x9488: return new  op::BCLR(opcode);        /* 1001 0100 1sss 1000 | BCLR */
 165                      case 0x9408: return new  op::BSET(opcode);        /* 1001 0100 0sss 1000 | BSET */
 166                  }
 167
 168                  /* opcodes with a 6-bit constant (K) and a register (Rd) as operands */
 169                  decode = opcode & ~(mask_K_6 | mask_Rd_2);
 170                  switch ( decode ) {
 171                      case 0x9600: return new  op::ADIW(opcode);        /* 1001 0110 KKdd KKKK | ADIW */
 172                      case 0x9700: return new  op::SBIW(opcode);        /* 1001 0111 KKdd KKKK | SBIW */
 173                  }
 174
 175                  /* opcodes with a 5-bit IO Addr (A) and register bit number (b) as operands */
 176                  decode = opcode & ~(mask_A_5 | mask_reg_bit);
 177                  switch ( decode ) {
 178                      case 0x9800: return new  op::CBI(opcode);         /* 1001 1000 AAAA Abbb | CBI */
 179                      case 0x9A00: return new  op::SBI(opcode);         /* 1001 1010 AAAA Abbb | SBI */
 180                      case 0x9900: return new  op::SBIC(opcode);        /* 1001 1001 AAAA Abbb | SBIC */
 181                      case 0x9B00: return new  op::SBIS(opcode);        /* 1001 1011 AAAA Abbb | SBIS */
 182                  }
 183
 184                  /* opcodes with a 6-bit IO Addr (A) and register (Rd) as operands */
 185                  decode = opcode & ~(mask_A_6 | mask_Rd_5);
 186                  switch ( decode ) {
 187                      case 0xB000: return new  op::IN(opcode);          /* 1011 0AAd dddd AAAA | IN */
 188                      case 0xB800: return new  op::OUT(opcode);         /* 1011 1AAd dddd AAAA | OUT */
 189                  }
 190
 191                  /* opcodes with a relative 12-bit address (k) operand */
 192                  decode = opcode & ~(mask_k_12);
 193                  switch ( decode ) {
 194                      case 0xD000: return new  op::RCALL(opcode);       /* 1101 kkkk kkkk kkkk | RCALL */
 195                      case 0xC000: return new  op::RJMP(opcode);        /* 1100 kkkk kkkk kkkk | RJMP */
 196                  }
 197
 198                  /* opcodes with two 4-bit register (Rd and Rr) operands */
 199                  decode = opcode & ~(mask_Rd_4 | mask_Rr_4);
 200                  switch ( decode ) {
 201                      case 0x0100: return new  op::MOVW(opcode);        /* 0000 0001 dddd rrrr | MOVW */
 202                      case 0x0200: return new  op::MULS(opcode);        /* 0000 0010 dddd rrrr | MULS */
 203                  }
 204
 205                  /* opcodes with two 3-bit register (Rd and Rr) operands */
 206                  decode = opcode & ~(mask_Rd_3 | mask_Rr_3);
 207                  switch ( decode ) {
 208                      case 0x0300: return new  op::MULSU(opcode);       /* 0000 0011 0ddd 0rrr | MULSU */
 209                      case 0x0308: return new  op::FMUL(opcode);        /* 0000 0011 0ddd 1rrr | FMUL */
 210                      case 0x0380: return new  op::FMULS(opcode);       /* 0000 0011 1ddd 0rrr | FMULS */
 211                      case 0x0388: return new  op::FMULSU(opcode);      /* 0000 0011 1ddd 1rrr | FMULSU */
 212                  }
 213
 214              } /* default */
 215             } /* first switch */
 216
 217             //return NULL;
 218             return new op::ILLEGAL(opcode);
 219         }
 220 }