descriptionuart16550 core
homepage URLhttp://www.opencores.org
ownerricky.nite@gmail.com
last changeMon, 22 Nov 2004 09:21:59 +0000 (22 09:21 +0000)
content tags
add:
readme
wishbone-compliant uart16550 core
shortlog
2004-11-22 igormTimeout interrupt should be generated only when there... master
2004-06-18 tadejmBrandl Tobias repaired a bug regarding frame error...
2004-05-21 tadejmAdded 2 LSB address generation dependent on select...
2004-05-21 tadejmRepaired bug in receiver. When stop bit is sampled...
2004-05-21 tadejmAdded synchronizer flops for RX input.
2004-05-21 tadejmAdded to synchronize RX input to Wishbone clock.
2004-03-27 tadejmTestbench with complete selfchecking. BUG is that THRE...
2004-03-27 tadejmTestbench with complete selfchecking. BUG is that THRE...
2004-03-27 tadejmTestbench with complete selfchecking. BUG is that THRE...
2004-03-27 tadejmTestbench with complete selfchecking. BUG is that THRE...
2003-12-04 simonsThis is revision 1.4, revision 1.5 was put there by...
2003-12-03 tadejmRemoved files due to new complete testbench.
2003-12-01 avishaAdd Flextronics header
2003-09-12 driesadjusted comment + define
2003-07-11 gorbanadded clearing the receiver fifo statuses on resets
2003-06-11 gorbanThis fixes errors in some cases when data is being...
...
heads
19 years ago master