Added to synchronize RX input to Wishbone clock.
tree35c2139fe394fbdb98cb5a6503f933e83e3984eb
drwxr-xr-x - bench
drwxr-xr-x - doc
drwxr-xr-x - fv
drwxr-xr-x - lint
drwxr-xr-x - rtl
drwxr-xr-x - sim
drwxr-xr-x - syn