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(parent: 3d48b2b) | patch
Added to synchronize RX input to Wishbone clock.
commit18da12624be631abf81065ef249e90081d494da8
authortadejm <tadejm>
Fri, 21 May 2004 11:43:25 +0000 (21 11:43 +0000)
committertadejm <tadejm>
Fri, 21 May 2004 11:43:25 +0000 (21 11:43 +0000)
tree35c2139fe394fbdb98cb5a6503f933e83e3984ebtree | snapshot (tar.gz zip)
parent3d48b2b501be468ba332cc36a550c4b96623706ccommit | diff
Added to synchronize RX input to Wishbone clock.
rtl/verilog/uart_sync_flops.v [new file with mode: 0644] blob
uart16550 core