Add file and line information for parameters, etc.
[sverilog.git] / Module.h
blob5985ab71770346caa47c4ac39c9ba110c26ec267
1 #ifndef __Module_H
2 #define __Module_H
3 /*
4 * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
23 # include <list>
24 # include <map>
25 # include "svector.h"
26 # include "StringHeap.h"
27 # include "HName.h"
28 # include "named.h"
29 # include "PScope.h"
30 # include "LineInfo.h"
31 # include "netlist.h"
32 # include "pform_types.h"
33 class PExpr;
34 class PEIdent;
35 class PGate;
36 class PGenerate;
37 class PSpecPath;
38 class PTask;
39 class PFunction;
40 class PWire;
41 class PProcess;
42 class Design;
43 class NetScope;
46 * A module is a named container and scope. A module holds a bunch of
47 * semantic quantities such as wires and gates. The module is
48 * therefore the handle for grasping the described circuit.
51 class Module : public PScope, public LineInfo {
53 /* The module ports are in general a vector of port_t
54 objects. Each port has a name and an ordered list of
55 wires. The name is the means that the outside uses to
56 access the port, the wires are the internal connections to
57 the port. */
58 public:
59 struct port_t {
60 perm_string name;
61 svector<PEIdent*> expr;
64 public:
65 /* The name passed here is the module name, not the instance
66 name. This make must be a permallocated string. */
67 explicit Module(perm_string name);
68 ~Module();
70 /* Initially false. This is set to true if the module has been
71 declared as a library module. This makes the module
72 ineligible for being chosen as an implicit root. It has no
73 other effect. */
74 bool library_flag;
76 NetNet::Type default_nettype;
78 /* The module has parameters that are evaluated when the
79 module is elaborated. During parsing, I put the parameters
80 into this map. */
81 struct param_expr_t {
82 PExpr*expr;
83 PExpr*msb;
84 PExpr*lsb;
85 perm_string file;
86 unsigned lineno;
87 bool signed_flag;
89 map<perm_string,param_expr_t>parameters;
90 map<perm_string,param_expr_t>localparams;
93 /* specparams are simpler then other params, in that they have
94 no type information. They are merely constant
95 expressions. */
96 map<perm_string,PExpr*>specparams;
98 /* The module also has defparam assignments which don't create
99 new parameters within the module, but may be used to set
100 values within this module (when instantiated) or in other
101 instantiated modules. */
102 map<pform_name_t,PExpr*>defparms;
104 /* Parameters may be overridden at instantiation time;
105 the overrides do not contain explicit parameter names,
106 but rather refer to parameters in the order they
107 appear in the instantiated module. Therefore a
108 list of names in module-order is needed to pass from
109 a parameter-index to its name. */
110 list<perm_string> param_names;
112 /* This is an array of port descriptors, which is in turn a
113 named array of PEident pointers. */
114 svector<port_t*> ports;
116 map<perm_string,PExpr*> attributes;
118 /* These are the timescale for this module. The default is
119 set by the `timescale directive. */
120 int time_unit, time_precision;
122 /* The module has a list of genvars that may be used in
123 various generate schemes. */
124 list<pair<perm_string,LineInfo*> > genvars;
126 /* the module has a list of generate schemes that appear in
127 the module definition. These are used at elaboration time. */
128 list<PGenerate*> generate_schemes;
130 list<PSpecPath*> specify_paths;
132 // The mod_name() is the name of the module type.
133 perm_string mod_name() const { return pscope_name(); }
135 void add_gate(PGate*gate);
136 void add_task(perm_string name, PTask*def);
137 void add_function(perm_string name, PFunction*def);
139 unsigned port_count() const;
140 const svector<PEIdent*>& get_port(unsigned idx) const;
141 unsigned find_port(const char*name) const;
143 PGate* get_gate(perm_string name);
145 const list<PGate*>& get_gates() const;
147 void dump(ostream&out) const;
148 bool elaborate(Design*, NetScope*scope) const;
150 typedef map<perm_string,NetExpr*> replace_t;
151 bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep) const;
153 bool elaborate_sig(Design*, NetScope*scope) const;
155 private:
156 list<PGate*> gates_;
157 map<perm_string,PTask*> tasks_;
158 map<perm_string,PFunction*> funcs_;
160 static void elaborate_parm_item_(perm_string name, const param_expr_t&cur,
161 Design*des, NetScope*scope,
162 perm_string file, unsigned lineno);
164 private: // Not implemented
165 Module(const Module&);
166 Module& operator= (const Module&);
169 #endif