Merge branch 'master' into verilog-ams
[sverilog.git] / Module.h
blobdaca1507879986f3e6b8e6a7eaaa5066883eeb42
1 #ifndef __Module_H
2 #define __Module_H
3 /*
4 * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
23 # include <list>
24 # include <map>
25 # include "svector.h"
26 # include "StringHeap.h"
27 # include "HName.h"
28 # include "named.h"
29 # include "PScope.h"
30 # include "LineInfo.h"
31 # include "netlist.h"
32 # include "pform_types.h"
33 class PExpr;
34 class PEIdent;
35 class PGate;
36 class PGenerate;
37 class PSpecPath;
38 class PTask;
39 class PFunction;
40 class PWire;
41 class PProcess;
42 class Design;
43 class NetScope;
46 * A module is a named container and scope. A module holds a bunch of
47 * semantic quantities such as wires and gates. The module is
48 * therefore the handle for grasping the described circuit.
51 class Module : public PScope, public LineInfo {
53 /* The module ports are in general a vector of port_t
54 objects. Each port has a name and an ordered list of
55 wires. The name is the means that the outside uses to
56 access the port, the wires are the internal connections to
57 the port. */
58 public:
59 struct port_t {
60 perm_string name;
61 svector<PEIdent*> expr;
64 public:
65 /* The name passed here is the module name, not the instance
66 name. This make must be a permallocated string. */
67 explicit Module(perm_string name);
68 ~Module();
70 /* Initially false. This is set to true if the module has been
71 declared as a library module. This makes the module
72 ineligible for being chosen as an implicit root. It has no
73 other effect. */
74 bool library_flag;
76 NetNet::Type default_nettype;
78 struct range_t {
79 // True if this is an exclude
80 bool exclude_flag;
81 // lower bound
82 // If low_open_flag is false and low_expr=0, then use -inf
83 bool low_open_flag;
84 PExpr*low_expr;
85 // upper bound
86 // If high_open_flag is false and high_expr=0, then use +inf
87 bool high_open_flag;
88 PExpr*high_expr;
89 // Next range description in list
90 struct range_t*next;
93 /* The module has parameters that are evaluated when the
94 module is elaborated. During parsing, I put the parameters
95 into this map. */
96 struct param_expr_t : public LineInfo {
97 param_expr_t() : range(0) { }
98 // Type information
99 ivl_variable_type_t type;
100 PExpr*msb;
101 PExpr*lsb;
102 bool signed_flag;
103 // Value expression
104 PExpr*expr;
105 // If there are range constrants, list them here
106 range_t*range;
108 map<perm_string,param_expr_t>parameters;
109 map<perm_string,param_expr_t>localparams;
112 /* specparams are simpler then other params, in that they have
113 no type information. They are merely constant
114 expressions. */
115 map<perm_string,PExpr*>specparams;
117 /* The module also has defparam assignments which don't create
118 new parameters within the module, but may be used to set
119 values within this module (when instantiated) or in other
120 instantiated modules. */
121 map<pform_name_t,PExpr*>defparms;
123 /* Parameters may be overridden at instantiation time;
124 the overrides do not contain explicit parameter names,
125 but rather refer to parameters in the order they
126 appear in the instantiated module. Therefore a
127 list of names in module-order is needed to pass from
128 a parameter-index to its name. */
129 list<perm_string> param_names;
131 /* This is an array of port descriptors, which is in turn a
132 named array of PEident pointers. */
133 svector<port_t*> ports;
135 map<perm_string,PExpr*> attributes;
137 /* These are the timescale for this module. The default is
138 set by the `timescale directive. */
139 int time_unit, time_precision;
141 /* The module has a list of genvars that may be used in
142 various generate schemes. */
143 map<perm_string,LineInfo*> genvars;
145 /* the module has a list of generate schemes that appear in
146 the module definition. These are used at elaboration time. */
147 list<PGenerate*> generate_schemes;
149 list<PSpecPath*> specify_paths;
151 // The mod_name() is the name of the module type.
152 perm_string mod_name() const { return pscope_name(); }
154 void add_gate(PGate*gate);
155 void add_task(perm_string name, PTask*def);
156 void add_function(perm_string name, PFunction*def);
158 unsigned port_count() const;
159 const svector<PEIdent*>& get_port(unsigned idx) const;
160 unsigned find_port(const char*name) const;
162 PGate* get_gate(perm_string name);
164 const list<PGate*>& get_gates() const;
166 void dump(ostream&out) const;
167 bool elaborate(Design*, NetScope*scope) const;
169 typedef map<perm_string,NetExpr*> replace_t;
170 bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep) const;
172 bool elaborate_sig(Design*, NetScope*scope) const;
174 private:
175 list<PGate*> gates_;
176 map<perm_string,PTask*> tasks_;
177 map<perm_string,PFunction*> funcs_;
179 static void elaborate_parm_item_(perm_string name, const param_expr_t&cur,
180 Design*des, NetScope*scope);
182 private: // Not implemented
183 Module(const Module&);
184 Module& operator= (const Module&);
187 #endif