| blob | 423895de32c54738ca6b3609968b979b04c478e9 |
1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
24 if-statements and ?: on it. This way we have compile-time error checking
25 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
26 to optimize away all constant tests. */
27 #ifdef MOTOROLA
28 # undef MOTOROLA
31 #else
34 #endif
36 /* Note that some other tm.h files include this one and then override
37 many of the definitions that relate to assembler syntax. */
39 /* Target CPU builtins. */
40 #define TARGET_CPU_CPP_BUILTINS() \
41 do \
42 { \
45 if (TARGET_68040_ONLY) \
46 { \
47 if (TARGET_68060) \
49 else \
51 } \
53 { \
58 } \
60 { \
64 } \
65 else if (TARGET_68030) \
67 else if (TARGET_68020) \
69 if (TARGET_68881) \
71 if (TARGET_CPU32) \
72 { \
75 } \
76 if (TARGET_COLDFIRE) \
78 if (TARGET_5200) \
80 if (TARGET_528x) \
81 { \
84 } \
85 if (TARGET_CFV3) \
86 { \
89 } \
90 if (TARGET_CFV4) \
91 { \
94 } \
95 if (TARGET_CF_HWDIV) \
97 if (flag_pic) \
98 { \
100 if (flag_pic > 1) \
102 } \
105 } \
106 while (0)
108 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
109 quantities. */
115 /* Set the default */
116 #define INT_OP_GROUP INT_OP_DOT_WORD
118 /* Run-time compilation parameters selecting different hardware subsets. */
122 /* Macros used in the machine description to test the flags. */
124 /* Compile for a 68020 (not a 68000 or 68010). */
125 #define MASK_68020 (1<<0)
126 #define TARGET_68020 (target_flags & MASK_68020)
128 /* Compile for a 68030. This does not really make a difference in GCC,
129 it just enables the __mc68030__ predefine. */
130 #define MASK_68030 (1<<1)
131 #define TARGET_68030 (target_flags & MASK_68030)
133 /* Optimize for 68040, but still allow execution on 68020
134 (-m68020-40 or -m68040).
135 The 68040 will execute all 68030 and 68881/2 instructions, but some
136 of them must be emulated in software by the OS. When TARGET_68040 is
137 turned on, these instructions won't be used. This code will still
138 run on a 68030 and 68881/2. */
139 #define MASK_68040 (1<<2)
140 #define TARGET_68040 (target_flags & MASK_68040)
142 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
143 #define MASK_68040_ONLY (1<<3)
144 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
146 /* Optimize for 68060, but still allow execution on 68020
147 (-m68020-60 or -m68060).
148 The 68060 will execute all 68030 and 68881/2 instructions, but some
149 of them must be emulated in software by the OS. When TARGET_68060 is
150 turned on, these instructions won't be used. This code will still
151 run on a 68030 and 68881/2. */
152 #define MASK_68060 (1<<4)
153 #define TARGET_68060 (target_flags & MASK_68060)
155 /* Compile for mcf5200 */
156 #define MASK_5200 (1<<5)
157 #define TARGET_5200 (target_flags & MASK_5200)
159 /* Build for ColdFire v3 */
160 #define MASK_CFV3 (1<<6)
161 #define TARGET_CFV3 (target_flags & MASK_CFV3)
163 /* Build for ColdFire v4 */
164 #define MASK_CFV4 (1<<7)
165 #define TARGET_CFV4 (target_flags & MASK_CFV4)
167 /* Compile for ColdFire 528x */
168 #define MASK_528x (1<<8)
169 #define TARGET_528x (target_flags & MASK_528x)
171 /* Divide support for ColdFire */
172 #define MASK_CF_HWDIV (1<<9)
173 #define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
175 /* Compile 68881 insns for floating point (not library calls). */
176 #define MASK_68881 (1<<10)
177 #define TARGET_68881 (target_flags & MASK_68881)
179 /* Compile using 68020 bit-field insns. */
180 #define MASK_BITFIELD (1<<11)
181 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
183 /* Compile with 16-bit `int'. */
184 #define MASK_SHORT (1<<12)
185 #define TARGET_SHORT (target_flags & MASK_SHORT)
187 /* Align ints to a word boundary. This breaks compatibility with the
188 published ABI's for structures containing ints, but produces faster
189 code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire).
190 It's required for ColdFire cpus without a misalignment module. */
191 #define MASK_ALIGN_INT (1<<13)
192 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
194 /* Use PC-relative addressing modes (without using a global offset table).
195 The m68000 supports 16-bit PC-relative addressing.
196 The m68020 supports 32-bit PC-relative addressing
197 (using outer displacements).
199 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
200 treated as all containing an implicit PC-relative component, and hence
201 cannot be used directly as addresses for memory writes. See the comments
202 in m68k.c for more information. */
203 #define MASK_PCREL (1<<14)
204 #define TARGET_PCREL (target_flags & MASK_PCREL)
206 /* Relax strict alignment. */
207 #define MASK_NO_STRICT_ALIGNMENT (1<<15)
208 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
210 /* Compile using rtd insn calling sequence.
211 This will not work unless you use prototypes at least
212 for all functions that can take varying numbers of args. */
213 #define MASK_RTD (1<<16)
214 #define TARGET_RTD (target_flags & MASK_RTD)
216 /* Support A5 relative data separate from text.
217 * This option implies -fPIC, however it inhibits the generation of the
218 * A5 save/restore in functions and the loading of a5 with a got pointer.
219 */
220 #define MASK_SEP_DATA (1<<17)
221 #define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA)
223 /* Compile using library ID based shared libraries.
224 * Set a specific ID using the -mshared-library-id=xxx option.
225 */
226 #define MASK_ID_SHARED_LIBRARY (1<<18)
227 #define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY)
229 /* Compile for a CPU32. A 68020 without bitfields is a good
230 heuristic for a CPU32. */
231 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
233 /* Is the target a ColdFire? */
234 #define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
235 #define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
237 /* Which bits can be set by specifying a ColdFire */
238 #define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
240 /* Macro to define tables used to set the flags.
241 This is a list in braces of pairs in braces,
242 each pair being { "NAME", VALUE }
243 where VALUE is the bits to set or minus the bits to clear.
244 An empty string NAME is used to identify the default VALUE. */
246 #define TARGET_SWITCHES \
254 |MASK_68020|MASK_BITFIELD|MASK_68881), \
257 |MASK_68020|MASK_BITFIELD|MASK_68881), \
289 |MASK_BITFIELD|MASK_68881), \
293 |MASK_BITFIELD|MASK_68881), \
297 |MASK_BITFIELD|MASK_68881), \
301 |MASK_BITFIELD|MASK_68881), \
305 |MASK_BITFIELD|MASK_68881), \
313 |MASK_68020|MASK_BITFIELD|MASK_68881), \
316 |MASK_BITFIELD|MASK_68881), \
320 |MASK_BITFIELD|MASK_68881), \
345 SUBTARGET_SWITCHES \
347 /* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */
349 /* This macro is similar to `TARGET_SWITCHES' but defines names of
350 command options that have values. Its definition is an
351 initializer with a subgrouping for each command option.
353 Each subgrouping contains a string constant, that defines the
354 fixed part of the option name, and the address of a variable. The
355 variable, type `char *', is set to the variable part of the given
356 option if the fixed part matches. The actual option name is made
357 by appending `-m' to the specified name. */
358 #define TARGET_OPTIONS \
367 SUBTARGET_OPTIONS \
368 }
370 /* Sometimes certain combinations of command options do not make
371 sense on a particular target machine. You can define a macro
372 `OVERRIDE_OPTIONS' to take account of this. This macro, if
373 defined, is executed once just after all the command options have
374 been parsed.
376 Don't use this macro to turn on various extra optimizations for
377 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
379 #define OVERRIDE_OPTIONS override_options()
381 /* These are meant to be redefined in the host dependent files */
382 #define SUBTARGET_SWITCHES
383 #define SUBTARGET_OPTIONS
384 #define SUBTARGET_OVERRIDE_OPTIONS
385 \f
386 /* target machine storage layout */
388 /* Define for XFmode extended real floating point support. */
389 #define LONG_DOUBLE_TYPE_SIZE 96
391 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
392 instructions, we get proper intermediate rounding, otherwise we
393 get extended precision results. */
394 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
396 /* Define this if most significant bit is lowest numbered
397 in instructions that operate on numbered bit-fields.
398 This is true for 68020 insns such as bfins and bfexts.
399 We make it true always by avoiding using the single-bit insns
400 except in special cases with constant bit numbers. */
401 #define BITS_BIG_ENDIAN 1
403 /* Define this if most significant byte of a word is the lowest numbered. */
404 /* That is true on the 68000. */
405 #define BYTES_BIG_ENDIAN 1
407 /* Define this if most significant word of a multiword number is the lowest
408 numbered. */
409 /* For 68000 we can decide arbitrarily
410 since there are no machine instructions for them.
411 So let's be consistent. */
412 #define WORDS_BIG_ENDIAN 1
414 /* Width of a word, in units (bytes). */
415 #define UNITS_PER_WORD 4
417 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
418 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
420 /* Boundary (in *bits*) on which stack pointer should be aligned. */
421 #define STACK_BOUNDARY 16
423 /* Allocation boundary (in *bits*) for the code of a function. */
424 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
426 /* Alignment of field after `int : 0' in a structure. */
427 #define EMPTY_FIELD_BOUNDARY 16
429 /* No data type wants to be aligned rounder than this.
430 Most published ABIs say that ints should be aligned on 16 bit
431 boundaries, but cpus with 32-bit busses get better performance
432 aligned on 32-bit boundaries. ColdFires without a misalignment
433 module require 32-bit alignment. */
434 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
436 /* Set this nonzero if move instructions will actually fail to work
437 when given unaligned data. */
438 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
440 /* Maximum power of 2 that code can be aligned to. */
443 /* Maximum number of library ids we permit */
444 #define MAX_LIBRARY_ID 255
446 /* Align loop starts for optimal branching. */
447 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
449 /* This is how to align an instruction for optimal branching. */
450 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
452 /* Define number of bits in most basic integer type.
453 (If undefined, default is BITS_PER_WORD). */
455 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
457 /* Define these to avoid dependence on meaning of `int'. */
460 #define WCHAR_TYPE_SIZE 32
461 \f
462 /* Standard register usage. */
464 /* Number of actual hardware registers.
465 The hardware registers are assigned numbers for the compiler
466 from 0 to just below FIRST_PSEUDO_REGISTER.
467 All registers that the compiler knows about must be given numbers,
468 even those that are not normally considered general registers.
469 For the 68000, we give the data registers numbers 0-7,
470 the address registers numbers 010-017,
471 and the 68881 floating point registers numbers 020-027. */
472 #define FIRST_PSEUDO_REGISTER 25
474 /* This defines the register which is used to hold the offset table for PIC. */
475 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
477 /* 1 for registers that have pervasive standard uses
478 and are not available for the register allocator.
479 On the 68000, only the stack pointer is such. */
481 #define FIXED_REGISTERS \
483 0, 0, 0, 0, 0, 0, 0, 0, \
484 \
486 0, 0, 0, 0, 0, 0, 0, 1, \
487 \
488 /* Floating point registers \
490 0, 0, 0, 0, 0, 0, 0, 0 }
492 /* 1 for registers not available across function calls.
493 These must include the FIXED_REGISTERS and also any
494 registers that can be used without being saved.
495 The latter must include the registers where values are returned
496 and the register where structure-value addresses are passed.
497 Aside from that, you can include as many other registers as you like. */
498 #define CALL_USED_REGISTERS \
499 {1, 1, 0, 0, 0, 0, 0, 0, \
500 1, 1, 0, 0, 0, 0, 0, 1, \
501 1, 1, 0, 0, 0, 0, 0, 0 }
504 /* Make sure everything's fine if we *don't* have a given processor.
505 This assumes that putting a register in fixed_regs will keep the
506 compiler's mitts completely off it. We don't bother to zero it out
507 of register classes. */
509 #define CONDITIONAL_REGISTER_USAGE \
510 { \
511 int i; \
512 HARD_REG_SET x; \
513 if (! TARGET_68881) \
514 { \
515 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
516 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
517 if (TEST_HARD_REG_BIT (x, i)) \
518 fixed_regs[i] = call_used_regs[i] = 1; \
519 } \
520 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
521 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
522 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
523 }
525 /* Return number of consecutive hard regs needed starting at reg REGNO
526 to hold something of mode MODE.
527 This is ordinarily the length in words of a value of mode MODE
528 but can be less for certain modes in special long registers.
530 On the 68000, ordinary registers hold 32 bits worth;
531 for the 68881 registers, a single register is always enough for
532 anything that can be stored in them at all. */
533 #define HARD_REGNO_NREGS(REGNO, MODE) \
534 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
535 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
537 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
538 On the 68000, the cpu registers can hold any mode but the 68881 registers
539 can hold only SFmode or DFmode. */
541 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
542 (((REGNO) < 16 \
543 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
544 || ((REGNO) >= 16 && (REGNO) < 24 \
545 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
546 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
547 && GET_MODE_UNIT_SIZE (MODE) <= 12))
550 /* Value is 1 if it is a good idea to tie two pseudo registers
551 when one has mode MODE1 and one has mode MODE2.
552 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
553 for any hard reg, then this must be 0 for correct output. */
554 #define MODES_TIEABLE_P(MODE1, MODE2) \
555 (! TARGET_68881 \
556 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
557 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
558 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
559 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
561 /* Specify the registers used for certain standard purposes.
562 The values of these macros are register numbers. */
564 /* m68000 pc isn't overloaded on a register. */
565 /* #define PC_REGNUM */
567 /* Register to use for pushing function arguments. */
568 #define STACK_POINTER_REGNUM 15
570 /* Base register for access to local variables of the function. */
571 #define FRAME_POINTER_REGNUM 14
573 /* Value should be nonzero if functions must have frame pointers.
574 Zero means the frame pointer need not be set up (and parms
575 may be accessed via the stack pointer) in functions that seem suitable.
576 This is computed in `reload', in reload1.c. */
577 #define FRAME_POINTER_REQUIRED 0
579 /* Base register for access to arguments of the function.
580 * This isn't a hardware register. It will be eliminated to the
581 * stack pointer or frame pointer.
582 */
583 #define ARG_POINTER_REGNUM 24
585 /* Register in which static-chain is passed to a function. */
586 #define STATIC_CHAIN_REGNUM 8
588 /* Register in which address to store a structure value
589 is passed to a function. */
590 #define STRUCT_VALUE_REGNUM 9
591 \f
592 /* Define the classes of registers for register constraints in the
593 machine description. Also define ranges of constants.
595 One of the classes must always be named ALL_REGS and include all hard regs.
596 If there is more than one class, another class must be named NO_REGS
597 and contain no registers.
599 The name GENERAL_REGS must be the name of a class (or an alias for
600 another name such as ALL_REGS). This is the class of registers
601 that is allowed by "g" or "r" in a register constraint.
602 Also, registers outside this class are allocated only when
603 instructions express preferences for them.
605 The classes must be numbered in nondecreasing order; that is,
606 a larger-numbered class must never be contained completely
607 in a smaller-numbered class.
609 For any two classes, it is very desirable that there be another
610 class that represents their union. */
612 /* The 68000 has three kinds of registers, so eight classes would be
613 a complete set. One of them is not needed. */
620 LIM_REG_CLASSES };
622 #define N_REG_CLASSES (int) LIM_REG_CLASSES
624 /* Give names of register classes as strings for dump file. */
626 #define REG_CLASS_NAMES \
632 /* Define which registers fit in which classes.
633 This is an initializer for a vector of HARD_REG_SET
634 of length N_REG_CLASSES. */
636 #define REG_CLASS_CONTENTS \
637 { \
646 }
648 /* The same information, inverted:
649 Return the class number of the smallest class containing
650 reg number REGNO. This could be a conditional expression
651 or could index an array. */
653 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
655 /* The class value for index registers, and the one for base regs. */
657 #define INDEX_REG_CLASS GENERAL_REGS
658 #define BASE_REG_CLASS ADDR_REGS
660 /* Get reg_class from a letter such as appears in the machine description.
661 We do a trick here to modify the effective constraints on the
662 machine description; we zorch the constraint letters that aren't
663 appropriate for a specific target. This allows us to guarantee
664 that a specific kind of register will not be used for a given target
665 without fiddling with the register classes above. */
667 #define REG_CLASS_FROM_LETTER(C) \
671 NO_REGS) : \
672 NO_REGS)))
674 /* The letters I, J, K, L and M in a register constraint string
675 can be used to stand for particular ranges of immediate operands.
676 This macro defines what the ranges are.
677 C is the letter, and VALUE is a constant value.
678 Return 1 if VALUE is in the range specified by C.
680 For the 68000, `I' is used for the range 1 to 8
681 allowed as immediate shift counts and in addq.
682 `J' is used for the range of signed numbers that fit in 16 bits.
683 `K' is for numbers that moveq can't handle.
684 `L' is for range -8 to -1, range of values that can be added with subq.
685 `M' is for numbers that moveq+notb can't handle.
686 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
687 'O' is for 16 (for rotate using swap).
688 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
690 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
700 /*
701 * A small bit of explanation:
702 * "G" defines all of the floating constants that are *NOT* 68881
703 * constants. this is so 68881 constants get reloaded and the
704 * fpmovecr is used.
705 */
706 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
709 /* A C expression that defines the optional machine-dependent constraint
710 letters that can be used to segregate specific types of operands,
711 usually memory references, for the target machine. It should return 1 if
712 VALUE corresponds to the operand type represented by the constraint letter
713 C. If C is not defined as an extra constraint, the value returned should
714 be 0 regardless of VALUE. */
716 /* Letters in the range `Q' through `U' may be defined in a
717 machine-dependent fashion to stand for arbitrary operand types.
718 The machine description macro `EXTRA_CONSTRAINT' is passed the
719 operand as its first argument and the constraint letter as its
720 second operand.
722 `Q' means address register indirect addressing mode.
723 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
724 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
726 #define EXTRA_CONSTRAINT(OP,CODE) \
728 ? (TARGET_PCREL \
729 && GET_CODE (OP) == MEM \
730 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
731 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
732 || GET_CODE (XEXP (OP, 0)) == CONST)) \
733 : \
735 ? ( !TARGET_PCREL \
736 && (GET_CODE (OP) == SYMBOL_REF \
737 || GET_CODE (OP) == LABEL_REF \
738 || GET_CODE (OP) == CONST)) \
739 : \
741 ? (GET_CODE (OP) == MEM \
742 && GET_CODE (XEXP (OP, 0)) == REG) \
743 : \
744 0)))
746 /* Given an rtx X being reloaded into a reg required to be
747 in class CLASS, return the class of reg to actually use.
748 In general this is just CLASS; but on some machines
749 in some cases it is preferable to use a more restrictive class.
750 On the 68000 series, use a data reg if possible when the
751 value is a constant in the range where moveq could be used
752 and we ensure that QImodes are reloaded into data regs. */
754 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
755 ((GET_CODE (X) == CONST_INT \
756 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
757 && (CLASS) != ADDR_REGS) \
758 ? DATA_REGS \
759 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
760 ? DATA_REGS \
761 : (GET_CODE (X) == CONST_DOUBLE \
762 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
763 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
764 ? FP_REGS : NO_REGS) \
765 : (TARGET_PCREL \
766 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
767 || GET_CODE (X) == LABEL_REF)) \
768 ? ADDR_REGS \
769 : (CLASS))
771 /* Force QImode output reloads from subregs to be allocated to data regs,
772 since QImode stores from address regs are not supported. We make the
773 assumption that if the class is not ADDR_REGS, then it must be a superset
774 of DATA_REGS. */
776 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
777 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
778 ? DATA_REGS \
779 : (CLASS))
781 /* Return the maximum number of consecutive registers
782 needed to represent mode MODE in a register of class CLASS. */
783 /* On the 68000, this is the size of MODE in words,
784 except in the FP regs, where a single reg is always enough. */
785 #define CLASS_MAX_NREGS(CLASS, MODE) \
786 ((CLASS) == FP_REGS ? 1 \
787 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
789 /* Moves between fp regs and other regs are two insns. */
790 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
791 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
792 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
793 ? 4 : 2)
794 \f
795 /* Stack layout; function entry, exit and calling. */
797 /* Define this if pushing a word on the stack
798 makes the stack pointer a smaller address. */
799 #define STACK_GROWS_DOWNWARD
801 /* Define this if the nominal address of the stack frame
802 is at the high-address end of the local variables;
803 that is, each additional local variable allocated
804 goes at a more negative offset in the frame. */
805 #define FRAME_GROWS_DOWNWARD
807 /* Offset within stack frame to start allocating local variables at.
808 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
809 first local allocated. Otherwise, it is the offset to the BEGINNING
810 of the first local allocated. */
811 #define STARTING_FRAME_OFFSET 0
813 /* If we generate an insn to push BYTES bytes,
814 this says how many the stack pointer really advances by.
815 On the 68000, sp@- in a byte insn really pushes a word.
816 On the 5200 (ColdFire), sp@- in a byte insn pushes just a byte. */
817 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
819 /* We want to avoid trying to push bytes. */
820 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
821 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
822 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
824 /* Offset of first parameter from the argument pointer register value. */
825 #define FIRST_PARM_OFFSET(FNDECL) 8
827 /* Value is the number of byte of arguments automatically
828 popped when returning from a subroutine call.
829 FUNDECL is the declaration node of the function (as a tree),
830 FUNTYPE is the data type of the function (as a tree),
831 or for a library call it is an identifier node for the subroutine name.
832 SIZE is the number of bytes of arguments passed on the stack.
834 On the 68000, the RTS insn cannot pop anything.
835 On the 68010, the RTD insn may be used to pop them if the number
836 of args is fixed, but if the number is variable then the caller
837 must pop them all. RTD can't be used for library calls now
838 because the library is compiled with the Unix compiler.
839 Use of RTD is a selectable option, since it is incompatible with
840 standard Unix calling sequences. If the option is not selected,
841 the caller must always pop the args. */
843 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
844 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
845 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
846 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
847 == void_type_node))) \
848 ? (SIZE) : 0)
850 /* Define how to find the value returned by a function.
851 VALTYPE is the data type of the value (as a tree).
852 If the precise function being called is known, FUNC is its FUNCTION_DECL;
853 otherwise, FUNC is 0. */
855 /* On the 68000 the return value is in D0 regardless. */
857 #define FUNCTION_VALUE(VALTYPE, FUNC) \
858 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
860 /* Define how to find the value returned by a library function
861 assuming the value has mode MODE. */
863 /* On the 68000 the return value is in D0 regardless. */
865 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
867 /* 1 if N is a possible register number for a function value.
868 On the 68000, d0 is the only register thus used. */
870 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
872 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
873 more than one register. */
875 #define NEEDS_UNTYPED_CALL 0
877 /* Define this if PCC uses the nonreentrant convention for returning
878 structure and union values. */
880 #define PCC_STATIC_STRUCT_RETURN
882 /* 1 if N is a possible register number for function argument passing.
883 On the 68000, no registers are used in this way. */
885 #define FUNCTION_ARG_REGNO_P(N) 0
886 \f
887 /* Define a data type for recording info about an argument list
888 during the scan of that argument list. This data type should
889 hold all necessary information about the function itself
890 and about the args processed so far, enough to enable macros
891 such as FUNCTION_ARG to determine where the next arg should go.
893 On the m68k, this is a single integer, which is a number of bytes
894 of arguments scanned so far. */
896 #define CUMULATIVE_ARGS int
898 /* Initialize a variable CUM of type CUMULATIVE_ARGS
899 for a call to a function whose data type is FNTYPE.
900 For a library call, FNTYPE is 0.
902 On the m68k, the offset starts at 0. */
904 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
905 ((CUM) = 0)
907 /* Update the data in CUM to advance over an argument
908 of mode MODE and data type TYPE.
909 (TYPE is null for libcalls where that information may not be available.) */
911 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
912 ((CUM) += ((MODE) != BLKmode \
913 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
914 : (int_size_in_bytes (TYPE) + 3) & ~3))
916 /* Define where to put the arguments to a function.
917 Value is zero to push the argument on the stack,
918 or a hard register in which to store the argument.
920 MODE is the argument's machine mode.
921 TYPE is the data type of the argument (as a tree).
922 This is null for libcalls where that information may
923 not be available.
924 CUM is a variable of type CUMULATIVE_ARGS which gives info about
925 the preceding args and about the function being called.
926 NAMED is nonzero if this argument is a named parameter
927 (otherwise it is an extra parameter matching an ellipsis).
929 On the m68k all args are always pushed. */
931 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
933 /* For an arg passed partly in registers and partly in memory,
934 this is the number of registers used.
935 For args passed entirely in registers or entirely in memory, zero. */
937 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
939 /* Output assembler code to FILE to increment profiler label # LABELNO
940 for profiling a function entry. */
942 #define FUNCTION_PROFILER(FILE, LABELNO) \
945 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
946 the stack pointer does not matter. The value is tested only in
947 functions that have frame pointers.
948 No definition is equivalent to always zero. */
950 #define EXIT_IGNORE_STACK 1
952 /* This is a hook for other tm files to change. */
953 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
955 /* Determine if the epilogue should be output as RTL.
956 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
957 #define USE_RETURN_INSN use_return_insn ()
959 /* Output assembler code for a block containing the constant parts
960 of a trampoline, leaving space for the variable parts. */
962 /* On the 68k, the trampoline looks like this:
963 movl #STATIC,a0
964 jmp FUNCTION
966 WARNING: Targets that may run on 68040+ cpus must arrange for
967 the instruction cache to be flushed. Previous incarnations of
968 the m68k trampoline code attempted to get around this by either
969 using an out-of-line transfer function or pc-relative data, but
970 the fact remains that the code to jump to the transfer function
971 or the code to load the pc-relative data needs to be flushed
972 just as much as the "variable" portion of the trampoline.
973 Recognizing that a cache flush is going to be required anyway,
974 dispense with such notions and build a smaller trampoline. */
976 /* Since more instructions are required to move a template into
977 place than to create it on the spot, don't use a template. */
979 /* Length in units of the trampoline for entering a nested function. */
981 #define TRAMPOLINE_SIZE 12
983 /* Alignment required for a trampoline in bits. */
985 #define TRAMPOLINE_ALIGNMENT 16
987 /* Targets redefine this to invoke code to either flush the cache,
988 or enable stack execution (or both). */
990 #ifndef FINALIZE_TRAMPOLINE
991 #define FINALIZE_TRAMPOLINE(TRAMP)
992 #endif
994 /* Emit RTL insns to initialize the variable parts of a trampoline.
995 FNADDR is an RTX for the address of the function's pure code.
996 CXT is an RTX for the static chain value for the function.
998 We generate a two-instructions program at address TRAMP :
999 movea.l &CXT,%a0
1000 jmp FNADDR */
1002 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1003 { \
1004 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1005 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1006 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1007 GEN_INT(0x4EF9)); \
1008 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1009 FINALIZE_TRAMPOLINE(TRAMP); \
1010 }
1012 /* This is the library routine that is used
1013 to transfer control from the trampoline
1014 to the actual nested function.
1015 It is defined for backward compatibility,
1016 for linking with object code that used the old
1017 trampoline definition. */
1019 /* A colon is used with no explicit operands
1020 to cause the template string to be scanned for %-constructs. */
1021 /* The function name __transfer_from_trampoline is not actually used.
1022 The function definition just permits use of "asm with operands"
1023 (though the operand list is empty). */
1024 #define TRANSFER_FROM_TRAMPOLINE \
1025 void \
1026 __transfer_from_trampoline () \
1027 { \
1034 }
1035 \f
1036 /* Definitions for register eliminations.
1038 This is an array of structures. Each structure initializes one pair
1039 of eliminable registers. The "from" register number is given first,
1040 followed by "to". Eliminations of the same "from" register are listed
1041 in order of preference.
1043 There are two registers that can always be eliminated on the m68k.
1044 The frame pointer and the arg pointer can be replaced by either the
1045 hard frame pointer or to the stack pointer, depending upon the
1046 circumstances. The hard frame pointer is not used before reload and
1047 so it is not eligible for elimination. */
1049 #define ELIMINABLE_REGS \
1050 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1051 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
1052 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
1054 /* Given FROM and TO register numbers, say whether this elimination is
1055 allowed. Frame pointer elimination is automatically handled.
1057 All other eliminations are valid. */
1059 #define CAN_ELIMINATE(FROM, TO) \
1060 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1062 /* Define the offset between two registers, one to be eliminated, and the other
1063 its replacement, at the start of a routine. */
1065 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1066 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
1067 \f
1068 /* Addressing modes, and classification of registers for them. */
1070 #define HAVE_POST_INCREMENT 1
1072 #define HAVE_PRE_DECREMENT 1
1074 /* Macros to check register numbers against specific register classes. */
1076 /* These assume that REGNO is a hard or pseudo reg number.
1077 They give nonzero only if REGNO is a hard reg of the suitable class
1078 or a pseudo reg currently allocated to a suitable hard reg.
1079 Since they use reg_renumber, they are safe only once reg_renumber
1080 has been allocated, which happens in local-alloc.c. */
1082 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1083 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1084 #define REGNO_OK_FOR_BASE_P(REGNO) \
1085 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1086 #define REGNO_OK_FOR_DATA_P(REGNO) \
1087 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1088 #define REGNO_OK_FOR_FP_P(REGNO) \
1089 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1091 /* Now macros that check whether X is a register and also,
1092 strictly, whether it is in a specified class.
1094 These macros are specific to the 68000, and may be used only
1095 in code for printing assembler insns and in conditions for
1096 define_optimization. */
1098 /* 1 if X is a data register. */
1100 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1102 /* 1 if X is an fp register. */
1104 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1106 /* 1 if X is an address register */
1108 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1109 \f
1110 /* Maximum number of registers that can appear in a valid memory address. */
1112 #define MAX_REGS_PER_ADDRESS 2
1114 /* Recognize any constant value that is a valid address. */
1116 #define CONSTANT_ADDRESS_P(X) \
1117 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1118 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1119 || GET_CODE (X) == HIGH)
1121 /* Nonzero if the constant value X is a legitimate general operand.
1122 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1124 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
1126 /* Nonzero if the constant value X is a legitimate general operand
1127 when generating PIC code. It is given that flag_pic is on and
1128 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1130 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1131 accepted by insn predicates, but which would otherwise fail the
1132 `general_operand' test. */
1134 #ifndef REG_OK_STRICT
1135 #define PCREL_GENERAL_OPERAND_OK 0
1136 #else
1137 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1138 #endif
1140 #define LEGITIMATE_PIC_OPERAND_P(X) \
1141 (! symbolic_operand (X, VOIDmode) \
1142 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1143 || PCREL_GENERAL_OPERAND_OK)
1145 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1146 and check its validity for a certain class.
1147 We have two alternate definitions for each of them.
1148 The usual definition accepts all pseudo regs; the other rejects
1149 them unless they have been allocated suitable hard regs.
1150 The symbol REG_OK_STRICT causes the latter definition to be used.
1152 Most source files want to accept pseudo regs in the hope that
1153 they will get allocated to the class that the insn wants them to be in.
1154 Source files for reload pass need to be strict.
1155 After reload, it makes no difference, since pseudo regs have
1156 been eliminated by then. */
1158 #ifndef REG_OK_STRICT
1160 /* Nonzero if X is a hard reg that can be used as an index
1161 or if it is a pseudo reg. */
1162 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1163 /* Nonzero if X is a hard reg that can be used as a base reg
1164 or if it is a pseudo reg. */
1165 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1167 #else
1169 /* Nonzero if X is a hard reg that can be used as an index. */
1170 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1171 /* Nonzero if X is a hard reg that can be used as a base reg. */
1172 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1174 #endif
1175 \f
1176 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1177 that is a valid memory address for an instruction.
1178 The MODE argument is the machine mode for the MEM expression
1179 that wants to use this address.
1181 When generating PIC, an address involving a SYMBOL_REF is legitimate
1182 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1183 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1184 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1186 Likewise for a LABEL_REF when generating PIC.
1188 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1190 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1191 also makes function inlining work when inline functions are called with
1192 arguments that are SUBREGs. */
1194 #define LEGITIMATE_BASE_REG_P(X) \
1195 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1196 || (GET_CODE (X) == SUBREG \
1197 && GET_CODE (SUBREG_REG (X)) == REG \
1198 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1200 #define INDIRECTABLE_1_ADDRESS_P(X) \
1201 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1202 || LEGITIMATE_BASE_REG_P (X) \
1203 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1204 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1205 || (GET_CODE (X) == PLUS \
1206 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1207 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1208 && (TARGET_68020 \
1209 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1210 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1211 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1212 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1213 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1215 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1216 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1218 /* Only labels on dispatch tables are valid for indexing from. */
1219 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1220 { rtx temp; \
1221 if (GET_CODE (X) == LABEL_REF \
1222 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1223 && GET_CODE (temp) == JUMP_INSN \
1224 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1225 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1226 goto ADDR; \
1227 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1229 #define GO_IF_INDEXING(X, ADDR) \
1230 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1231 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1232 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1233 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1235 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1236 { GO_IF_INDEXING (X, ADDR); \
1237 if (GET_CODE (X) == PLUS) \
1238 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1239 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1240 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1241 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1242 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1243 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1245 /* ColdFire/5200 does not allow HImode index registers. */
1246 #define LEGITIMATE_INDEX_REG_P(X) \
1247 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1248 || (! TARGET_COLDFIRE \
1249 && GET_CODE (X) == SIGN_EXTEND \
1250 && GET_CODE (XEXP (X, 0)) == REG \
1251 && GET_MODE (XEXP (X, 0)) == HImode \
1252 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1253 || (GET_CODE (X) == SUBREG \
1254 && GET_CODE (SUBREG_REG (X)) == REG \
1255 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1257 #define LEGITIMATE_INDEX_P(X) \
1258 (LEGITIMATE_INDEX_REG_P (X) \
1259 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
1260 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1261 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1262 && (INTVAL (XEXP (X, 1)) == 2 \
1263 || INTVAL (XEXP (X, 1)) == 4 \
1264 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
1266 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1267 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1268 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1269 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1270 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1271 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1272 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1273 goto ADDR; }
1275 /* Don't call memory_address_noforce for the address to fetch
1276 the switch offset. This address is ok as it stands (see above),
1277 but memory_address_noforce would alter it. */
1278 #define PIC_CASE_VECTOR_ADDRESS(index) index
1279 \f
1280 /* Try machine-dependent ways of modifying an illegitimate address
1281 to be legitimate. If we find one, return the new, valid address.
1282 This macro is used in only one place: `memory_address' in explow.c.
1284 OLDX is the address as it was before break_out_memory_refs was called.
1285 In some cases it is useful to look at this to decide what needs to be done.
1287 MODE and WIN are passed so that this macro can use
1288 GO_IF_LEGITIMATE_ADDRESS.
1290 It is always safe for this macro to do nothing. It exists to recognize
1291 opportunities to optimize the output.
1293 For the 68000, we handle X+REG by loading X into a register R and
1294 using R+REG. R will go in an address reg and indexing will be used.
1295 However, if REG is a broken-out memory address or multiplication,
1296 nothing needs to be done because REG can certainly go in an address reg. */
1298 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1299 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1300 { register int ch = (X) != (OLDX); \
1301 if (GET_CODE (X) == PLUS) \
1302 { int copied = 0; \
1303 if (GET_CODE (XEXP (X, 0)) == MULT) \
1304 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1305 if (GET_CODE (XEXP (X, 1)) == MULT) \
1306 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1307 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1308 && GET_CODE (XEXP (X, 0)) == REG) \
1309 goto WIN; \
1310 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1311 if (GET_CODE (XEXP (X, 0)) == REG \
1312 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1313 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1314 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1315 { register rtx temp = gen_reg_rtx (Pmode); \
1316 register rtx val = force_operand (XEXP (X, 1), 0); \
1317 emit_move_insn (temp, val); \
1318 COPY_ONCE (X); \
1319 XEXP (X, 1) = temp; \
1320 goto WIN; } \
1321 else if (GET_CODE (XEXP (X, 1)) == REG \
1322 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1323 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1324 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1325 { register rtx temp = gen_reg_rtx (Pmode); \
1326 register rtx val = force_operand (XEXP (X, 0), 0); \
1327 emit_move_insn (temp, val); \
1328 COPY_ONCE (X); \
1329 XEXP (X, 0) = temp; \
1330 goto WIN; }}}
1332 /* Go to LABEL if ADDR (a legitimate address expression)
1333 has an effect that depends on the machine mode it is used for.
1334 On the 68000, only predecrement and postincrement address depend thus
1335 (the amount of decrement or increment being the length of the operand). */
1337 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1338 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1339 \f
1340 /* Specify the machine mode that this machine uses
1341 for the index in the tablejump instruction. */
1342 #define CASE_VECTOR_MODE HImode
1344 /* Define as C expression which evaluates to nonzero if the tablejump
1345 instruction expects the table to contain offsets from the address of the
1346 table.
1347 Do not define this if the table should contain absolute addresses. */
1348 #define CASE_VECTOR_PC_RELATIVE 1
1350 /* Define this as 1 if `char' should by default be signed; else as 0. */
1351 #define DEFAULT_SIGNED_CHAR 1
1353 /* Don't cse the address of the function being compiled. */
1354 #define NO_RECURSIVE_FUNCTION_CSE
1356 /* Max number of bytes we can move from memory to memory
1357 in one reasonably fast instruction. */
1358 #define MOVE_MAX 4
1360 /* Nonzero if access to memory by bytes is slow and undesirable. */
1361 #define SLOW_BYTE_ACCESS 0
1363 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1364 is done just by pretending it is already truncated. */
1365 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1367 /* We assume that the store-condition-codes instructions store 0 for false
1368 and some other value for true. This is the value stored for true. */
1370 #define STORE_FLAG_VALUE (-1)
1372 /* When a prototype says `char' or `short', really pass an `int'. */
1373 #define PROMOTE_PROTOTYPES 1
1375 /* Specify the machine mode that pointers have.
1376 After generation of rtl, the compiler makes no further distinction
1377 between pointers and any other objects of this machine mode. */
1378 #define Pmode SImode
1380 /* A function address in a call instruction
1381 is a byte address (for indexing purposes)
1382 so give the MEM rtx a byte's mode. */
1383 #define FUNCTION_MODE QImode
1385 \f
1386 /* Tell final.c how to eliminate redundant test instructions. */
1388 /* Here we define machine-dependent flags and fields in cc_status
1389 (see `conditions.h'). */
1391 /* Set if the cc value is actually in the 68881, so a floating point
1392 conditional branch must be output. */
1393 #define CC_IN_68881 04000
1395 /* Store in cc_status the expressions that the condition codes will
1396 describe after execution of an instruction whose pattern is EXP.
1397 Do not alter them if the instruction would not alter the cc's. */
1399 /* On the 68000, all the insns to store in an address register fail to
1400 set the cc's. However, in some cases these instructions can make it
1401 possibly invalid to use the saved cc's. In those cases we clear out
1402 some or all of the saved cc's so they won't be used. */
1404 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1406 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1407 do { if (cc_prev_status.flags & CC_IN_68881) \
1408 return FLOAT; \
1409 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1410 return NO_OV; \
1411 return NORMAL; } while (0)
1412 \f
1413 /* Control the assembler format that we output. */
1415 /* Output to assembler file text saying following lines
1416 may contain character constants, extra white space, comments, etc. */
1420 /* Output to assembler file text saying following lines
1421 no longer contain unusual constructs. */
1425 /* Output before read-only data. */
1429 /* Output before writable data. */
1435 /* Here are four prefixes that are used by asm_fprintf to
1436 facilitate customization for alternate assembler syntaxes.
1437 Machines with no likelihood of an alternate syntax need not
1438 define these and need not use asm_fprintf. */
1440 /* The prefix for register names. Note that REGISTER_NAMES
1441 is supposed to include this prefix. */
1445 /* The prefix for local labels. You should be able to define this as
1446 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1447 without having to make any other changes to account for the specific
1448 definition. Note it is a string literal, not interpreted by printf
1449 and friends. */
1453 /* The prefix to add to user-visible assembler symbols. */
1457 /* The prefix for immediate operands. */
1461 /* How to refer to registers in assembler output.
1462 This sequence is indexed by compiler's hard-register-number (see above). */
1464 #define REGISTER_NAMES \
1469 /* How to renumber registers for dbx and gdb.
1470 On the Sun-3, the floating point registers have numbers
1471 18 to 25, not 16 to 23 as they do in the compiler. */
1473 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1475 /* Before the prologue, RA is at 0(%sp). */
1476 #define INCOMING_RETURN_ADDR_RTX \
1477 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1479 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1480 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1481 Instead use the identity mapping. */
1482 #define DWARF_FRAME_REGNUM(REG) REG
1484 /* Before the prologue, the top of the frame is at 4(%sp). */
1485 #define INCOMING_FRAME_SP_OFFSET 4
1487 /* Describe how we implement __builtin_eh_return. */
1488 #define EH_RETURN_DATA_REGNO(N) \
1489 ((N) < 2 ? (N) : INVALID_REGNUM)
1490 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1491 #define EH_RETURN_HANDLER_RTX \
1492 gen_rtx_MEM (Pmode, \
1493 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1494 plus_constant (EH_RETURN_STACKADJ_RTX, \
1495 UNITS_PER_WORD)))
1497 /* Select a format to encode pointers in exception handling data. CODE
1498 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1499 true if the symbol may be affected by dynamic relocations. */
1500 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1501 (flag_pic \
1502 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1503 : DW_EH_PE_absptr)
1505 /* This is how to output a reference to a user-level label named NAME.
1506 `assemble_name' uses this. */
1508 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1511 /* This is how to store into the string LABEL
1512 the symbol_ref name of an internal numbered label where
1513 PREFIX is the class of label and NUM is the number within the class.
1514 This is suitable for output with `assemble_name'. */
1516 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1519 /* This is how to output an insn to push a register on the stack.
1520 It need not be very fast code. */
1522 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1525 /* This is how to output an insn to pop a register from the stack.
1526 It need not be very fast code. */
1528 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1531 /* This is how to output an element of a case-vector that is absolute.
1532 (The 68000 does not use such vectors,
1533 but we must define this macro anyway.) */
1535 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1538 /* This is how to output an element of a case-vector that is relative. */
1540 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1543 /* This is how to output an assembler line
1544 that says to advance the location counter
1545 to a multiple of 2**LOG bytes. */
1547 /* We don't have a way to align to more than a two-byte boundary, so do the
1548 best we can and don't complain. */
1549 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1550 if ((LOG) >= 1) \
1553 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1556 /* This says how to output an assembler line
1557 to define a global common symbol. */
1559 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1561 assemble_name ((FILE), (NAME)), \
1564 /* This says how to output an assembler line
1565 to define a local common symbol. */
1567 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1569 assemble_name ((FILE), (NAME)), \
1572 /* Output a float value (represented as a C double) as an immediate operand.
1573 This macro is a 68k-specific macro. */
1575 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1576 do { \
1578 { \
1579 char dstr[30]; \
1580 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1582 } \
1583 else \
1584 { \
1585 long l; \
1586 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1588 } \
1589 } while (0)
1591 /* Output a double value (represented as a C double) as an immediate operand.
1592 This macro is a 68k-specific macro. */
1593 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1594 do { char dstr[30]; \
1595 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1597 } while (0)
1599 /* Note, long double immediate operands are not actually
1600 generated by m68k.md. */
1601 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1602 do { char dstr[30]; \
1603 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1605 } while (0)
1607 /* Print operand X (an rtx) in assembler syntax to file FILE.
1608 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1609 For `%' followed by punctuation, CODE is the punctuation and X is null.
1611 On the 68000, we use several CODE characters:
1612 '.' for dot needed in Motorola-style opcode names.
1613 '-' for an operand pushing on the stack:
1614 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1615 '+' for an operand pushing on the stack:
1616 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1617 '@' for a reference to the top word on the stack:
1618 sp@, (sp) or (%sp) depending on the style of syntax.
1619 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1620 but & in SGS syntax).
1621 '!' for the fpcr register (used in some float-to-fixed conversions).
1622 '$' for the letter `s' in an op code, but only on the 68040.
1623 '&' for the letter `d' in an op code, but only on the 68040.
1624 '/' for register prefix needed by longlong.h.
1626 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1627 'd' to force memory addressing to be absolute, not relative.
1628 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1629 'o' for operands to go directly to output_operand_address (bypassing
1630 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1631 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1632 or print pair of registers as rx:ry. */
1634 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1639 /* A C compound statement to output to stdio stream STREAM the
1640 assembler syntax for an instruction operand X. X is an RTL
1641 expression.
1643 CODE is a value that can be used to specify one of several ways
1644 of printing the operand. It is used when identical operands
1645 must be printed differently depending on the context. CODE
1646 comes from the `%' specification that was used to request
1647 printing of the operand. If the specification was just `%DIGIT'
1648 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1649 is the ASCII code for LTR.
1651 If X is a register, this macro should print the register's name.
1652 The names can be found in an array `reg_names' whose type is
1653 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1655 When the machine description has a specification `%PUNCT' (a `%'
1656 followed by a punctuation character), this macro is called with
1657 a null pointer for X and the punctuation character for CODE.
1659 See m68k.c for the m68k specific codes. */
1661 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1663 /* A C compound statement to output to stdio stream STREAM the
1664 assembler syntax for an instruction operand that is a memory
1665 reference whose address is ADDR. ADDR is an RTL expression. */
1667 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1669 /* Variables in m68k.c */
1679 \f
1680 /* Define the codes that are matched by predicates in m68k.c. */
1682 #define PREDICATE_CODES \
1684 LABEL_REF, SUBREG, REG, MEM}}, \
1692 GT, LT, GE, LE}}, \
1694 \f
1695 /*
1696 Local variables:
1697 version-control: t
1698 End:
1699 */