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Use DW_TAG_module for Ada
[official-gcc.git] / gcc / config / m68k / m68k.h
blob1aa89f1789b52b8ce0f3394b6b30b2f54cdfa973
1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987-2024 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
21 if-statements and ?: on it. This way we have compile-time error checking
22 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
23 to optimize away all constant tests. */
24 #if MOTOROLA /* Use the Motorola assembly syntax. */
25 #else
26 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
27 #endif
28
29 /* Handle --with-cpu default option from configure script. */
30 #define OPTION_DEFAULT_SPECS \
31 { "cpu", "%{!m68020-40:%{!m68020-60:\
32 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}" },
33
34 /* Pass flags to gas indicating which type of processor we have. This
35 can be simplified when we can rely on the assembler supporting .cpu
36 and .arch directives. */
37
38 #define ASM_CPU_SPEC "\
39 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
40 %{m68020-40:-m68040}%{m68020-60:-m68040}\
41 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
42 "
43 #define ASM_PCREL_SPEC "%{" FPIE_OR_FPIC_SPEC ":--pcrel} \
44 %{mpcrel:%{" NO_FPIE_AND_FPIC_SPEC ":--pcrel}} \
45 %{msep-data|mid-shared-library:--pcrel} \
46 "
47
48 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)"
49
50 #define EXTRA_SPECS \
51 { "asm_cpu_spec", ASM_CPU_SPEC }, \
52 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \
53 SUBTARGET_EXTRA_SPECS
54
55 #define SUBTARGET_EXTRA_SPECS
56
57 /* Note that some other tm.h files include this one and then override
58 many of the definitions that relate to assembler syntax. */
59
60 #define TARGET_CPU_CPP_BUILTINS() \
61 do \
62 { \
63 builtin_define ("__m68k__"); \
64 builtin_define_std ("mc68000"); \
65 /* The other mc680x0 macros have traditionally been derived \
66 from the tuning setting. For example, -m68020-60 defines \
67 m68060, even though it generates pure 68020 code. */ \
68 switch (m68k_tune) \
69 { \
70 case u68010: \
71 builtin_define_std ("mc68010"); \
72 break; \
73 \
74 case u68020: \
75 builtin_define_std ("mc68020"); \
76 break; \
77 \
78 case u68030: \
79 builtin_define_std ("mc68030"); \
80 break; \
81 \
82 case u68040: \
83 builtin_define_std ("mc68040"); \
84 break; \
85 \
86 case u68060: \
87 builtin_define_std ("mc68060"); \
88 break; \
89 \
90 case u68020_60: \
91 builtin_define_std ("mc68060"); \
92 /* Fall through. */ \
93 case u68020_40: \
94 builtin_define_std ("mc68040"); \
95 builtin_define_std ("mc68030"); \
96 builtin_define_std ("mc68020"); \
97 break; \
98 \
99 case ucpu32: \
100 builtin_define_std ("mc68332"); \
101 builtin_define_std ("mcpu32"); \
102 builtin_define_std ("mc68020"); \
103 break; \
104 \
105 case ucfv1: \
106 builtin_define ("__mcfv1__"); \
107 break; \
108 \
109 case ucfv2: \
110 builtin_define ("__mcfv2__"); \
111 break; \
112 \
113 case ucfv3: \
114 builtin_define ("__mcfv3__"); \
115 break; \
116 \
117 case ucfv4: \
118 builtin_define ("__mcfv4__"); \
119 break; \
120 \
121 case ucfv4e: \
122 builtin_define ("__mcfv4e__"); \
123 break; \
124 \
125 case ucfv5: \
126 builtin_define ("__mcfv5__"); \
127 break; \
128 \
129 default: \
130 break; \
131 } \
132 \
133 if (TARGET_68881) \
134 builtin_define ("__HAVE_68881__"); \
135 \
136 if (TARGET_COLDFIRE) \
137 { \
138 const char *tmp; \
139 \
140 tmp = m68k_cpp_cpu_ident ("cf"); \
141 if (tmp) \
142 builtin_define (tmp); \
143 tmp = m68k_cpp_cpu_family ("cf"); \
144 if (tmp) \
145 builtin_define (tmp); \
146 builtin_define ("__mcoldfire__"); \
147 \
148 if (TARGET_ISAC) \
149 builtin_define ("__mcfisac__"); \
150 else if (TARGET_ISAB) \
151 { \
152 builtin_define ("__mcfisab__"); \
153 /* ISA_B: Legacy 5407 defines. */ \
154 builtin_define ("__mcf5400__"); \
155 builtin_define ("__mcf5407__"); \
156 } \
157 else if (TARGET_ISAAPLUS) \
158 { \
159 builtin_define ("__mcfisaaplus__"); \
160 /* ISA_A+: legacy defines. */ \
161 builtin_define ("__mcf528x__"); \
162 builtin_define ("__mcf5200__"); \
163 } \
164 else \
165 { \
166 builtin_define ("__mcfisaa__"); \
167 /* ISA_A: legacy defines. */ \
168 switch (m68k_tune) \
169 { \
170 case ucfv2: \
171 builtin_define ("__mcf5200__"); \
172 break; \
173 \
174 case ucfv3: \
175 builtin_define ("__mcf5307__"); \
176 builtin_define ("__mcf5300__"); \
177 break; \
178 \
179 default: \
180 break; \
181 } \
182 } \
183 } \
184 \
185 if (TARGET_COLDFIRE_FPU) \
186 builtin_define ("__mcffpu__"); \
187 \
188 if (TARGET_CF_HWDIV) \
189 builtin_define ("__mcfhwdiv__"); \
190 \
191 if (TARGET_FIDOA) \
192 builtin_define ("__mfido__"); \
193 \
194 builtin_assert ("cpu=m68k"); \
195 builtin_assert ("machine=m68k"); \
196 } \
197 while (0)
198
199 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
200 quantities. */
201 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
202 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
203 #define INT_OP_NO_DOT 2 /* byte, short, long */
204 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
205
206 /* Set the default. */
207 #define INT_OP_GROUP INT_OP_DOT_WORD
208
209 /* Bit values used by m68k-devices.def to identify processor capabilities. */
210 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
211 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
212 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
213 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
214 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
215 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
216 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
217 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
218 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
219 #define FL_ISA_68000 (1 << 9)
220 #define FL_ISA_68010 (1 << 10)
221 #define FL_ISA_68020 (1 << 11)
222 #define FL_ISA_68040 (1 << 12)
223 #define FL_ISA_A (1 << 13)
224 #define FL_ISA_APLUS (1 << 14)
225 #define FL_ISA_B (1 << 15)
226 #define FL_ISA_C (1 << 16)
227 #define FL_FIDOA (1 << 17)
228 #define FL_CAS (1 << 18) /* Support cas insn. */
229 #define FL_MMU 0 /* Used by multilib machinery. */
230 #define FL_UCLINUX 0 /* Used by multilib machinery. */
231
232 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
233 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
234 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
235 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
236 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
237 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
238 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0)
239 #define TARGET_CAS ((m68k_cpu_flags & FL_CAS) != 0)
240
241 /* Size (in bytes) of FPU registers. */
242 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
243
244 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
245 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
246 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
247
248 /* Some instructions are common to more than one ISA. */
249 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC)
250 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC)
251 #define ISA_HAS_TAS (!TARGET_COLDFIRE || TARGET_ISAB || TARGET_ISAC)
252
253 #define TUNE_68000 (m68k_tune == u68000)
254 #define TUNE_68010 (m68k_tune == u68010)
255 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
256 #define TUNE_68030 (m68k_tune == u68030 \
257 || m68k_tune == u68020_40 \
258 || m68k_tune == u68020_60)
259 #define TUNE_68040 (m68k_tune == u68040 \
260 || m68k_tune == u68020_40 \
261 || m68k_tune == u68020_60)
262 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
263 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
264 #define TUNE_CPU32 (m68k_tune == ucpu32)
265 #define TUNE_CFV1 (m68k_tune == ucfv1)
266 #define TUNE_CFV2 (m68k_tune == ucfv2)
267 #define TUNE_CFV3 (m68k_tune == ucfv3)
268 #define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e)
269
270 #define TUNE_MAC ((m68k_tune_flags & FL_CF_MAC) != 0)
271 #define TUNE_EMAC ((m68k_tune_flags & FL_CF_EMAC) != 0)
272
273 /* These are meant to be redefined in the host dependent files */
274 #define SUBTARGET_OVERRIDE_OPTIONS
275 \f
276 /* target machine storage layout */
277
278 /* "long double" is the same as "double" on ColdFire and fido
279 targets. */
280
281 #define LONG_DOUBLE_TYPE_SIZE \
282 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80)
283
284 #define BITS_BIG_ENDIAN 1
285 #define BYTES_BIG_ENDIAN 1
286 #define WORDS_BIG_ENDIAN 1
287
288 #define UNITS_PER_WORD 4
289
290 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
291 #define STACK_BOUNDARY 16
292 #define FUNCTION_BOUNDARY 16
293 #define EMPTY_FIELD_BOUNDARY 16
294 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */
295 #define PREFERRED_STACK_BOUNDARY \
296 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16)
297
298 /* No data type wants to be aligned rounder than this.
299 Most published ABIs say that ints should be aligned on 16-bit
300 boundaries, but CPUs with 32-bit busses get better performance
301 aligned on 32-bit boundaries. */
302 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
303
304 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
305 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1
306
307 #define DWARF_CIE_DATA_ALIGNMENT -2
308
309 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
310
311 /* Define these to avoid dependence on meaning of `int'. */
312 #define WCHAR_TYPE "long int"
313 #define WCHAR_TYPE_SIZE 32
314
315 /* Maximum number of library IDs we permit with -mid-shared-library. */
316 #define MAX_LIBRARY_ID 255
317
318 \f
319 /* Standard register usage. */
320
321 /* For the m68k, we give the data registers numbers 0-7,
322 the address registers numbers 010-017 (8-15),
323 and the 68881 floating point registers numbers 020-027 (16-23).
324 We also have a fake `arg-pointer' register 030 (24) used for
325 register elimination. */
326 #define FIRST_PSEUDO_REGISTER 25
327
328 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
329 #define PIC_OFFSET_TABLE_REGNUM \
330 (!flag_pic ? INVALID_REGNUM \
331 : reload_completed ? REGNO (pic_offset_table_rtx) \
332 : PIC_REG)
333
334 /* 1 for registers that have pervasive standard uses
335 and are not available for the register allocator.
336 On the m68k, only the stack pointer is such.
337 Our fake arg-pointer is obviously fixed as well. */
338 #define FIXED_REGISTERS \
339 {/* Data registers. */ \
340 0, 0, 0, 0, 0, 0, 0, 0, \
341 \
342 /* Address registers. */ \
343 0, 0, 0, 0, 0, 0, 0, 1, \
344 \
345 /* Floating point registers \
346 (if available). */ \
347 0, 0, 0, 0, 0, 0, 0, 0, \
348 \
349 /* Arg pointer. */ \
350 1 }
351
352 /* 1 for registers not available across function calls.
353 These must include the FIXED_REGISTERS and also any
354 registers that can be used without being saved.
355 The latter must include the registers where values are returned
356 and the register where structure-value addresses are passed.
357 Aside from that, you can include as many other registers as you like. */
358 #define CALL_USED_REGISTERS \
359 {/* Data registers. */ \
360 1, 1, 0, 0, 0, 0, 0, 0, \
361 \
362 /* Address registers. */ \
363 1, 1, 0, 0, 0, 0, 0, 1, \
364 \
365 /* Floating point registers \
366 (if available). */ \
367 1, 1, 0, 0, 0, 0, 0, 0, \
368 \
369 /* Arg pointer. */ \
370 1 }
371
372 #define REG_ALLOC_ORDER \
373 { /* d0/d1/a0/a1 */ \
374 0, 1, 8, 9, \
375 /* d2-d7 */ \
376 2, 3, 4, 5, 6, 7, \
377 /* a2-a7/arg */ \
378 10, 11, 12, 13, 14, 15, 24, \
379 /* fp0-fp7 */ \
380 16, 17, 18, 19, 20, 21, 22, 23\
381 }
382
383
384 /* A C expression that is nonzero if hard register NEW_REG can be
385 considered for use as a rename register for OLD_REG register. */
386
387 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
388 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
389
390 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
391 m68k_secondary_reload_class (CLASS, MODE, X)
392
393 /* Specify the registers used for certain standard purposes.
394 The values of these macros are register numbers. */
395
396 #define STACK_POINTER_REGNUM SP_REG
397
398 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
399 ABI uses %a6 for shared library calls, therefore the frame
400 pointer is shifted to %a5 on this target. */
401 #define FRAME_POINTER_REGNUM A6_REG
402
403 /* Base register for access to arguments of the function.
404 * This isn't a hardware register. It will be eliminated to the
405 * stack pointer or frame pointer.
406 */
407 #define ARG_POINTER_REGNUM 24
408
409 #define STATIC_CHAIN_REGNUM A0_REG
410 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
411
412 /* Register in which address to store a structure value
413 is passed to a function. */
414 #define M68K_STRUCT_VALUE_REGNUM A1_REG
415
416 \f
417
418 /* The m68k has three kinds of registers, so eight classes would be
419 a complete set. One of them is not needed. */
420 enum reg_class {
421 NO_REGS, DATA_REGS,
422 ADDR_REGS, FP_REGS,
423 GENERAL_REGS, DATA_OR_FP_REGS,
424 ADDR_OR_FP_REGS, ALL_REGS,
425 LIM_REG_CLASSES };
426
427 #define N_REG_CLASSES (int) LIM_REG_CLASSES
428
429 #define REG_CLASS_NAMES \
430 { "NO_REGS", "DATA_REGS", \
431 "ADDR_REGS", "FP_REGS", \
432 "GENERAL_REGS", "DATA_OR_FP_REGS", \
433 "ADDR_OR_FP_REGS", "ALL_REGS" }
434
435 #define REG_CLASS_CONTENTS \
436 { \
437 {0x00000000}, /* NO_REGS */ \
438 {0x000000ff}, /* DATA_REGS */ \
439 {0x0100ff00}, /* ADDR_REGS */ \
440 {0x00ff0000}, /* FP_REGS */ \
441 {0x0100ffff}, /* GENERAL_REGS */ \
442 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
443 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
444 {0x01ffffff}, /* ALL_REGS */ \
445 }
446
447 extern enum reg_class regno_reg_class[];
448 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
449 #define INDEX_REG_CLASS GENERAL_REGS
450 #define BASE_REG_CLASS ADDR_REGS
451
452 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
453 m68k_preferred_reload_class (X, CLASS)
454
455 /* On the m68k, this is the size of MODE in words,
456 except in the FP regs, where a single reg is always enough. */
457 #define CLASS_MAX_NREGS(CLASS, MODE) \
458 ((CLASS) == FP_REGS ? 1 \
459 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
460
461 /* Moves between fp regs and other regs are two insns. */
462 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
463 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
464
465 \f
466 /* Stack layout; function entry, exit and calling. */
467
468 #define STACK_GROWS_DOWNWARD 1
469 #define FRAME_GROWS_DOWNWARD 1
470
471 #define PUSH_ROUNDING(BYTES) m68k_push_rounding (BYTES)
472
473 #define FIRST_PARM_OFFSET(FNDECL) 8
474
475 /* On the m68k the return value defaults to D0. */
476 #define FUNCTION_VALUE(VALTYPE, FUNC) \
477 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG)
478
479 /* On the m68k the return value defaults to D0. */
480 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG)
481
482 /* On the m68k, D0 is usually the only register used. */
483 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG)
484
485 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
486 more than one register.
487 XXX This macro is m68k specific and used only for m68kemb.h. */
488 #define NEEDS_UNTYPED_CALL 0
489
490 /* On the m68k, all arguments are usually pushed on the stack. */
491 #define FUNCTION_ARG_REGNO_P(N) 0
492 \f
493 /* On the m68k, this is a single integer, which is a number of bytes
494 of arguments scanned so far. */
495 #define CUMULATIVE_ARGS int
496
497 /* On the m68k, the offset starts at 0. */
498 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
499 ((CUM) = 0)
500
501 #define FUNCTION_PROFILER(FILE, LABELNO) \
502 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
503
504 #define EXIT_IGNORE_STACK 1
505
506 /* Output assembler code for a block containing the constant parts
507 of a trampoline, leaving space for the variable parts.
508
509 On the m68k, the trampoline looks like this:
510 movl #STATIC,a0
511 jmp FUNCTION
512
513 WARNING: Targets that may run on 68040+ cpus must arrange for
514 the instruction cache to be flushed. Previous incarnations of
515 the m68k trampoline code attempted to get around this by either
516 using an out-of-line transfer function or pc-relative data, but
517 the fact remains that the code to jump to the transfer function
518 or the code to load the pc-relative data needs to be flushed
519 just as much as the "variable" portion of the trampoline.
520 Recognizing that a cache flush is going to be required anyway,
521 dispense with such notions and build a smaller trampoline.
522
523 Since more instructions are required to move a template into
524 place than to create it on the spot, don't use a template. */
525
526 #define TRAMPOLINE_SIZE 12
527 #define TRAMPOLINE_ALIGNMENT 16
528
529 /* Targets redefine this to invoke code to either flush the cache,
530 or enable stack execution (or both). */
531 #ifndef FINALIZE_TRAMPOLINE
532 #define FINALIZE_TRAMPOLINE(TRAMP)
533 #endif
534
535 /* This is the library routine that is used to transfer control from the
536 trampoline to the actual nested function. It is defined for backward
537 compatibility, for linking with object code that used the old trampoline
538 definition.
539
540 A colon is used with no explicit operands to cause the template string
541 to be scanned for %-constructs.
542
543 The function name __transfer_from_trampoline is not actually used.
544 The function definition just permits use of "asm with operands"
545 (though the operand list is empty). */
546 #define TRANSFER_FROM_TRAMPOLINE \
547 void \
548 __transfer_from_trampoline () \
549 { \
550 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
551 asm (GLOBAL_ASM_OP "___trampoline"); \
552 asm ("___trampoline:"); \
553 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
554 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
555 asm ("rts":); \
556 }
557 \f
558 /* There are two registers that can always be eliminated on the m68k.
559 The frame pointer and the arg pointer can be replaced by either the
560 hard frame pointer or to the stack pointer, depending upon the
561 circumstances. The hard frame pointer is not used before reload and
562 so it is not eligible for elimination. */
563 #define ELIMINABLE_REGS \
564 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
565 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
566 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
567
568 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
569 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
570 \f
571 /* Addressing modes, and classification of registers for them. */
572
573 #define HAVE_POST_INCREMENT 1
574 #define HAVE_PRE_DECREMENT 1
575
576 /* Macros to check register numbers against specific register classes. */
577
578 /* True for data registers, D0 through D7. */
579 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7)
580
581 /* True for address registers, A0 through A7. */
582 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15)
583
584 /* True for integer registers, D0 through D7 and A0 through A7. */
585 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15)
586
587 /* True for floating point registers, FP0 through FP7. */
588 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23)
589
590 #define REGNO_OK_FOR_INDEX_P(REGNO) \
591 (INT_REGNO_P (REGNO) \
592 || INT_REGNO_P (reg_renumber[REGNO]))
593
594 #define REGNO_OK_FOR_BASE_P(REGNO) \
595 (ADDRESS_REGNO_P (REGNO) \
596 || ADDRESS_REGNO_P (reg_renumber[REGNO]))
597
598 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
599 (INT_REGNO_P (REGNO) \
600 || REGNO == ARG_POINTER_REGNUM \
601 || REGNO >= FIRST_PSEUDO_REGISTER)
602
603 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
604 (ADDRESS_REGNO_P (REGNO) \
605 || REGNO == ARG_POINTER_REGNUM \
606 || REGNO >= FIRST_PSEUDO_REGISTER)
607
608 /* Now macros that check whether X is a register and also,
609 strictly, whether it is in a specified class.
610
611 These macros are specific to the m68k, and may be used only
612 in code for printing assembler insns and in conditions for
613 define_optimization. */
614
615 /* 1 if X is a data register. */
616 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X)))
617
618 /* 1 if X is an fp register. */
619 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
620
621 /* 1 if X is an address register */
622 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X)))
623 \f
624 /* True if SYMBOL + OFFSET constants must refer to something within
625 SYMBOL's section. */
626 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
627 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
628 #endif
629
630 #define MAX_REGS_PER_ADDRESS 2
631
632 #define CONSTANT_ADDRESS_P(X) \
633 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
634 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
635 || GET_CODE (X) == HIGH) \
636 && m68k_legitimate_constant_p (Pmode, X))
637
638 #ifndef REG_OK_STRICT
639 #define REG_STRICT_P 0
640 #else
641 #define REG_STRICT_P 1
642 #endif
643
644 #define LEGITIMATE_PIC_OPERAND_P(X) \
645 (!symbolic_operand (X, VOIDmode) \
646 || (TARGET_PCREL && REG_STRICT_P) \
647 || m68k_tls_reference_p (X, true))
648
649 #define REG_OK_FOR_BASE_P(X) \
650 m68k_legitimate_base_reg_p (X, REG_STRICT_P)
651
652 #define REG_OK_FOR_INDEX_P(X) \
653 m68k_legitimate_index_reg_p (X, REG_STRICT_P)
654
655 \f
656 /* This address is OK as it stands. */
657 #define PIC_CASE_VECTOR_ADDRESS(index) index
658 #define CASE_VECTOR_MODE (TARGET_LONG_JUMP_TABLE_OFFSETS ? SImode : HImode)
659 #define CASE_VECTOR_PC_RELATIVE 1
660
661 #define DEFAULT_SIGNED_CHAR 1
662 #define MOVE_MAX 4
663 #define SLOW_BYTE_ACCESS 0
664
665 /* The 68020 BFFFO and ColdFire FF1 instructions return 32 for zero. */
666 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
667
668 #define STORE_FLAG_VALUE (-1)
669
670 #define Pmode SImode
671 #define FUNCTION_MODE QImode
672
673 \f
674 /* Control the assembler format that we output. */
675
676 #define ASM_APP_ON "#APP\n"
677 #define ASM_APP_OFF "#NO_APP\n"
678 #define TEXT_SECTION_ASM_OP "\t.text"
679 #define DATA_SECTION_ASM_OP "\t.data"
680 #define GLOBAL_ASM_OP "\t.globl\t"
681 #define REGISTER_PREFIX ""
682 #define LOCAL_LABEL_PREFIX ""
683 #define USER_LABEL_PREFIX "_"
684 #define IMMEDIATE_PREFIX "#"
685
686 #define REGISTER_NAMES \
687 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
688 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
689 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
690 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
691 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
692 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
693 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
694 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
695 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
696
697 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
698
699 /* Return a register name by index, handling %fp nicely.
700 We don't replace %fp for targets that don't map it to %a6
701 since it may confuse GAS. */
702 #define M68K_REGNAME(r) ( \
703 ((FRAME_POINTER_REGNUM == A6_REG) \
704 && ((r) == FRAME_POINTER_REGNUM) \
705 && frame_pointer_needed) ? \
706 M68K_FP_REG_NAME : reg_names[(r)])
707
708 /* On the Sun-3, the floating point registers have numbers
709 18 to 25, not 16 to 23 as they do in the compiler. */
710 #define DEBUGGER_REGNO(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
711
712 /* Before the prologue, RA is at 0(%sp). */
713 #define INCOMING_RETURN_ADDR_RTX \
714 gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM))
715
716 /* After the prologue, RA is at 4(AP) in the current frame. */
717 #define RETURN_ADDR_RTX(COUNT, FRAME) \
718 ((COUNT) == 0 \
719 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
720 UNITS_PER_WORD)) \
721 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD)))
722
723 /* We must not use the debugger register numbers for the DWARF 2 CFA column
724 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
725 Instead use the identity mapping. */
726 #define DWARF_FRAME_REGNUM(REG) \
727 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM)
728
729 /* The return column was originally 24, but gcc used 25 for a while too.
730 Define both registers 24 and 25 as Pmode ones and use 24 in our own
731 unwind information. */
732 #define DWARF_FRAME_REGISTERS 25
733 #define DWARF_FRAME_RETURN_COLUMN 24
734 #define DWARF_ALT_FRAME_RETURN_COLUMN 25
735
736 /* Before the prologue, the top of the frame is at 4(%sp). */
737 #define INCOMING_FRAME_SP_OFFSET 4
738
739 #define EPILOGUE_USES(REGNO) m68k_epilogue_uses (REGNO)
740
741 /* Describe how we implement __builtin_eh_return. */
742 #define EH_RETURN_DATA_REGNO(N) \
743 ((N) < 2 ? (N) : INVALID_REGNUM)
744 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG)
745 #define EH_RETURN_HANDLER_RTX \
746 gen_rtx_MEM (Pmode, \
747 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
748 plus_constant (Pmode, EH_RETURN_STACKADJ_RTX, \
749 UNITS_PER_WORD)))
750
751 /* Select a format to encode pointers in exception handling data. CODE
752 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
753 true if the symbol may be affected by dynamic relocations.
754
755 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
756 a read-only text segment without imposing a fixed gap between the
757 text and data segments. As a result, the text segment cannot refer
758 to anything in the data segment, even in PC-relative form. Because
759 .eh_frame refers to both code and data, it follows that .eh_frame
760 must be in the data segment itself, and that the offset between
761 .eh_frame and code will not be a link-time constant.
762
763 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
764 | DW_EH_PE_indirect for all code references. However, gcc currently
765 handles indirect references using a per-TU constant pool. This means
766 that if a function and its eh_frame are removed by the linker, the
767 eh_frame's indirect references to the removed function will not be
768 removed, leading to an unresolved symbol error.
769
770 It isn't clear that any -msep-data or -mid-shared-library target
771 would benefit from a read-only .eh_frame anyway. In particular,
772 no known target that supports these options has a feature like
773 PT_GNU_RELRO. Without any such feature to motivate them, indirect
774 references would be unnecessary bloat, so we simply use an absolute
775 pointer for code and global references. We still use pc-relative
776 references to data, as this avoids a relocation. */
777 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
778 (flag_pic \
779 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \
780 && ((GLOBAL) || (CODE))) \
781 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
782 : DW_EH_PE_absptr)
783
784 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
785 asm_fprintf (FILE, "%U%s", NAME)
786
787 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
788 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
789
790 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
791 asm_fprintf (FILE, (MOTOROLA \
792 ? "\tmove.l %s,-(%Rsp)\n" \
793 : "\tmovel %s,%Rsp@-\n"), \
794 reg_names[REGNO])
795
796 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
797 asm_fprintf (FILE, (MOTOROLA \
798 ? "\tmove.l (%Rsp)+,%s\n" \
799 : "\tmovel %Rsp@+,%s\n"), \
800 reg_names[REGNO])
801
802 /* The m68k does not use absolute case-vectors, but we must define this macro
803 anyway. */
804 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
805 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
806
807 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
808 asm_fprintf (FILE, \
809 TARGET_LONG_JUMP_TABLE_OFFSETS \
810 ? "\t.long %LL%d-%LL%d\n" \
811 : "\t.word %LL%d-%LL%d\n", \
812 VALUE, REL)
813
814 /* We don't have a way to align to more than a two-byte boundary, so do the
815 best we can and don't complain. */
816 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
817 if ((LOG) >= 1) \
818 fprintf (FILE, "\t.even\n");
819
820 #ifdef HAVE_GAS_BALIGN_AND_P2ALIGN
821 /* Use "move.l %a4,%a4" to advance within code. */
822 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
823 if ((LOG) > 0) \
824 fprintf ((FILE), "\t.balignw %u,0x284c\n", 1 << (LOG));
825 #endif
826
827 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
828 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
829
830 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
831 ( fputs (".comm ", (FILE)), \
832 assemble_name ((FILE), (NAME)), \
833 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
834
835 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
836 ( fputs (".lcomm ", (FILE)), \
837 assemble_name ((FILE), (NAME)), \
838 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
839
840 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
841 m68k_final_prescan_insn (INSN, OPVEC, NOPERANDS)
842
843 /* On the 68000, we use several CODE characters:
844 '.' for dot needed in Motorola-style opcode names.
845 '-' for an operand pushing on the stack:
846 sp@-, -(sp) or -(%sp) depending on the style of syntax.
847 '+' for an operand pushing on the stack:
848 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
849 '@' for a reference to the top word on the stack:
850 sp@, (sp) or (%sp) depending on the style of syntax.
851 '#' for an immediate operand prefix (# in MIT and Motorola syntax
852 but & in SGS syntax).
853 '!' for the fpcr register (used in some float-to-fixed conversions).
854 '$' for the letter `s' in an op code, but only on the 68040.
855 '&' for the letter `d' in an op code, but only on the 68040.
856 '/' for register prefix needed by longlong.h.
857 '?' for m68k_library_id_string
858
859 'b' for byte insn (no effect, on the Sun; this is for the ISI).
860 'd' to force memory addressing to be absolute, not relative.
861 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
862 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
863 or print pair of registers as rx:ry. */
864
865 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
866 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
867 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
868 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?')
869
870
871 /* See m68k.cc for the m68k specific codes. */
872 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
873
874 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
875
876 #define CC_STATUS_INIT m68k_init_cc ()
877
878 #include "config/m68k/m68k-opts.h"
879
880 enum fpu_type
881 {
882 FPUTYPE_NONE,
883 FPUTYPE_68881,
884 FPUTYPE_COLDFIRE
885 };
886
887 enum m68k_function_kind
888 {
889 m68k_fk_normal_function,
890 m68k_fk_interrupt_handler,
891 m68k_fk_interrupt_thread
892 };
893
894 /* Variables in m68k.cc; see there for details. */
895 extern enum target_device m68k_cpu;
896 extern enum uarch_type m68k_tune;
897 extern enum fpu_type m68k_fpu;
898 extern unsigned int m68k_cpu_flags;
899 extern unsigned int m68k_tune_flags;
900 extern const char *m68k_symbolic_call;
901 extern const char *m68k_symbolic_jump;
902
903 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR,
904 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P };
905
906 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
907
908 /* ??? HOST_WIDE_INT is not being defined for auto-generated files.
909 Workaround that. */
910 #ifdef HOST_WIDE_INT
911 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ }
912 M68K_CONST_METHOD;
913
914 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT);
915 #endif
916
917 extern void m68k_emit_move_double (rtx [2]);
918
919 extern int m68k_sched_address_bypass_p (rtx_insn *, rtx_insn *);
920 extern int m68k_sched_indexed_address_bypass_p (rtx_insn *, rtx_insn *);
921
922 #define CPU_UNITS_QUERY 1
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