1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2023 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
119 #include "memmodel.h"
127 #include "addresses.h"
130 #include "rtl-error.h"
133 #include "print-rtl.h"
134 #include "function-abi.h"
135 #include "rtl-iter.h"
137 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
138 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
140 static int bb_reload_num
;
142 /* The current insn being processed and corresponding its single set
143 (NULL otherwise), its data (basic block, the insn data, the insn
144 static data, and the mode of each operand). */
145 static rtx_insn
*curr_insn
;
146 static rtx curr_insn_set
;
147 static basic_block curr_bb
;
148 static lra_insn_recog_data_t curr_id
;
149 static struct lra_static_insn_data
*curr_static_id
;
150 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
151 /* Mode of the register substituted by its equivalence with VOIDmode
152 (e.g. constant) and whose subreg is given operand of the current
153 insn. VOIDmode in all other cases. */
154 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
158 /* Start numbers for new registers and insns at the current constraints
160 static int new_regno_start
;
161 static int new_insn_uid_start
;
163 /* If LOC is nonnull, strip any outer subreg from it. */
165 strip_subreg (rtx
*loc
)
167 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
170 /* Return hard regno of REGNO or if it is was not assigned to a hard
171 register, use a hard register from its allocno class. */
173 get_try_hard_regno (int regno
)
176 enum reg_class rclass
;
178 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
179 hard_regno
= lra_get_regno_hard_regno (regno
);
182 rclass
= lra_get_allocno_class (regno
);
183 if (rclass
== NO_REGS
)
185 return ira_class_hard_regs
[rclass
][0];
188 /* Return the hard regno of X after removing its subreg. If X is not a
189 register or a subreg of a register, return -1. If X is a pseudo, use its
190 assignment. If X is a hard regno, return the final hard regno which will be
191 after elimination. */
193 get_hard_regno (rtx x
)
200 reg
= SUBREG_REG (x
);
203 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
204 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
207 if (HARD_REGISTER_NUM_P (REGNO (reg
)))
208 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
210 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
211 SUBREG_BYTE (x
), GET_MODE (x
));
215 /* If REGNO is a hard register or has been allocated a hard register,
216 return the class of that register. If REGNO is a reload pseudo
217 created by the current constraints pass, return its allocno class.
218 Return NO_REGS otherwise. */
219 static enum reg_class
220 get_reg_class (int regno
)
224 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
225 hard_regno
= lra_get_regno_hard_regno (regno
);
228 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
229 return REGNO_REG_CLASS (hard_regno
);
231 if (regno
>= new_regno_start
)
232 return lra_get_allocno_class (regno
);
236 /* Return true if REG_CLASS has enough allocatable hard regs to keep value of
239 enough_allocatable_hard_regs_p (enum reg_class reg_class
,
240 enum machine_mode reg_mode
)
242 int i
, j
, hard_regno
, class_size
, nregs
;
244 if (hard_reg_set_subset_p (reg_class_contents
[reg_class
], lra_no_alloc_regs
))
246 class_size
= ira_class_hard_regs_num
[reg_class
];
247 for (i
= 0; i
< class_size
; i
++)
249 hard_regno
= ira_class_hard_regs
[reg_class
][i
];
250 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
253 for (j
= 0; j
< nregs
; j
++)
254 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
255 || ! TEST_HARD_REG_BIT (reg_class_contents
[reg_class
],
264 /* Return true if REG satisfies (or will satisfy) reg class constraint
265 CL. Use elimination first if REG is a hard register. If REG is a
266 reload pseudo created by this constraints pass, assume that it will
267 be allocated a hard register from its allocno class, but allow that
268 class to be narrowed to CL if it is currently a superset of CL and
271 - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or
272 - the instruction we're processing is not a reload move.
274 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
275 REGNO (reg), or NO_REGS if no change in its class was needed. */
277 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
,
278 bool allow_all_reload_class_changes_p
= false)
280 enum reg_class rclass
, common_class
;
281 machine_mode reg_mode
;
283 int regno
= REGNO (reg
);
285 if (new_class
!= NULL
)
286 *new_class
= NO_REGS
;
287 if (regno
< FIRST_PSEUDO_REGISTER
)
290 rtx
*final_loc
= &final_reg
;
292 lra_eliminate_reg_if_possible (final_loc
);
293 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
295 reg_mode
= GET_MODE (reg
);
296 rclass
= get_reg_class (regno
);
297 src
= curr_insn_set
!= NULL
? SET_SRC (curr_insn_set
) : NULL
;
298 if (regno
< new_regno_start
299 /* Do not allow the constraints for reload instructions to
300 influence the classes of new pseudos. These reloads are
301 typically moves that have many alternatives, and restricting
302 reload pseudos for one alternative may lead to situations
303 where other reload pseudos are no longer allocatable. */
304 || (!allow_all_reload_class_changes_p
305 && INSN_UID (curr_insn
) >= new_insn_uid_start
307 && ((REG_P (src
) || MEM_P (src
))
308 || (GET_CODE (src
) == SUBREG
309 && (REG_P (SUBREG_REG (src
)) || MEM_P (SUBREG_REG (src
)))))))
310 /* When we don't know what class will be used finally for reload
311 pseudos, we use ALL_REGS. */
312 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
313 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
314 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
315 lra_no_alloc_regs
)));
318 common_class
= ira_reg_class_subset
[rclass
][cl
];
319 if (new_class
!= NULL
)
320 *new_class
= common_class
;
321 return enough_allocatable_hard_regs_p (common_class
, reg_mode
);
325 /* Return true if REGNO satisfies a memory constraint. */
329 return get_reg_class (regno
) == NO_REGS
;
332 /* Return true if ADDR is a valid memory address for mode MODE in address
333 space AS, and check that each pseudo has the proper kind of hard
336 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
337 rtx addr
, addr_space_t as
)
339 #ifdef GO_IF_LEGITIMATE_ADDRESS
340 lra_assert (ADDR_SPACE_GENERIC_P (as
));
341 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
347 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
,
353 /* Temporarily eliminates registers in an address (for the lifetime of
355 class address_eliminator
{
357 address_eliminator (struct address_info
*ad
);
358 ~address_eliminator ();
361 struct address_info
*m_ad
;
369 address_eliminator::address_eliminator (struct address_info
*ad
)
371 m_base_loc (strip_subreg (ad
->base_term
)),
372 m_base_reg (NULL_RTX
),
373 m_index_loc (strip_subreg (ad
->index_term
)),
374 m_index_reg (NULL_RTX
)
376 if (m_base_loc
!= NULL
)
378 m_base_reg
= *m_base_loc
;
379 /* If we have non-legitimate address which is decomposed not in
380 the way we expected, don't do elimination here. In such case
381 the address will be reloaded and elimination will be done in
382 reload insn finally. */
383 if (REG_P (m_base_reg
))
384 lra_eliminate_reg_if_possible (m_base_loc
);
385 if (m_ad
->base_term2
!= NULL
)
386 *m_ad
->base_term2
= *m_ad
->base_term
;
388 if (m_index_loc
!= NULL
)
390 m_index_reg
= *m_index_loc
;
391 if (REG_P (m_index_reg
))
392 lra_eliminate_reg_if_possible (m_index_loc
);
396 address_eliminator::~address_eliminator ()
398 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
400 *m_base_loc
= m_base_reg
;
401 if (m_ad
->base_term2
!= NULL
)
402 *m_ad
->base_term2
= *m_ad
->base_term
;
404 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
405 *m_index_loc
= m_index_reg
;
408 /* Return true if the eliminated form of AD is a legitimate target address.
409 If OP is a MEM, AD is the address within OP, otherwise OP should be
410 ignored. CONSTRAINT is one constraint that the operand may need
413 valid_address_p (rtx op
, struct address_info
*ad
,
414 enum constraint_num constraint
)
416 address_eliminator
eliminator (ad
);
418 /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
420 Need to extract memory from op for special memory constraint,
421 i.e. bcst_mem_operand in i386 backend. */
422 if (MEM_P (extract_mem_from_operand (op
))
423 && insn_extra_relaxed_memory_constraint (constraint
)
424 && constraint_satisfied_p (op
, constraint
))
427 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
430 /* For special_memory_operand, it could be false for MEM_P (op),
431 i.e. bcst_mem_operand in i386 backend.
432 Extract and return real memory operand or op. */
434 extract_mem_from_operand (rtx op
)
436 for (rtx x
= op
;; x
= XEXP (x
, 0))
440 if (GET_RTX_LENGTH (GET_CODE (x
)) != 1
441 || GET_RTX_FORMAT (GET_CODE (x
))[0] != 'e')
447 /* Return true if the eliminated form of memory reference OP satisfies
448 extra (special) memory constraint CONSTRAINT. */
450 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
452 struct address_info ad
;
453 rtx mem
= extract_mem_from_operand (op
);
457 decompose_mem_address (&ad
, mem
);
458 address_eliminator
eliminator (&ad
);
459 return constraint_satisfied_p (op
, constraint
);
462 /* Return true if the eliminated form of address AD satisfies extra
463 address constraint CONSTRAINT. */
465 satisfies_address_constraint_p (struct address_info
*ad
,
466 enum constraint_num constraint
)
468 address_eliminator
eliminator (ad
);
469 return constraint_satisfied_p (*ad
->outer
, constraint
);
472 /* Return true if the eliminated form of address OP satisfies extra
473 address constraint CONSTRAINT. */
475 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
477 struct address_info ad
;
479 decompose_lea_address (&ad
, &op
);
480 return satisfies_address_constraint_p (&ad
, constraint
);
483 /* Initiate equivalences for LRA. As we keep original equivalences
484 before any elimination, we need to make copies otherwise any change
485 in insns might change the equivalences. */
487 lra_init_equiv (void)
489 ira_expand_reg_equiv ();
490 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
494 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
495 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
496 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
497 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
501 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
503 /* Update equivalence for REGNO. We need to this as the equivalence
504 might contain other pseudos which are changed by their
507 update_equiv (int regno
)
511 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
512 ira_reg_equiv
[regno
].memory
513 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
515 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
516 ira_reg_equiv
[regno
].invariant
517 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
521 /* If we have decided to substitute X with another value, return that
522 value, otherwise return X. */
529 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
530 || ! ira_reg_equiv
[regno
].defined_p
531 || ! ira_reg_equiv
[regno
].profitable_p
532 || lra_get_regno_hard_regno (regno
) >= 0)
534 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
536 if (targetm
.cannot_substitute_mem_equiv_p (res
))
540 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
542 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
547 /* If we have decided to substitute X with the equivalent value,
548 return that value after elimination for INSN, otherwise return
551 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
553 rtx res
= get_equiv (x
);
555 if (x
== res
|| CONSTANT_P (res
))
557 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
558 false, false, 0, true);
561 /* Set up curr_operand_mode. */
563 init_curr_operand_mode (void)
565 int nop
= curr_static_id
->n_operands
;
566 for (int i
= 0; i
< nop
; i
++)
568 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
569 if (mode
== VOIDmode
)
571 /* The .md mode for address operands is the mode of the
572 addressed value rather than the mode of the address itself. */
573 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
576 mode
= curr_static_id
->operand
[i
].mode
;
578 curr_operand_mode
[i
] = mode
;
584 /* The page contains code to reuse input reloads. */
586 /* Structure describes input reload of the current insns. */
589 /* True for input reload of matched operands. */
591 /* Reloaded value. */
593 /* Reload pseudo used. */
597 /* The number of elements in the following array. */
598 static int curr_insn_input_reloads_num
;
599 /* Array containing info about input reloads. It is used to find the
600 same input reload and reuse the reload pseudo in this case. */
601 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
603 /* Initiate data concerning reuse of input reloads for the current
606 init_curr_insn_input_reloads (void)
608 curr_insn_input_reloads_num
= 0;
611 /* The canonical form of an rtx inside a MEM is not necessarily the same as the
612 canonical form of the rtx outside the MEM. Fix this up in the case that
613 we're reloading an address (and therefore pulling it outside a MEM). */
615 canonicalize_reload_addr (rtx addr
)
617 subrtx_var_iterator::array_type array
;
618 FOR_EACH_SUBRTX_VAR (iter
, array
, addr
, NONCONST
)
621 if (GET_CODE (x
) == MULT
&& CONST_INT_P (XEXP (x
, 1)))
623 const HOST_WIDE_INT ci
= INTVAL (XEXP (x
, 1));
624 const int pwr2
= exact_log2 (ci
);
627 /* Rewrite this to use a shift instead, which is canonical when
629 PUT_CODE (x
, ASHIFT
);
630 XEXP (x
, 1) = GEN_INT (pwr2
);
638 /* Create a new pseudo using MODE, RCLASS, EXCLUDE_START_HARD_REGS, ORIGINAL or
639 reuse an existing reload pseudo. Don't reuse an existing reload pseudo if
640 IN_SUBREG_P is true and the reused pseudo should be wrapped up in a SUBREG.
641 The result pseudo is returned through RESULT_REG. Return TRUE if we created
642 a new pseudo, FALSE if we reused an existing reload pseudo. Use TITLE to
643 describe new registers for debug purposes. */
645 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
646 enum reg_class rclass
, HARD_REG_SET
*exclude_start_hard_regs
,
647 bool in_subreg_p
, const char *title
, rtx
*result_reg
)
650 enum reg_class new_class
;
651 bool unique_p
= false;
655 /* Output reload registers tend to start out with a conservative
656 choice of register class. Usually this is ALL_REGS, although
657 a target might narrow it (for performance reasons) through
658 targetm.preferred_reload_class. It's therefore quite common
659 for a reload instruction to require a more restrictive class
660 than the class that was originally assigned to the reload register.
662 In these situations, it's more efficient to refine the choice
663 of register class rather than create a second reload register.
664 This also helps to avoid cycling for registers that are only
665 used by reload instructions. */
667 && (int) REGNO (original
) >= new_regno_start
668 && INSN_UID (curr_insn
) >= new_insn_uid_start
669 && in_class_p (original
, rclass
, &new_class
, true))
671 unsigned int regno
= REGNO (original
);
672 if (lra_dump_file
!= NULL
)
674 fprintf (lra_dump_file
, " Reuse r%d for output ", regno
);
675 dump_value_slim (lra_dump_file
, original
, 1);
677 if (new_class
!= lra_get_allocno_class (regno
))
678 lra_change_class (regno
, new_class
, ", change to", false);
679 if (lra_dump_file
!= NULL
)
680 fprintf (lra_dump_file
, "\n");
681 *result_reg
= original
;
685 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
,
686 exclude_start_hard_regs
, title
);
689 /* Prevent reuse value of expression with side effects,
690 e.g. volatile memory. */
691 if (! side_effects_p (original
))
692 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
694 if (! curr_insn_input_reloads
[i
].match_p
695 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
696 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
698 rtx reg
= curr_insn_input_reloads
[i
].reg
;
700 /* If input is equal to original and both are VOIDmode,
701 GET_MODE (reg) might be still different from mode.
702 Ensure we don't return *result_reg with wrong mode. */
703 if (GET_MODE (reg
) != mode
)
707 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
708 GET_MODE_SIZE (mode
)))
710 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
711 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
715 if (lra_dump_file
!= NULL
)
717 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
718 dump_value_slim (lra_dump_file
, original
, 1);
720 if (new_class
!= lra_get_allocno_class (regno
))
721 lra_change_class (regno
, new_class
, ", change to", false);
722 if (lra_dump_file
!= NULL
)
723 fprintf (lra_dump_file
, "\n");
726 /* If we have an input reload with a different mode, make sure it
727 will get a different hard reg. */
728 else if (REG_P (original
)
729 && REG_P (curr_insn_input_reloads
[i
].input
)
730 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
731 && (GET_MODE (original
)
732 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
735 *result_reg
= (unique_p
736 ? lra_create_new_reg_with_unique_value
737 : lra_create_new_reg
) (mode
, original
, rclass
,
738 exclude_start_hard_regs
, title
);
739 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
740 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
741 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
742 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
747 /* The page contains major code to choose the current insn alternative
748 and generate reloads for it. */
750 /* Return the offset from REGNO of the least significant register
753 This function is used to tell whether two registers satisfy
754 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
756 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
757 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
759 lra_constraint_offset (int regno
, machine_mode mode
)
761 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
763 scalar_int_mode int_mode
;
765 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
766 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
767 return hard_regno_nregs (regno
, mode
) - 1;
771 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
772 if they are the same hard reg, and has special hacks for
773 auto-increment and auto-decrement. This is specifically intended for
774 process_alt_operands to use in determining whether two operands
775 match. X is the operand whose number is the lower of the two.
777 It is supposed that X is the output operand and Y is the input
778 operand. Y_HARD_REGNO is the final hard regno of register Y or
779 register in subreg Y as we know it now. Otherwise, it is a
782 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
785 RTX_CODE code
= GET_CODE (x
);
790 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
791 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
795 i
= get_hard_regno (x
);
799 if ((j
= y_hard_regno
) < 0)
802 i
+= lra_constraint_offset (i
, GET_MODE (x
));
803 j
+= lra_constraint_offset (j
, GET_MODE (y
));
808 /* If two operands must match, because they are really a single
809 operand of an assembler insn, then two post-increments are invalid
810 because the assembler insn would increment only once. On the
811 other hand, a post-increment matches ordinary indexing if the
812 post-increment is the output operand. */
813 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
814 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
816 /* Two pre-increments are invalid because the assembler insn would
817 increment only once. On the other hand, a pre-increment matches
818 ordinary indexing if the pre-increment is the input operand. */
819 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
820 || GET_CODE (y
) == PRE_MODIFY
)
821 return operands_match_p (x
, XEXP (y
, 0), -1);
825 if (code
== REG
&& REG_P (y
))
826 return REGNO (x
) == REGNO (y
);
828 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
829 && x
== SUBREG_REG (y
))
831 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
832 && SUBREG_REG (x
) == y
)
835 /* Now we have disposed of all the cases in which different rtx
837 if (code
!= GET_CODE (y
))
840 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
841 if (GET_MODE (x
) != GET_MODE (y
))
850 if (!same_vector_encodings_p (x
, y
))
855 return label_ref_label (x
) == label_ref_label (y
);
857 return XSTR (x
, 0) == XSTR (y
, 0);
863 /* Compare the elements. If any pair of corresponding elements fail
864 to match, return false for the whole things. */
866 fmt
= GET_RTX_FORMAT (code
);
867 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
873 if (XWINT (x
, i
) != XWINT (y
, i
))
878 if (XINT (x
, i
) != XINT (y
, i
))
883 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
888 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
897 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
899 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
901 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
907 /* It is believed that rtx's at this level will never
908 contain anything but integers and other rtx's, except for
909 within LABEL_REFs and SYMBOL_REFs. */
917 /* True if X is a constant that can be forced into the constant pool.
918 MODE is the mode of the operand, or VOIDmode if not known. */
919 #define CONST_POOL_OK_P(MODE, X) \
920 ((MODE) != VOIDmode \
922 && GET_CODE (X) != HIGH \
923 && GET_MODE_SIZE (MODE).is_constant () \
924 && !targetm.cannot_force_const_mem (MODE, X))
926 /* True if C is a non-empty register class that has too few registers
927 to be safely used as a reload target class. */
928 #define SMALL_REGISTER_CLASS_P(C) \
929 (ira_class_hard_regs_num [(C)] == 1 \
930 || (ira_class_hard_regs_num [(C)] >= 1 \
931 && targetm.class_likely_spilled_p (C)))
933 /* If REG is a reload pseudo, try to make its class satisfying CL. */
935 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
937 enum reg_class rclass
;
939 /* Do not make more accurate class from reloads generated. They are
940 mostly moves with a lot of constraints. Making more accurate
941 class may results in very narrow class and impossibility of find
942 registers for several reloads of one insn. */
943 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
945 if (GET_CODE (reg
) == SUBREG
)
946 reg
= SUBREG_REG (reg
);
947 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
949 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
950 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
953 /* Searches X for any reference to a reg with the same value as REGNO,
954 returning the rtx of the reference found if any. Otherwise,
957 regno_val_use_in (unsigned int regno
, rtx x
)
963 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
966 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
967 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
971 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
974 else if (fmt
[i
] == 'E')
975 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
976 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
983 /* Return true if all current insn non-output operands except INS (it
984 has a negaitve end marker) do not use pseudos with the same value
987 check_conflict_input_operands (int regno
, signed char *ins
)
990 int n_operands
= curr_static_id
->n_operands
;
992 for (int nop
= 0; nop
< n_operands
; nop
++)
993 if (! curr_static_id
->operand
[nop
].is_operator
994 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
996 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
1000 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
1006 /* Generate reloads for matching OUT and INS (array of input operand numbers
1007 with end marker -1) with reg class GOAL_CLASS and EXCLUDE_START_HARD_REGS,
1008 considering output operands OUTS (similar array to INS) needing to be in
1009 different registers. Add input and output reloads correspondingly to the
1010 lists *BEFORE and *AFTER. OUT might be negative. In this case we generate
1011 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
1012 that the output operand is early clobbered for chosen alternative. */
1014 match_reload (signed char out
, signed char *ins
, signed char *outs
,
1015 enum reg_class goal_class
, HARD_REG_SET
*exclude_start_hard_regs
,
1016 rtx_insn
**before
, rtx_insn
**after
, bool early_clobber_p
)
1020 rtx new_in_reg
, new_out_reg
, reg
;
1021 machine_mode inmode
, outmode
;
1022 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
1023 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
1025 inmode
= curr_operand_mode
[ins
[0]];
1026 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
1027 push_to_sequence (*before
);
1028 if (inmode
!= outmode
)
1030 /* process_alt_operands has already checked that the mode sizes
1032 if (partial_subreg_p (outmode
, inmode
))
1034 bool asm_p
= asm_noperands (PATTERN (curr_insn
)) >= 0;
1036 HARD_REG_SET temp_hard_reg_set
;
1038 if (asm_p
&& (hr
= get_hard_regno (out_rtx
)) >= 0
1039 && hard_regno_nregs (hr
, inmode
) > 1)
1041 /* See gcc.c-torture/execute/20030222-1.c.
1042 Consider the code for 32-bit (e.g. BE) target:
1043 int i, v; long x; x = v; asm ("" : "=r" (i) : "0" (x));
1044 We generate the following RTL with reload insns:
1045 1. subreg:si(x:di, 0) = 0;
1046 2. subreg:si(x:di, 4) = v:si;
1047 3. t:di = x:di, dead x;
1048 4. asm ("" : "=r" (subreg:si(t:di,4)) : "0" (t:di))
1049 5. i:si = subreg:si(t:di,4);
1050 If we assign hard reg of x to t, dead code elimination
1051 will remove insn #2 and we will use unitialized hard reg.
1052 So exclude the hard reg of x for t. We could ignore this
1053 problem for non-empty asm using all x value but it is hard to
1054 check that the asm are expanded into insn realy using x
1056 CLEAR_HARD_REG_SET (temp_hard_reg_set
);
1057 if (exclude_start_hard_regs
!= NULL
)
1058 temp_hard_reg_set
= *exclude_start_hard_regs
;
1059 SET_HARD_REG_BIT (temp_hard_reg_set
, hr
);
1060 exclude_start_hard_regs
= &temp_hard_reg_set
;
1063 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
, goal_class
,
1064 exclude_start_hard_regs
,
1066 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
1067 LRA_SUBREG_P (new_out_reg
) = 1;
1068 /* If the input reg is dying here, we can use the same hard
1069 register for REG and IN_RTX. We do it only for original
1070 pseudos as reload pseudos can die although original
1071 pseudos still live where reload pseudos dies. */
1072 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
1073 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1074 && (!early_clobber_p
1075 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
1076 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
1081 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1083 exclude_start_hard_regs
,
1085 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
1086 /* NEW_IN_REG is non-paradoxical subreg. We don't want
1087 NEW_OUT_REG living above. We add clobber clause for
1088 this. This is just a temporary clobber. We can remove
1089 it at the end of LRA work. */
1090 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
1091 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
1092 LRA_SUBREG_P (new_in_reg
) = 1;
1093 if (GET_CODE (in_rtx
) == SUBREG
)
1095 rtx subreg_reg
= SUBREG_REG (in_rtx
);
1097 /* If SUBREG_REG is dying here and sub-registers IN_RTX
1098 and NEW_IN_REG are similar, we can use the same hard
1099 register for REG and SUBREG_REG. */
1100 if (REG_P (subreg_reg
)
1101 && (int) REGNO (subreg_reg
) < lra_new_regno_start
1102 && GET_MODE (subreg_reg
) == outmode
1103 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
1104 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
1105 && (! early_clobber_p
1106 || check_conflict_input_operands (REGNO (subreg_reg
),
1108 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
1114 /* Pseudos have values -- see comments for lra_reg_info.
1115 Different pseudos with the same value do not conflict even if
1116 they live in the same place. When we create a pseudo we
1117 assign value of original pseudo (if any) from which we
1118 created the new pseudo. If we create the pseudo from the
1119 input pseudo, the new pseudo will have no conflict with the
1120 input pseudo which is wrong when the input pseudo lives after
1121 the insn and as the new pseudo value is changed by the insn
1122 output. Therefore we create the new pseudo from the output
1123 except the case when we have single matched dying input
1126 We cannot reuse the current output register because we might
1127 have a situation like "a <- a op b", where the constraints
1128 force the second input operand ("b") to match the output
1129 operand ("a"). "b" must then be copied into a new register
1130 so that it doesn't clobber the current value of "a".
1132 We cannot use the same value if the output pseudo is
1133 early clobbered or the input pseudo is mentioned in the
1134 output, e.g. as an address part in memory, because
1135 output reload will actually extend the pseudo liveness.
1136 We don't care about eliminable hard regs here as we are
1137 interesting only in pseudos. */
1139 /* Matching input's register value is the same as one of the other
1140 output operand. Output operands in a parallel insn must be in
1141 different registers. */
1142 out_conflict
= false;
1145 for (i
= 0; outs
[i
] >= 0; i
++)
1147 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1148 if (outs
[i
] != out
&& REG_P (other_out_rtx
)
1149 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1152 out_conflict
= true;
1158 new_in_reg
= new_out_reg
1159 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1160 && (int) REGNO (in_rtx
) < lra_new_regno_start
1161 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1162 && (! early_clobber_p
1163 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1165 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1167 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
,
1168 exclude_start_hard_regs
, "")
1169 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
, goal_class
,
1170 exclude_start_hard_regs
,
1173 /* In operand can be got from transformations before processing insn
1174 constraints. One example of such transformations is subreg
1175 reloading (see function simplify_operand_subreg). The new
1176 pseudos created by the transformations might have inaccurate
1177 class (ALL_REGS) and we should make their classes more
1179 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1180 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1181 *before
= get_insns ();
1183 /* Add the new pseudo to consider values of subsequent input reload
1185 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1186 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1187 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1188 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1189 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1190 if (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1191 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]))
1192 *curr_id
->operand_loc
[in
] = new_in_reg
;
1196 (GET_MODE (new_out_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1197 *curr_id
->operand_loc
[in
] = new_out_reg
;
1199 lra_update_dups (curr_id
, ins
);
1202 /* See a comment for the input operand above. */
1203 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1204 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1206 reg
= SUBREG_P (out_rtx
) ? SUBREG_REG (out_rtx
) : out_rtx
;
1208 /* If we had strict_low_part, use it also in reload to keep other
1209 parts unchanged but do it only for regs as strict_low_part
1210 has no sense for memory and probably there is no insn pattern
1211 to match the reload insn in memory case. */
1212 if (out
>= 0 && curr_static_id
->operand
[out
].strict_low
&& REG_P (reg
))
1213 out_rtx
= gen_rtx_STRICT_LOW_PART (VOIDmode
, out_rtx
);
1214 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1216 *after
= get_insns ();
1219 *curr_id
->operand_loc
[out
] = new_out_reg
;
1220 lra_update_dup (curr_id
, out
);
1223 /* Return register class which is union of all reg classes in insn
1224 constraint alternative string starting with P. */
1225 static enum reg_class
1226 reg_class_from_constraints (const char *p
)
1229 enum reg_class op_class
= NO_REGS
;
1232 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1239 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1243 enum constraint_num cn
= lookup_constraint (p
);
1244 enum reg_class cl
= reg_class_for_constraint (cn
);
1247 if (insn_extra_address_constraint (cn
))
1249 = (reg_class_subunion
1250 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1251 ADDRESS
, SCRATCH
)]);
1255 op_class
= reg_class_subunion
[op_class
][cl
];
1258 while ((p
+= len
), c
);
1262 /* If OP is a register, return the class of the register as per
1263 get_reg_class, otherwise return NO_REGS. */
1264 static inline enum reg_class
1265 get_op_class (rtx op
)
1267 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1270 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1271 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1272 SUBREG for VAL to make them equal. */
1274 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1276 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1278 /* Usually size of mem_pseudo is greater than val size but in
1279 rare cases it can be less as it can be defined by target
1280 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1283 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1284 GET_CODE (val
) == SUBREG
1285 ? SUBREG_REG (val
) : val
);
1286 LRA_SUBREG_P (val
) = 1;
1290 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1291 LRA_SUBREG_P (mem_pseudo
) = 1;
1294 return to_p
? gen_move_insn (mem_pseudo
, val
)
1295 : gen_move_insn (val
, mem_pseudo
);
1298 /* Process a special case insn (register move), return true if we
1299 don't need to process it anymore. INSN should be a single set
1300 insn. Set up that RTL was changed through CHANGE_P and that hook
1301 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1304 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1307 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1309 enum reg_class dclass
, sclass
, secondary_class
;
1310 secondary_reload_info sri
;
1312 lra_assert (curr_insn_set
!= NULL_RTX
);
1313 dreg
= dest
= SET_DEST (curr_insn_set
);
1314 sreg
= src
= SET_SRC (curr_insn_set
);
1315 if (GET_CODE (dest
) == SUBREG
)
1316 dreg
= SUBREG_REG (dest
);
1317 if (GET_CODE (src
) == SUBREG
)
1318 sreg
= SUBREG_REG (src
);
1319 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1321 sclass
= dclass
= NO_REGS
;
1323 dclass
= get_reg_class (REGNO (dreg
));
1324 gcc_assert (dclass
< LIM_REG_CLASSES
&& dclass
>= NO_REGS
);
1325 if (dclass
== ALL_REGS
)
1326 /* ALL_REGS is used for new pseudos created by transformations
1327 like reload of SUBREG_REG (see function
1328 simplify_operand_subreg). We don't know their class yet. We
1329 should figure out the class from processing the insn
1330 constraints not in this fast path function. Even if ALL_REGS
1331 were a right class for the pseudo, secondary_... hooks usually
1332 are not define for ALL_REGS. */
1335 sclass
= get_reg_class (REGNO (sreg
));
1336 gcc_assert (sclass
< LIM_REG_CLASSES
&& sclass
>= NO_REGS
);
1337 if (sclass
== ALL_REGS
)
1338 /* See comments above. */
1340 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1342 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1343 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1345 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1350 if (! REG_P (dreg
) || ! REG_P (sreg
))
1352 sri
.prev_sri
= NULL
;
1353 sri
.icode
= CODE_FOR_nothing
;
1355 secondary_class
= NO_REGS
;
1356 /* Set up hard register for a reload pseudo for hook
1357 secondary_reload because some targets just ignore unassigned
1358 pseudos in the hook. */
1359 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1361 dregno
= REGNO (dreg
);
1362 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1366 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1368 sregno
= REGNO (sreg
);
1369 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1373 if (sclass
!= NO_REGS
)
1375 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1376 (reg_class_t
) sclass
,
1377 GET_MODE (src
), &sri
);
1378 if (sclass
== NO_REGS
1379 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1380 && dclass
!= NO_REGS
))
1382 enum reg_class old_sclass
= secondary_class
;
1383 secondary_reload_info old_sri
= sri
;
1385 sri
.prev_sri
= NULL
;
1386 sri
.icode
= CODE_FOR_nothing
;
1389 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1390 (reg_class_t
) dclass
,
1391 GET_MODE (src
), &sri
);
1392 /* Check the target hook consistency. */
1394 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1395 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1396 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1399 reg_renumber
[sregno
] = -1;
1401 reg_renumber
[dregno
] = -1;
1402 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1406 if (secondary_class
!= NO_REGS
)
1407 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1408 secondary_class
, NULL
,
1411 if (sri
.icode
== CODE_FOR_nothing
)
1412 lra_emit_move (new_reg
, src
);
1415 enum reg_class scratch_class
;
1417 scratch_class
= (reg_class_from_constraints
1418 (insn_data
[sri
.icode
].operand
[2].constraint
));
1419 scratch_reg
= (lra_create_new_reg_with_unique_value
1420 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1421 scratch_class
, NULL
, "scratch"));
1422 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1425 before
= get_insns ();
1427 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1428 if (new_reg
!= NULL_RTX
)
1429 SET_SRC (curr_insn_set
) = new_reg
;
1432 if (lra_dump_file
!= NULL
)
1434 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1435 dump_insn_slim (lra_dump_file
, curr_insn
);
1437 lra_set_insn_deleted (curr_insn
);
1443 /* The following data describe the result of process_alt_operands.
1444 The data are used in curr_insn_transform to generate reloads. */
1446 /* The chosen reg classes which should be used for the corresponding
1448 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1449 /* Hard registers which cannot be a start hard register for the corresponding
1451 static HARD_REG_SET goal_alt_exclude_start_hard_regs
[MAX_RECOG_OPERANDS
];
1452 /* True if the operand should be the same as another operand and that
1453 other operand does not need a reload. */
1454 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1455 /* True if the operand does not need a reload. */
1456 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1457 /* True if the operand can be offsetable memory. */
1458 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1459 /* The number of an operand to which given operand can be matched to. */
1460 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1461 /* The number of elements in the following array. */
1462 static int goal_alt_dont_inherit_ops_num
;
1463 /* Numbers of operands whose reload pseudos should not be inherited. */
1464 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1465 /* True if we should try only this alternative for the next constraint sub-pass
1466 to speed up the sub-pass. */
1467 static bool goal_reuse_alt_p
;
1468 /* True if the insn commutative operands should be swapped. */
1469 static bool goal_alt_swapped
;
1470 /* The chosen insn alternative. */
1471 static int goal_alt_number
;
1472 /* True if output reload of the stack pointer should be generated. */
1473 static bool goal_alt_out_sp_reload_p
;
1475 /* True if the corresponding operand is the result of an equivalence
1477 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1479 /* The following five variables are used to choose the best insn
1480 alternative. They reflect final characteristics of the best
1483 /* Number of necessary reloads and overall cost reflecting the
1484 previous value and other unpleasantness of the best alternative. */
1485 static int best_losers
, best_overall
;
1486 /* Overall number hard registers used for reloads. For example, on
1487 some targets we need 2 general registers to reload DFmode and only
1488 one floating point register. */
1489 static int best_reload_nregs
;
1490 /* Overall number reflecting distances of previous reloading the same
1491 value. The distances are counted from the current BB start. It is
1492 used to improve inheritance chances. */
1493 static int best_reload_sum
;
1495 /* True if the current insn should have no correspondingly input or
1497 static bool no_input_reloads_p
, no_output_reloads_p
;
1499 /* True if we swapped the commutative operands in the current
1501 static int curr_swapped
;
1503 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1504 register of class CL. Add any input reloads to list BEFORE. AFTER
1505 is nonnull if *LOC is an automodified value; handle that case by
1506 adding the required output reloads to list AFTER. Return true if
1507 the RTL was changed.
1509 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1510 register. Return false if the address register is correct. */
1512 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1516 enum reg_class rclass
, new_class
;
1520 bool subreg_p
, before_p
= false;
1522 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1525 reg
= SUBREG_REG (*loc
);
1526 mode
= GET_MODE (reg
);
1528 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1529 between two registers with different classes, but there normally will
1530 be "mov" which transfers element of vector register into the general
1531 register, and this normally will be a subreg which should be reloaded
1532 as a whole. This is particularly likely to be triggered when
1533 -fno-split-wide-types specified. */
1535 || in_class_p (reg
, cl
, &new_class
)
1536 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1537 loc
= &SUBREG_REG (*loc
);
1541 mode
= GET_MODE (reg
);
1546 /* Always reload memory in an address even if the target supports
1548 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, NULL
,
1554 regno
= REGNO (reg
);
1555 rclass
= get_reg_class (regno
);
1557 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1559 if (lra_dump_file
!= NULL
)
1561 fprintf (lra_dump_file
,
1562 "Changing pseudo %d in address of insn %u on equiv ",
1563 REGNO (reg
), INSN_UID (curr_insn
));
1564 dump_value_slim (lra_dump_file
, *loc
, 1);
1565 fprintf (lra_dump_file
, "\n");
1567 *loc
= copy_rtx (*loc
);
1569 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1574 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1575 mode
, reg
, cl
, NULL
,
1576 subreg_p
, "address", &new_reg
))
1579 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1583 lra_change_class (regno
, new_class
, " Change to", true);
1591 push_to_sequence (*before
);
1592 lra_emit_move (new_reg
, reg
);
1593 *before
= get_insns ();
1600 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1602 *after
= get_insns ();
1608 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1609 the insn to be inserted before curr insn. AFTER returns the
1610 the insn to be inserted after curr insn. ORIGREG and NEWREG
1611 are the original reg and new reg for reload. */
1613 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1618 push_to_sequence (*before
);
1619 lra_emit_move (newreg
, origreg
);
1620 *before
= get_insns ();
1626 lra_emit_move (origreg
, newreg
);
1628 *after
= get_insns ();
1633 static bool valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1634 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1636 /* Make reloads for subreg in operand NOP with internal subreg mode
1637 REG_MODE, add new reloads for further processing. Return true if
1638 any change was done. */
1640 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1642 int hard_regno
, inner_hard_regno
;
1643 rtx_insn
*before
, *after
;
1644 machine_mode mode
, innermode
;
1646 rtx operand
= *curr_id
->operand_loc
[nop
];
1647 enum reg_class regclass
;
1650 before
= after
= NULL
;
1652 if (GET_CODE (operand
) != SUBREG
)
1655 mode
= GET_MODE (operand
);
1656 reg
= SUBREG_REG (operand
);
1657 innermode
= GET_MODE (reg
);
1658 type
= curr_static_id
->operand
[nop
].type
;
1661 const bool addr_was_valid
1662 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1663 alter_subreg (curr_id
->operand_loc
[nop
], false);
1664 rtx subst
= *curr_id
->operand_loc
[nop
];
1665 lra_assert (MEM_P (subst
));
1666 const bool addr_is_valid
= valid_address_p (GET_MODE (subst
),
1668 MEM_ADDR_SPACE (subst
));
1671 || ((get_constraint_type (lookup_constraint
1672 (curr_static_id
->operand
[nop
].constraint
))
1673 != CT_SPECIAL_MEMORY
)
1674 /* We still can reload address and if the address is
1675 valid, we can remove subreg without reloading its
1677 && valid_address_p (GET_MODE (subst
),
1679 [ira_class_hard_regs
1680 [base_reg_class (GET_MODE (subst
),
1681 MEM_ADDR_SPACE (subst
),
1682 ADDRESS
, SCRATCH
)][0]],
1683 MEM_ADDR_SPACE (subst
))))
1685 /* If we change the address for a paradoxical subreg of memory, the
1686 new address might violate the necessary alignment or the access
1687 might be slow; take this into consideration. We need not worry
1688 about accesses beyond allocated memory for paradoxical memory
1689 subregs as we don't substitute such equiv memory (see processing
1690 equivalences in function lra_constraints) and because for spilled
1691 pseudos we allocate stack memory enough for the biggest
1692 corresponding paradoxical subreg.
1694 However, do not blindly simplify a (subreg (mem ...)) for
1695 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1696 data into a register when the inner is narrower than outer or
1697 missing important data from memory when the inner is wider than
1698 outer. This rule only applies to modes that are no wider than
1701 If valid memory becomes invalid after subreg elimination
1702 and address might be different we still have to reload
1705 if ((! addr_was_valid
1707 || known_eq (GET_MODE_SIZE (mode
), GET_MODE_SIZE (innermode
)))
1708 && !(maybe_ne (GET_MODE_PRECISION (mode
),
1709 GET_MODE_PRECISION (innermode
))
1710 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1711 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1712 && WORD_REGISTER_OPERATIONS
)
1713 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1714 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1715 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1716 && targetm
.slow_unaligned_access (innermode
,
1720 *curr_id
->operand_loc
[nop
] = operand
;
1722 /* But if the address was not valid, we cannot reload the MEM without
1723 reloading the address first. */
1724 if (!addr_was_valid
)
1725 process_address (nop
, false, &before
, &after
);
1727 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1728 enum reg_class rclass
1729 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1730 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1732 true, "slow/invalid mem", &new_reg
))
1734 bool insert_before
, insert_after
;
1735 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1737 insert_before
= (type
!= OP_OUT
1738 || partial_subreg_p (mode
, innermode
));
1739 insert_after
= type
!= OP_IN
;
1740 insert_move_for_subreg (insert_before
? &before
: NULL
,
1741 insert_after
? &after
: NULL
,
1744 SUBREG_REG (operand
) = new_reg
;
1746 /* Convert to MODE. */
1749 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1750 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1752 true, "slow/invalid mem", &new_reg
))
1754 bool insert_before
, insert_after
;
1755 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1757 insert_before
= type
!= OP_OUT
;
1758 insert_after
= type
!= OP_IN
;
1759 insert_move_for_subreg (insert_before
? &before
: NULL
,
1760 insert_after
? &after
: NULL
,
1763 *curr_id
->operand_loc
[nop
] = new_reg
;
1764 lra_process_new_insns (curr_insn
, before
, after
,
1765 "Inserting slow/invalid mem reload");
1769 /* If the address was valid and became invalid, prefer to reload
1770 the memory. Typical case is when the index scale should
1771 correspond the memory. */
1772 *curr_id
->operand_loc
[nop
] = operand
;
1773 /* Do not return false here as the MEM_P (reg) will be processed
1774 later in this function. */
1776 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1778 alter_subreg (curr_id
->operand_loc
[nop
], false);
1781 else if (CONSTANT_P (reg
))
1783 /* Try to simplify subreg of constant. It is usually result of
1784 equivalence substitution. */
1785 if (innermode
== VOIDmode
1786 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1787 innermode
= curr_static_id
->operand
[nop
].mode
;
1788 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1789 SUBREG_BYTE (operand
))) != NULL_RTX
)
1791 *curr_id
->operand_loc
[nop
] = new_reg
;
1795 /* Put constant into memory when we have mixed modes. It generates
1796 a better code in most cases as it does not need a secondary
1797 reload memory. It also prevents LRA looping when LRA is using
1798 secondary reload memory again and again. */
1799 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1800 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1802 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1803 alter_subreg (curr_id
->operand_loc
[nop
], false);
1806 auto fp_subreg_can_be_simplified_after_reload_p
= [] (machine_mode innermode
,
1808 machine_mode mode
) {
1809 reload_completed
= 1;
1810 bool res
= simplify_subreg_regno (FRAME_POINTER_REGNUM
,
1813 reload_completed
= 0;
1816 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1817 if there may be a problem accessing OPERAND in the outer
1820 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1821 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1822 /* Don't reload paradoxical subregs because we could be looping
1823 having repeatedly final regno out of hard regs range. */
1824 && (hard_regno_nregs (hard_regno
, innermode
)
1825 >= hard_regno_nregs (hard_regno
, mode
))
1826 && simplify_subreg_regno (hard_regno
, innermode
,
1827 SUBREG_BYTE (operand
), mode
) < 0
1828 /* Exclude reloading of frame pointer in subreg if frame pointer can not
1829 be simplified here only because the reload is not finished yet. */
1830 && (hard_regno
!= FRAME_POINTER_REGNUM
1831 || !fp_subreg_can_be_simplified_after_reload_p (innermode
,
1832 SUBREG_BYTE (operand
),
1834 /* Don't reload subreg for matching reload. It is actually
1835 valid subreg in LRA. */
1836 && ! LRA_SUBREG_P (operand
))
1837 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1839 enum reg_class rclass
;
1842 /* There is a big probability that we will get the same class
1843 for the new pseudo and we will get the same insn which
1844 means infinite looping. So spill the new pseudo. */
1847 /* The class will be defined later in curr_insn_transform. */
1849 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1851 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1853 true, "subreg reg", &new_reg
))
1855 bool insert_before
, insert_after
;
1856 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1858 insert_before
= (type
!= OP_OUT
1859 || read_modify_subreg_p (operand
));
1860 insert_after
= (type
!= OP_IN
);
1861 insert_move_for_subreg (insert_before
? &before
: NULL
,
1862 insert_after
? &after
: NULL
,
1865 SUBREG_REG (operand
) = new_reg
;
1866 lra_process_new_insns (curr_insn
, before
, after
,
1867 "Inserting subreg reload");
1870 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1871 IRA allocates hardreg to the inner pseudo reg according to its mode
1872 instead of the outermode, so the size of the hardreg may not be enough
1873 to contain the outermode operand, in that case we may need to insert
1874 reload for the reg. For the following two types of paradoxical subreg,
1875 we need to insert reload:
1876 1. If the op_type is OP_IN, and the hardreg could not be paired with
1877 other hardreg to contain the outermode operand
1878 (checked by in_hard_reg_set_p), we need to insert the reload.
1879 2. If the op_type is OP_OUT or OP_INOUT.
1881 Here is a paradoxical subreg example showing how the reload is generated:
1883 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1884 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1886 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1887 here, if reg107 is assigned to hardreg R15, because R15 is the last
1888 hardreg, compiler cannot find another hardreg to pair with R15 to
1889 contain TImode data. So we insert a TImode reload reg180 for it.
1890 After reload is inserted:
1892 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1893 (reg:DI 107 [ __comp ])) -1
1894 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1895 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1897 Two reload hard registers will be allocated to reg180 to save TImode data
1900 For LRA pseudos this should normally be handled by the biggest_mode
1901 mechanism. However, it's possible for new uses of an LRA pseudo
1902 to be introduced after we've allocated it, such as when undoing
1903 inheritance, and the allocated register might not then be appropriate
1904 for the new uses. */
1905 else if (REG_P (reg
)
1906 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1907 && paradoxical_subreg_p (operand
)
1908 && (inner_hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1910 = simplify_subreg_regno (inner_hard_regno
, innermode
,
1911 SUBREG_BYTE (operand
), mode
)) < 0
1912 || ((hard_regno_nregs (inner_hard_regno
, innermode
)
1913 < hard_regno_nregs (hard_regno
, mode
))
1914 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1916 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1918 || overlaps_hard_reg_set_p (lra_no_alloc_regs
,
1919 mode
, hard_regno
)))))
1921 /* The class will be defined later in curr_insn_transform. */
1922 enum reg_class rclass
1923 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1925 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1927 true, "paradoxical subreg", &new_reg
))
1930 bool insert_before
, insert_after
;
1932 PUT_MODE (new_reg
, mode
);
1933 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1934 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1936 insert_before
= (type
!= OP_OUT
);
1937 insert_after
= (type
!= OP_IN
);
1938 insert_move_for_subreg (insert_before
? &before
: NULL
,
1939 insert_after
? &after
: NULL
,
1942 SUBREG_REG (operand
) = new_reg
;
1943 lra_process_new_insns (curr_insn
, before
, after
,
1944 "Inserting paradoxical subreg reload");
1950 /* Return TRUE if X refers for a hard register from SET. */
1952 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1954 int i
, j
, x_hard_regno
;
1961 code
= GET_CODE (x
);
1962 mode
= GET_MODE (x
);
1966 /* For all SUBREGs we want to check whether the full multi-register
1967 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1968 the inner register, for paradoxical SUBREGs this means the
1969 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1970 fine. Use the wider mode for all cases. */
1971 rtx subreg
= SUBREG_REG (x
);
1972 mode
= wider_subreg_mode (x
);
1973 if (mode
== GET_MODE (subreg
))
1976 code
= GET_CODE (x
);
1980 if (REG_P (x
) || SUBREG_P (x
))
1982 x_hard_regno
= get_hard_regno (x
);
1983 return (x_hard_regno
>= 0
1984 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1986 fmt
= GET_RTX_FORMAT (code
);
1987 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1991 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1994 else if (fmt
[i
] == 'E')
1996 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1997 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
2004 /* Return true if OP is a spilled pseudo. */
2006 spilled_pseudo_p (rtx op
)
2009 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
2012 /* Return true if X is a general constant. */
2014 general_constant_p (rtx x
)
2016 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
2020 reg_in_class_p (rtx reg
, enum reg_class cl
)
2023 return get_reg_class (REGNO (reg
)) == NO_REGS
;
2024 return in_class_p (reg
, cl
, NULL
);
2027 /* Return true if SET of RCLASS contains no hard regs which can be
2030 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
2036 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
2037 temp
= set
& ~lra_no_alloc_regs
;
2038 return (hard_reg_set_subset_p
2039 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
2043 /* Used to check validity info about small class input operands. It
2044 should be incremented at start of processing an insn
2046 static unsigned int curr_small_class_check
= 0;
2048 /* Update number of used inputs of class OP_CLASS for operand NOP
2049 of alternative NALT. Return true if we have more such class operands
2050 than the number of available regs. */
2052 update_and_check_small_class_inputs (int nop
, int nalt
,
2053 enum reg_class op_class
)
2055 static unsigned int small_class_check
[LIM_REG_CLASSES
];
2056 static int small_class_input_nums
[LIM_REG_CLASSES
];
2058 if (SMALL_REGISTER_CLASS_P (op_class
)
2059 /* We are interesting in classes became small because of fixing
2060 some hard regs, e.g. by an user through GCC options. */
2061 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
2063 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
2064 || TEST_BIT (curr_static_id
->operand
[nop
].early_clobber_alts
, nalt
)))
2066 if (small_class_check
[op_class
] == curr_small_class_check
)
2067 small_class_input_nums
[op_class
]++;
2070 small_class_check
[op_class
] = curr_small_class_check
;
2071 small_class_input_nums
[op_class
] = 1;
2073 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
2079 /* Print operand constraints for alternative ALT_NUMBER of the current
2082 print_curr_insn_alt (int alt_number
)
2084 for (int i
= 0; i
< curr_static_id
->n_operands
; i
++)
2086 const char *p
= (curr_static_id
->operand_alternative
2087 [alt_number
* curr_static_id
->n_operands
+ i
].constraint
);
2090 fprintf (lra_dump_file
, " (%d) ", i
);
2091 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
2092 fputc (*p
, lra_dump_file
);
2096 /* Major function to choose the current insn alternative and what
2097 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
2098 negative we should consider only this alternative. Return false if
2099 we cannot choose the alternative or find how to reload the
2102 process_alt_operands (int only_alternative
)
2105 int nop
, overall
, nalt
;
2106 int n_alternatives
= curr_static_id
->n_alternatives
;
2107 int n_operands
= curr_static_id
->n_operands
;
2108 /* LOSERS counts the operands that don't fit this alternative and
2109 would require loading. */
2112 /* REJECT is a count of how undesirable this alternative says it is
2113 if any reloading is required. If the alternative matches exactly
2114 then REJECT is ignored, but otherwise it gets this much counted
2115 against it in addition to the reloading needed. */
2117 /* This is defined by '!' or '?' alternative constraint and added to
2118 reject. But in some cases it can be ignored. */
2121 /* The number of elements in the following array. */
2122 int early_clobbered_regs_num
;
2123 /* Numbers of operands which are early clobber registers. */
2124 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
2125 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
2126 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
2127 HARD_REG_SET curr_alt_exclude_start_hard_regs
[MAX_RECOG_OPERANDS
];
2128 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
2129 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
2130 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
2131 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
2132 /* The number of elements in the following array. */
2133 int curr_alt_dont_inherit_ops_num
;
2134 /* Numbers of operands whose reload pseudos should not be inherited. */
2135 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
2136 bool curr_reuse_alt_p
;
2137 /* True if output stack pointer reload should be generated for the current
2139 bool curr_alt_out_sp_reload_p
;
2141 /* The register when the operand is a subreg of register, otherwise the
2143 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
2144 /* The register if the operand is a register or subreg of register,
2146 rtx operand_reg
[MAX_RECOG_OPERANDS
];
2147 int hard_regno
[MAX_RECOG_OPERANDS
];
2148 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
2149 int reload_nregs
, reload_sum
;
2152 const HARD_REG_SET
*cl_filter
;
2154 /* Calculate some data common for all alternatives to speed up the
2156 for (nop
= 0; nop
< n_operands
; nop
++)
2160 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
2161 /* The real hard regno of the operand after the allocation. */
2162 hard_regno
[nop
] = get_hard_regno (op
);
2164 operand_reg
[nop
] = reg
= op
;
2165 biggest_mode
[nop
] = GET_MODE (op
);
2166 if (GET_CODE (op
) == SUBREG
)
2168 biggest_mode
[nop
] = wider_subreg_mode (op
);
2169 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
2172 operand_reg
[nop
] = NULL_RTX
;
2173 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2174 || ((int) REGNO (reg
)
2175 == lra_get_elimination_hard_regno (REGNO (reg
))))
2176 no_subreg_reg_operand
[nop
] = reg
;
2178 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
2179 /* Just use natural mode for elimination result. It should
2180 be enough for extra constraints hooks. */
2181 = regno_reg_rtx
[hard_regno
[nop
]];
2184 /* The constraints are made of several alternatives. Each operand's
2185 constraint looks like foo,bar,... with commas separating the
2186 alternatives. The first alternatives for all operands go
2187 together, the second alternatives go together, etc.
2189 First loop over alternatives. */
2190 alternative_mask preferred
= curr_id
->preferred_alternatives
;
2191 if (only_alternative
>= 0)
2192 preferred
&= ALTERNATIVE_BIT (only_alternative
);
2194 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
2196 /* Loop over operands for one constraint alternative. */
2197 if (!TEST_BIT (preferred
, nalt
))
2200 if (lra_dump_file
!= NULL
)
2202 fprintf (lra_dump_file
, " Considering alt=%d of insn %d: ",
2203 nalt
, INSN_UID (curr_insn
));
2204 print_curr_insn_alt (nalt
);
2205 fprintf (lra_dump_file
, "\n");
2208 bool matching_early_clobber
[MAX_RECOG_OPERANDS
];
2209 curr_small_class_check
++;
2210 overall
= losers
= addr_losers
= 0;
2211 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
2212 for (nop
= 0; nop
< n_operands
; nop
++)
2214 int inc
= (curr_static_id
2215 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2216 if (lra_dump_file
!= NULL
&& inc
!= 0)
2217 fprintf (lra_dump_file
,
2218 " Staticly defined alt reject+=%d\n", inc
);
2219 static_reject
+= inc
;
2220 matching_early_clobber
[nop
] = 0;
2222 reject
+= static_reject
;
2223 early_clobbered_regs_num
= 0;
2224 curr_alt_out_sp_reload_p
= false;
2225 curr_reuse_alt_p
= true;
2227 for (nop
= 0; nop
< n_operands
; nop
++)
2231 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2232 bool win
, did_match
, offmemok
, early_clobber_p
;
2233 /* false => this operand can be reloaded somehow for this
2236 /* true => this operand can be reloaded if the alternative
2239 /* True if a constant forced into memory would be OK for
2242 enum reg_class this_alternative
, this_costly_alternative
;
2243 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2244 HARD_REG_SET this_alternative_exclude_start_hard_regs
;
2245 bool this_alternative_match_win
, this_alternative_win
;
2246 bool this_alternative_offmemok
;
2249 enum constraint_num cn
;
2251 opalt_num
= nalt
* n_operands
+ nop
;
2252 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2254 /* Fast track for no constraints at all. */
2255 curr_alt
[nop
] = NO_REGS
;
2256 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2257 curr_alt_win
[nop
] = true;
2258 curr_alt_match_win
[nop
] = false;
2259 curr_alt_offmemok
[nop
] = false;
2260 curr_alt_matches
[nop
] = -1;
2264 op
= no_subreg_reg_operand
[nop
];
2265 mode
= curr_operand_mode
[nop
];
2267 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2270 early_clobber_p
= false;
2271 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2273 this_costly_alternative
= this_alternative
= NO_REGS
;
2274 /* We update set of possible hard regs besides its class
2275 because reg class might be inaccurate. For example,
2276 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2277 is translated in HI_REGS because classes are merged by
2278 pairs and there is no accurate intermediate class. */
2279 CLEAR_HARD_REG_SET (this_alternative_set
);
2280 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2281 CLEAR_HARD_REG_SET (this_alternative_exclude_start_hard_regs
);
2282 this_alternative_win
= false;
2283 this_alternative_match_win
= false;
2284 this_alternative_offmemok
= false;
2285 this_alternative_matches
= -1;
2287 /* An empty constraint should be excluded by the fast
2289 lra_assert (*p
!= 0 && *p
!= ',');
2292 /* Scan this alternative's specs for this operand; set WIN
2293 if the operand fits any letter in this alternative.
2294 Otherwise, clear BADOP if this operand could fit some
2295 letter after reloads, or set WINREG if this operand could
2296 fit after reloads provided the constraint allows some
2301 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2311 early_clobber_p
= true;
2315 op_reject
+= LRA_MAX_REJECT
;
2318 op_reject
+= LRA_LOSER_COST_FACTOR
;
2322 /* Ignore rest of this alternative. */
2326 case '0': case '1': case '2': case '3': case '4':
2327 case '5': case '6': case '7': case '8': case '9':
2332 m
= strtoul (p
, &end
, 10);
2335 lra_assert (nop
> m
);
2337 /* Reject matches if we don't know which operand is
2338 bigger. This situation would arguably be a bug in
2339 an .md pattern, but could also occur in a user asm. */
2340 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2341 GET_MODE_SIZE (biggest_mode
[nop
])))
2344 /* Don't match wrong asm insn operands for proper
2345 diagnostic later. */
2346 if (INSN_CODE (curr_insn
) < 0
2347 && (curr_operand_mode
[m
] == BLKmode
2348 || curr_operand_mode
[nop
] == BLKmode
)
2349 && curr_operand_mode
[m
] != curr_operand_mode
[nop
])
2352 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
2353 /* We are supposed to match a previous operand.
2354 If we do, we win if that one did. If we do
2355 not, count both of the operands as losers.
2356 (This is too conservative, since most of the
2357 time only a single reload insn will be needed
2358 to make the two operands win. As a result,
2359 this alternative may be rejected when it is
2360 actually desirable.) */
2362 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2363 *curr_id
->operand_loc
[m
], m_hregno
))
2365 /* We should reject matching of an early
2366 clobber operand if the matching operand is
2367 not dying in the insn. */
2368 if (!TEST_BIT (curr_static_id
->operand
[m
]
2369 .early_clobber_alts
, nalt
)
2370 || operand_reg
[nop
] == NULL_RTX
2371 || (find_regno_note (curr_insn
, REG_DEAD
,
2373 || REGNO (op
) == REGNO (operand_reg
[m
])))
2378 /* If we are matching a non-offsettable
2379 address where an offsettable address was
2380 expected, then we must reject this
2381 combination, because we can't reload
2383 if (curr_alt_offmemok
[m
]
2384 && MEM_P (*curr_id
->operand_loc
[m
])
2385 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2390 /* If the operands do not match and one
2391 operand is INOUT, we can not match them.
2392 Try other possibilities, e.g. other
2393 alternatives or commutative operand
2395 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
2396 || curr_static_id
->operand
[m
].type
== OP_INOUT
)
2398 /* Operands don't match. If the operands are
2399 different user defined explicit hard
2400 registers, then we cannot make them match
2401 when one is early clobber operand. */
2402 if ((REG_P (*curr_id
->operand_loc
[nop
])
2403 || SUBREG_P (*curr_id
->operand_loc
[nop
]))
2404 && (REG_P (*curr_id
->operand_loc
[m
])
2405 || SUBREG_P (*curr_id
->operand_loc
[m
])))
2407 rtx nop_reg
= *curr_id
->operand_loc
[nop
];
2408 if (SUBREG_P (nop_reg
))
2409 nop_reg
= SUBREG_REG (nop_reg
);
2410 rtx m_reg
= *curr_id
->operand_loc
[m
];
2411 if (SUBREG_P (m_reg
))
2412 m_reg
= SUBREG_REG (m_reg
);
2415 && HARD_REGISTER_P (nop_reg
)
2416 && REG_USERVAR_P (nop_reg
)
2418 && HARD_REGISTER_P (m_reg
)
2419 && REG_USERVAR_P (m_reg
))
2423 for (i
= 0; i
< early_clobbered_regs_num
; i
++)
2424 if (m
== early_clobbered_nops
[i
])
2426 if (i
< early_clobbered_regs_num
2431 /* Both operands must allow a reload register,
2432 otherwise we cannot make them match. */
2433 if (curr_alt
[m
] == NO_REGS
)
2435 /* Retroactively mark the operand we had to
2436 match as a loser, if it wasn't already and
2437 it wasn't matched to a register constraint
2438 (e.g it might be matched by memory). */
2440 && (operand_reg
[m
] == NULL_RTX
2441 || hard_regno
[m
] < 0))
2445 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2446 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2449 /* Prefer matching earlyclobber alternative as
2450 it results in less hard regs required for
2451 the insn than a non-matching earlyclobber
2453 if (TEST_BIT (curr_static_id
->operand
[m
]
2454 .early_clobber_alts
, nalt
))
2456 if (lra_dump_file
!= NULL
)
2459 " %d Matching earlyclobber alt:"
2462 if (!matching_early_clobber
[m
])
2465 matching_early_clobber
[m
] = 1;
2468 /* Otherwise we prefer no matching
2469 alternatives because it gives more freedom
2471 else if (operand_reg
[nop
] == NULL_RTX
2472 || (find_regno_note (curr_insn
, REG_DEAD
,
2473 REGNO (operand_reg
[nop
]))
2476 if (lra_dump_file
!= NULL
)
2479 " %d Matching alt: reject+=2\n",
2484 /* If we have to reload this operand and some
2485 previous operand also had to match the same
2486 thing as this operand, we don't know how to do
2488 if (!match_p
|| !curr_alt_win
[m
])
2490 for (i
= 0; i
< nop
; i
++)
2491 if (curr_alt_matches
[i
] == m
)
2499 this_alternative_matches
= m
;
2500 /* This can be fixed with reloads if the operand
2501 we are supposed to match can be fixed with
2504 this_alternative
= curr_alt
[m
];
2505 this_alternative_set
= curr_alt_set
[m
];
2506 this_alternative_exclude_start_hard_regs
2507 = curr_alt_exclude_start_hard_regs
[m
];
2508 winreg
= this_alternative
!= NO_REGS
;
2514 || general_constant_p (op
)
2515 || spilled_pseudo_p (op
))
2518 cl_filter
= nullptr;
2522 cn
= lookup_constraint (p
);
2523 switch (get_constraint_type (cn
))
2526 cl
= reg_class_for_constraint (cn
);
2529 cl_filter
= get_register_filter (cn
);
2535 if (CONST_INT_P (op
)
2536 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2541 case CT_RELAXED_MEMORY
:
2543 && satisfies_memory_constraint_p (op
, cn
))
2545 else if (spilled_pseudo_p (op
))
2548 /* If we didn't already win, we can reload constants
2549 via force_const_mem or put the pseudo value into
2550 memory, or make other memory by reloading the
2551 address like for 'o'. */
2552 if (CONST_POOL_OK_P (mode
, op
)
2553 || MEM_P (op
) || REG_P (op
)
2554 /* We can restore the equiv insn by a
2556 || equiv_substition_p
[nop
])
2563 /* An asm operand with an address constraint
2564 that doesn't satisfy address_operand has
2565 is_address cleared, so that we don't try to
2566 make a non-address fit. */
2567 if (!curr_static_id
->operand
[nop
].is_address
)
2569 /* If we didn't already win, we can reload the address
2570 into a base register. */
2571 if (satisfies_address_constraint_p (op
, cn
))
2573 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2575 cl_filter
= nullptr;
2580 if (constraint_satisfied_p (op
, cn
))
2584 case CT_SPECIAL_MEMORY
:
2585 if (satisfies_memory_constraint_p (op
, cn
))
2587 else if (spilled_pseudo_p (op
))
2589 curr_reuse_alt_p
= false;
2597 if (mode
== BLKmode
)
2599 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2600 if (hard_reg_set_subset_p (this_alternative_set
,
2601 reg_class_contents
[cl
]))
2602 this_alternative_exclude_start_hard_regs
2603 = ira_exclude_class_mode_regs
[cl
][mode
];
2604 else if (!hard_reg_set_subset_p (reg_class_contents
[cl
],
2605 this_alternative_set
))
2606 this_alternative_exclude_start_hard_regs
2607 |= ira_exclude_class_mode_regs
[cl
][mode
];
2608 this_alternative_set
|= reg_class_contents
[cl
];
2610 this_alternative_exclude_start_hard_regs
|= ~*cl_filter
;
2613 this_costly_alternative
2614 = reg_class_subunion
[this_costly_alternative
][cl
];
2615 this_costly_alternative_set
|= reg_class_contents
[cl
];
2621 if (hard_regno
[nop
] >= 0
2622 && in_hard_reg_set_p (this_alternative_set
,
2623 mode
, hard_regno
[nop
])
2625 || TEST_HARD_REG_BIT (*cl_filter
,
2627 && ((REG_ATTRS (op
) && (decl
= REG_EXPR (op
)) != NULL
2628 && VAR_P (decl
) && DECL_HARD_REGISTER (decl
))
2629 || !(TEST_HARD_REG_BIT
2630 (this_alternative_exclude_start_hard_regs
,
2633 else if (hard_regno
[nop
] < 0
2634 && in_class_p (op
, this_alternative
, NULL
))
2639 if (c
!= ' ' && c
!= '\t')
2640 costly_p
= c
== '*';
2642 while ((p
+= len
), c
);
2644 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2645 && ira_former_scratch_p (REGNO (operand_reg
[nop
])));
2646 /* Record which operands fit this alternative. */
2649 this_alternative_win
= true;
2650 if (operand_reg
[nop
] != NULL_RTX
)
2652 if (hard_regno
[nop
] >= 0)
2654 if (in_hard_reg_set_p (this_costly_alternative_set
,
2655 mode
, hard_regno
[nop
]))
2657 if (lra_dump_file
!= NULL
)
2658 fprintf (lra_dump_file
,
2659 " %d Costly set: reject++\n",
2666 /* Prefer won reg to spilled pseudo under other
2667 equal conditions for possibe inheritance. */
2670 if (lra_dump_file
!= NULL
)
2673 " %d Non pseudo reload: reject++\n",
2677 if (in_class_p (operand_reg
[nop
],
2678 this_costly_alternative
, NULL
))
2680 if (lra_dump_file
!= NULL
)
2683 " %d Non pseudo costly reload:"
2689 /* We simulate the behavior of old reload here.
2690 Although scratches need hard registers and it
2691 might result in spilling other pseudos, no reload
2692 insns are generated for the scratches. So it
2693 might cost something but probably less than old
2694 reload pass believes. */
2697 if (lra_dump_file
!= NULL
)
2698 fprintf (lra_dump_file
,
2699 " %d Scratch win: reject+=2\n",
2706 this_alternative_match_win
= true;
2709 int const_to_mem
= 0;
2712 reject
+= op_reject
;
2713 /* Mark output reload of the stack pointer. */
2714 if (op
== stack_pointer_rtx
2715 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2716 curr_alt_out_sp_reload_p
= true;
2718 /* If this alternative asks for a specific reg class, see if there
2719 is at least one allocatable register in that class. */
2721 = (this_alternative
== NO_REGS
2722 || (hard_reg_set_subset_p
2723 (reg_class_contents
[this_alternative
],
2724 lra_no_alloc_regs
)));
2726 /* For asms, verify that the class for this alternative is possible
2727 for the mode that is specified. */
2728 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2731 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2732 if (targetm
.hard_regno_mode_ok (i
, mode
)
2733 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2736 if (i
== FIRST_PSEUDO_REGISTER
)
2740 /* If this operand accepts a register, and if the
2741 register class has at least one allocatable register,
2742 then this operand can be reloaded. */
2743 if (winreg
&& !no_regs_p
)
2748 if (lra_dump_file
!= NULL
)
2749 fprintf (lra_dump_file
,
2750 " Bad operand -- refuse\n");
2754 if (this_alternative
!= NO_REGS
)
2756 HARD_REG_SET available_regs
2757 = (reg_class_contents
[this_alternative
]
2758 & ~((ira_prohibited_class_mode_regs
2759 [this_alternative
][mode
])
2760 | lra_no_alloc_regs
));
2761 if (hard_reg_set_empty_p (available_regs
))
2763 /* There are no hard regs holding a value of given
2767 this_alternative
= NO_REGS
;
2768 if (lra_dump_file
!= NULL
)
2769 fprintf (lra_dump_file
,
2770 " %d Using memory because of"
2771 " a bad mode: reject+=2\n",
2777 if (lra_dump_file
!= NULL
)
2778 fprintf (lra_dump_file
,
2779 " Wrong mode -- refuse\n");
2785 /* If not assigned pseudo has a class which a subset of
2786 required reg class, it is a less costly alternative
2787 as the pseudo still can get a hard reg of necessary
2789 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2790 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2791 && ira_class_subset_p
[this_alternative
][cl
])
2793 if (lra_dump_file
!= NULL
)
2796 " %d Super set class reg: reject-=3\n", nop
);
2800 this_alternative_offmemok
= offmemok
;
2801 if (this_costly_alternative
!= NO_REGS
)
2803 if (lra_dump_file
!= NULL
)
2804 fprintf (lra_dump_file
,
2805 " %d Costly loser: reject++\n", nop
);
2808 /* If the operand is dying, has a matching constraint,
2809 and satisfies constraints of the matched operand
2810 which failed to satisfy the own constraints, most probably
2811 the reload for this operand will be gone. */
2812 if (this_alternative_matches
>= 0
2813 && !curr_alt_win
[this_alternative_matches
]
2815 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2816 && (hard_regno
[nop
] >= 0
2817 ? in_hard_reg_set_p (this_alternative_set
,
2818 mode
, hard_regno
[nop
])
2819 : in_class_p (op
, this_alternative
, NULL
)))
2821 if (lra_dump_file
!= NULL
)
2824 " %d Dying matched operand reload: reject++\n",
2830 /* Strict_low_part requires to reload the register
2831 not the sub-register. In this case we should
2832 check that a final reload hard reg can hold the
2834 if (curr_static_id
->operand
[nop
].strict_low
2836 && hard_regno
[nop
] < 0
2837 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2838 && ira_class_hard_regs_num
[this_alternative
] > 0
2839 && (!targetm
.hard_regno_mode_ok
2840 (ira_class_hard_regs
[this_alternative
][0],
2841 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2843 if (lra_dump_file
!= NULL
)
2846 " Strict low subreg reload -- refuse\n");
2851 if (operand_reg
[nop
] != NULL_RTX
2852 /* Output operands and matched input operands are
2853 not inherited. The following conditions do not
2854 exactly describe the previous statement but they
2855 are pretty close. */
2856 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2857 && (this_alternative_matches
< 0
2858 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2860 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2864 /* The value of reload_sum has sense only if we
2865 process insns in their order. It happens only on
2866 the first constraints sub-pass when we do most of
2868 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2869 reload_sum
+= last_reload
- bb_reload_num
;
2871 /* If this is a constant that is reloaded into the
2872 desired class by copying it to memory first, count
2873 that as another reload. This is consistent with
2874 other code and is required to avoid choosing another
2875 alternative when the constant is moved into memory.
2876 Note that the test here is precisely the same as in
2877 the code below that calls force_const_mem. */
2878 if (CONST_POOL_OK_P (mode
, op
)
2879 && ((targetm
.preferred_reload_class
2880 (op
, this_alternative
) == NO_REGS
)
2881 || no_input_reloads_p
))
2888 /* Alternative loses if it requires a type of reload not
2889 permitted for this insn. We can always reload
2890 objects with a REG_UNUSED note. */
2891 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2892 && no_output_reloads_p
2893 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2894 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2895 && no_input_reloads_p
&& ! const_to_mem
)
2896 || (this_alternative_matches
>= 0
2897 && (no_input_reloads_p
2898 || (no_output_reloads_p
2899 && (curr_static_id
->operand
2900 [this_alternative_matches
].type
!= OP_IN
)
2901 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2902 no_subreg_reg_operand
2903 [this_alternative_matches
])))))
2905 if (lra_dump_file
!= NULL
)
2908 " No input/output reload -- refuse\n");
2912 /* Alternative loses if it required class pseudo cannot
2913 hold value of required mode. Such insns can be
2914 described by insn definitions with mode iterators. */
2915 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2916 && ! hard_reg_set_empty_p (this_alternative_set
)
2917 /* It is common practice for constraints to use a
2918 class which does not have actually enough regs to
2919 hold the value (e.g. x86 AREG for mode requiring
2920 more one general reg). Therefore we have 2
2921 conditions to check that the reload pseudo cannot
2922 hold the mode value. */
2923 && (!targetm
.hard_regno_mode_ok
2924 (ira_class_hard_regs
[this_alternative
][0],
2925 GET_MODE (*curr_id
->operand_loc
[nop
])))
2926 /* The above condition is not enough as the first
2927 reg in ira_class_hard_regs can be not aligned for
2928 multi-words mode values. */
2929 && (prohibited_class_reg_set_mode_p
2930 (this_alternative
, this_alternative_set
,
2931 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2933 if (lra_dump_file
!= NULL
)
2934 fprintf (lra_dump_file
,
2935 " reload pseudo for op %d "
2936 "cannot hold the mode value -- refuse\n",
2941 /* Check strong discouragement of reload of non-constant
2942 into class THIS_ALTERNATIVE. */
2943 if (! CONSTANT_P (op
) && ! no_regs_p
2944 && (targetm
.preferred_reload_class
2945 (op
, this_alternative
) == NO_REGS
2946 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2947 && (targetm
.preferred_output_reload_class
2948 (op
, this_alternative
) == NO_REGS
))))
2950 if (offmemok
&& REG_P (op
))
2952 if (lra_dump_file
!= NULL
)
2955 " %d Spill pseudo into memory: reject+=3\n",
2961 if (lra_dump_file
!= NULL
)
2964 " %d Non-prefered reload: reject+=%d\n",
2965 nop
, LRA_MAX_REJECT
);
2966 reject
+= LRA_MAX_REJECT
;
2970 if (! (MEM_P (op
) && offmemok
)
2971 && ! (const_to_mem
&& constmemok
))
2973 /* We prefer to reload pseudos over reloading other
2974 things, since such reloads may be able to be
2975 eliminated later. So bump REJECT in other cases.
2976 Don't do this in the case where we are forcing a
2977 constant into memory and it will then win since
2978 we don't want to have a different alternative
2980 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2982 if (lra_dump_file
!= NULL
)
2985 " %d Non-pseudo reload: reject+=2\n",
2992 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2994 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2996 if (lra_dump_file
!= NULL
)
2999 " %d Small class reload: reject+=%d\n",
3000 nop
, LRA_LOSER_COST_FACTOR
/ 2);
3001 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
3005 /* We are trying to spill pseudo into memory. It is
3006 usually more costly than moving to a hard register
3007 although it might takes the same number of
3010 Non-pseudo spill may happen also. Suppose a target allows both
3011 register and memory in the operand constraint alternatives,
3012 then it's typical that an eliminable register has a substition
3013 of "base + offset" which can either be reloaded by a simple
3014 "new_reg <= base + offset" which will match the register
3015 constraint, or a similar reg addition followed by further spill
3016 to and reload from memory which will match the memory
3017 constraint, but this memory spill will be much more costly
3020 Code below increases the reject for both pseudo and non-pseudo
3023 && !(MEM_P (op
) && offmemok
)
3024 && !(REG_P (op
) && hard_regno
[nop
] < 0))
3026 if (lra_dump_file
!= NULL
)
3029 " %d Spill %spseudo into memory: reject+=3\n",
3030 nop
, REG_P (op
) ? "" : "Non-");
3032 if (VECTOR_MODE_P (mode
))
3034 /* Spilling vectors into memory is usually more
3035 costly as they contain big values. */
3036 if (lra_dump_file
!= NULL
)
3039 " %d Spill vector pseudo: reject+=2\n",
3045 /* When we use an operand requiring memory in given
3046 alternative, the insn should write *and* read the
3047 value to/from memory it is costly in comparison with
3048 an insn alternative which does not use memory
3049 (e.g. register or immediate operand). We exclude
3050 memory operand for such case as we can satisfy the
3051 memory constraints by reloading address. */
3052 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
3054 if (lra_dump_file
!= NULL
)
3057 " Using memory insn operand %d: reject+=3\n",
3062 /* If reload requires moving value through secondary
3063 memory, it will need one more insn at least. */
3064 if (this_alternative
!= NO_REGS
3065 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
3066 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
3067 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
3069 || (curr_static_id
->operand
[nop
].type
!= OP_IN
3070 && (targetm
.secondary_memory_needed
3071 (GET_MODE (op
), this_alternative
, cl
)))))
3074 if (MEM_P (op
) && offmemok
)
3078 /* Input reloads can be inherited more often than
3079 output reloads can be removed, so penalize output
3081 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
3083 if (lra_dump_file
!= NULL
)
3086 " %d Non input pseudo reload: reject++\n",
3091 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
3093 if (lra_dump_file
!= NULL
)
3096 " %d Input/Output reload: reject+=%d\n",
3097 nop
, LRA_LOSER_COST_FACTOR
);
3098 reject
+= LRA_LOSER_COST_FACTOR
;
3103 if (early_clobber_p
&& ! scratch_p
)
3105 if (lra_dump_file
!= NULL
)
3106 fprintf (lra_dump_file
,
3107 " %d Early clobber: reject++\n", nop
);
3110 /* ??? We check early clobbers after processing all operands
3111 (see loop below) and there we update the costs more.
3112 Should we update the cost (may be approximately) here
3113 because of early clobber register reloads or it is a rare
3114 or non-important thing to be worth to do it. */
3115 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
3116 - (addr_losers
== losers
? static_reject
: 0));
3117 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
3119 if (lra_dump_file
!= NULL
)
3120 fprintf (lra_dump_file
,
3121 " overall=%d,losers=%d -- refuse\n",
3126 if (update_and_check_small_class_inputs (nop
, nalt
,
3129 if (lra_dump_file
!= NULL
)
3130 fprintf (lra_dump_file
,
3131 " not enough small class regs -- refuse\n");
3134 curr_alt
[nop
] = this_alternative
;
3135 curr_alt_set
[nop
] = this_alternative_set
;
3136 curr_alt_exclude_start_hard_regs
[nop
]
3137 = this_alternative_exclude_start_hard_regs
;
3138 curr_alt_win
[nop
] = this_alternative_win
;
3139 curr_alt_match_win
[nop
] = this_alternative_match_win
;
3140 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
3141 curr_alt_matches
[nop
] = this_alternative_matches
;
3143 if (this_alternative_matches
>= 0
3144 && !did_match
&& !this_alternative_win
)
3145 curr_alt_win
[this_alternative_matches
] = false;
3147 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
3148 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
3151 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
3152 /* Prevent processing non-move insns. */
3153 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
3154 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
3155 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
3156 && REG_P (no_subreg_reg_operand
[0])
3157 && REG_P (no_subreg_reg_operand
[1])
3158 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
3159 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
3160 || (! curr_alt_win
[0] && curr_alt_win
[1]
3161 && REG_P (no_subreg_reg_operand
[1])
3162 /* Check that we reload memory not the memory
3164 && ! (curr_alt_offmemok
[0]
3165 && MEM_P (no_subreg_reg_operand
[0]))
3166 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
3167 || (curr_alt_win
[0] && ! curr_alt_win
[1]
3168 && REG_P (no_subreg_reg_operand
[0])
3169 /* Check that we reload memory not the memory
3171 && ! (curr_alt_offmemok
[1]
3172 && MEM_P (no_subreg_reg_operand
[1]))
3173 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
3174 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
3175 no_subreg_reg_operand
[1])
3176 || (targetm
.preferred_reload_class
3177 (no_subreg_reg_operand
[1],
3178 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
3179 /* If it is a result of recent elimination in move
3180 insn we can transform it into an add still by
3181 using this alternative. */
3182 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
3183 /* Likewise if the source has been replaced with an
3184 equivalent value. This only happens once -- the reload
3185 will use the equivalent value instead of the register it
3186 replaces -- so there should be no danger of cycling. */
3187 && !equiv_substition_p
[1])))
3189 /* We have a move insn and a new reload insn will be similar
3190 to the current insn. We should avoid such situation as
3191 it results in LRA cycling. */
3192 if (lra_dump_file
!= NULL
)
3193 fprintf (lra_dump_file
,
3194 " Cycle danger: overall += LRA_MAX_REJECT\n");
3195 overall
+= LRA_MAX_REJECT
;
3198 curr_alt_dont_inherit_ops_num
= 0;
3199 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
3201 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
3202 HARD_REG_SET temp_set
;
3204 i
= early_clobbered_nops
[nop
];
3205 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
3206 || hard_regno
[i
] < 0)
3208 lra_assert (operand_reg
[i
] != NULL_RTX
);
3209 clobbered_hard_regno
= hard_regno
[i
];
3210 CLEAR_HARD_REG_SET (temp_set
);
3211 add_to_hard_reg_set (&temp_set
, GET_MODE (*curr_id
->operand_loc
[i
]),
3212 clobbered_hard_regno
);
3213 first_conflict_j
= last_conflict_j
= -1;
3214 for (j
= 0; j
< n_operands
; j
++)
3216 /* We don't want process insides of match_operator and
3217 match_parallel because otherwise we would process
3218 their operands once again generating a wrong
3220 || curr_static_id
->operand
[j
].is_operator
)
3222 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
3223 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
3225 /* If we don't reload j-th operand, check conflicts. */
3226 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
3227 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
3229 if (first_conflict_j
< 0)
3230 first_conflict_j
= j
;
3231 last_conflict_j
= j
;
3232 /* Both the earlyclobber operand and conflicting operand
3233 cannot both be user defined hard registers. */
3234 if (HARD_REGISTER_P (operand_reg
[i
])
3235 && REG_USERVAR_P (operand_reg
[i
])
3236 && operand_reg
[j
] != NULL_RTX
3237 && HARD_REGISTER_P (operand_reg
[j
])
3238 && REG_USERVAR_P (operand_reg
[j
]))
3240 /* For asm, let curr_insn_transform diagnose it. */
3241 if (INSN_CODE (curr_insn
) < 0)
3243 fatal_insn ("unable to generate reloads for "
3244 "impossible constraints:", curr_insn
);
3247 if (last_conflict_j
< 0)
3250 /* If an earlyclobber operand conflicts with another non-matching
3251 operand (ie, they have been assigned the same hard register),
3252 then it is better to reload the other operand, as there may
3253 exist yet another operand with a matching constraint associated
3254 with the earlyclobber operand. However, if one of the operands
3255 is an explicit use of a hard register, then we must reload the
3256 other non-hard register operand. */
3257 if (HARD_REGISTER_P (operand_reg
[i
])
3258 || (first_conflict_j
== last_conflict_j
3259 && operand_reg
[last_conflict_j
] != NULL_RTX
3260 && !curr_alt_match_win
[last_conflict_j
]
3261 && !HARD_REGISTER_P (operand_reg
[last_conflict_j
])))
3263 curr_alt_win
[last_conflict_j
] = false;
3264 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
3267 if (lra_dump_file
!= NULL
)
3270 " %d Conflict early clobber reload: reject--\n",
3275 /* We need to reload early clobbered register and the
3276 matched registers. */
3277 for (j
= 0; j
< n_operands
; j
++)
3278 if (curr_alt_matches
[j
] == i
)
3280 curr_alt_match_win
[j
] = false;
3282 overall
+= LRA_LOSER_COST_FACTOR
;
3284 if (! curr_alt_match_win
[i
])
3285 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
3288 /* Remember pseudos used for match reloads are never
3290 lra_assert (curr_alt_matches
[i
] >= 0);
3291 curr_alt_win
[curr_alt_matches
[i
]] = false;
3293 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
3295 if (lra_dump_file
!= NULL
)
3298 " %d Matched conflict early clobber reloads: "
3302 /* Early clobber was already reflected in REJECT. */
3303 if (!matching_early_clobber
[i
])
3305 lra_assert (reject
> 0);
3307 matching_early_clobber
[i
] = 1;
3309 overall
+= LRA_LOSER_COST_FACTOR
- 1;
3311 if (lra_dump_file
!= NULL
)
3312 fprintf (lra_dump_file
, " overall=%d,losers=%d,rld_nregs=%d\n",
3313 overall
, losers
, reload_nregs
);
3315 /* If this alternative can be made to work by reloading, and it
3316 needs less reloading than the others checked so far, record
3317 it as the chosen goal for reloading. */
3318 if ((best_losers
!= 0 && losers
== 0)
3319 || (((best_losers
== 0 && losers
== 0)
3320 || (best_losers
!= 0 && losers
!= 0))
3321 && (best_overall
> overall
3322 || (best_overall
== overall
3323 /* If the cost of the reloads is the same,
3324 prefer alternative which requires minimal
3325 number of reload regs. */
3326 && (reload_nregs
< best_reload_nregs
3327 || (reload_nregs
== best_reload_nregs
3328 && (best_reload_sum
< reload_sum
3329 || (best_reload_sum
== reload_sum
3330 && nalt
< goal_alt_number
))))))))
3332 for (nop
= 0; nop
< n_operands
; nop
++)
3334 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3335 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3336 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3337 goal_alt
[nop
] = curr_alt
[nop
];
3338 goal_alt_exclude_start_hard_regs
[nop
]
3339 = curr_alt_exclude_start_hard_regs
[nop
];
3340 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3342 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3343 goal_reuse_alt_p
= curr_reuse_alt_p
;
3344 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3345 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3346 goal_alt_swapped
= curr_swapped
;
3347 goal_alt_out_sp_reload_p
= curr_alt_out_sp_reload_p
;
3348 best_overall
= overall
;
3349 best_losers
= losers
;
3350 best_reload_nregs
= reload_nregs
;
3351 best_reload_sum
= reload_sum
;
3352 goal_alt_number
= nalt
;
3355 /* Everything is satisfied. Do not process alternatives
3364 /* Make reload base reg from address AD. */
3366 base_to_reg (struct address_info
*ad
)
3370 rtx new_inner
= NULL_RTX
;
3371 rtx new_reg
= NULL_RTX
;
3373 rtx_insn
*last_insn
= get_last_insn();
3375 lra_assert (ad
->disp
== ad
->disp_term
);
3376 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3377 get_index_code (ad
));
3378 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
, cl
, NULL
,
3380 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3381 ad
->disp_term
== NULL
3384 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3386 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3387 code
= recog_memoized (insn
);
3390 delete_insns_since (last_insn
);
3397 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3399 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3404 lra_assert (ad
->base
== ad
->base_term
);
3405 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3406 get_index_code (ad
));
3407 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
, cl
, NULL
,
3409 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3413 /* Make reload of index part of address AD. Return the new
3416 index_part_to_reg (struct address_info
*ad
, enum reg_class index_class
)
3420 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3421 index_class
, NULL
, "index term");
3422 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3423 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3427 /* Return true if we can add a displacement to address AD, even if that
3428 makes the address invalid. The fix-up code requires any new address
3429 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3431 can_add_disp_p (struct address_info
*ad
)
3433 return (!ad
->autoinc_p
3434 && ad
->segment
== NULL
3435 && ad
->base
== ad
->base_term
3436 && ad
->disp
== ad
->disp_term
);
3439 /* Make equiv substitution in address AD. Return true if a substitution
3442 equiv_address_substitution (struct address_info
*ad
)
3444 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3446 HOST_WIDE_INT scale
;
3449 base_term
= strip_subreg (ad
->base_term
);
3450 if (base_term
== NULL
)
3451 base_reg
= new_base_reg
= NULL_RTX
;
3454 base_reg
= *base_term
;
3455 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3457 index_term
= strip_subreg (ad
->index_term
);
3458 if (index_term
== NULL
)
3459 index_reg
= new_index_reg
= NULL_RTX
;
3462 index_reg
= *index_term
;
3463 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3465 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3469 if (lra_dump_file
!= NULL
)
3471 fprintf (lra_dump_file
, "Changing address in insn %d ",
3472 INSN_UID (curr_insn
));
3473 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3475 if (base_reg
!= new_base_reg
)
3478 if (REG_P (new_base_reg
))
3480 *base_term
= new_base_reg
;
3483 else if (GET_CODE (new_base_reg
) == PLUS
3484 && REG_P (XEXP (new_base_reg
, 0))
3485 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3486 && can_add_disp_p (ad
))
3489 *base_term
= XEXP (new_base_reg
, 0);
3492 if (ad
->base_term2
!= NULL
)
3493 *ad
->base_term2
= *ad
->base_term
;
3495 if (index_reg
!= new_index_reg
)
3498 if (REG_P (new_index_reg
))
3500 *index_term
= new_index_reg
;
3503 else if (GET_CODE (new_index_reg
) == PLUS
3504 && REG_P (XEXP (new_index_reg
, 0))
3505 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3506 && can_add_disp_p (ad
)
3507 && (scale
= get_index_scale (ad
)))
3509 disp
+= offset
* scale
;
3510 *index_term
= XEXP (new_index_reg
, 0);
3514 if (maybe_ne (disp
, 0))
3516 if (ad
->disp
!= NULL
)
3517 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3520 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3521 update_address (ad
);
3525 if (lra_dump_file
!= NULL
)
3528 fprintf (lra_dump_file
, " -- no change\n");
3531 fprintf (lra_dump_file
, " on equiv ");
3532 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3533 fprintf (lra_dump_file
, "\n");
3539 /* Skip all modifiers and whitespaces in constraint STR and return the
3542 skip_constraint_modifiers (const char *str
)
3547 case '+': case '&' : case '=': case '*': case ' ': case '\t':
3548 case '$': case '^' : case '%': case '?': case '!':
3550 default: return str
;
3554 /* Takes a string of 0 or more comma-separated constraints. When more
3555 than one constraint is present, evaluate whether they all correspond
3556 to a single, repeated constraint (e.g. "r,r") or whether we have
3557 more than one distinct constraints (e.g. "r,m"). */
3559 constraint_unique (const char *cstr
)
3561 enum constraint_num ca
, cb
;
3562 ca
= CONSTRAINT__UNKNOWN
;
3565 cstr
= skip_constraint_modifiers (cstr
);
3566 if (*cstr
== '\0' || *cstr
== ',')
3570 cb
= lookup_constraint (cstr
);
3571 if (cb
== CONSTRAINT__UNKNOWN
)
3573 cstr
+= CONSTRAINT_LEN (cstr
[0], cstr
);
3575 /* Handle the first iteration of the loop. */
3576 if (ca
== CONSTRAINT__UNKNOWN
)
3578 /* Handle the general case of comparing ca with subsequent
3589 /* Major function to make reloads for an address in operand NOP or
3590 check its correctness (If CHECK_ONLY_P is true). The supported
3593 1) an address that existed before LRA started, at which point it
3594 must have been valid. These addresses are subject to elimination
3595 and may have become invalid due to the elimination offset being out
3598 2) an address created by forcing a constant to memory
3599 (force_const_to_mem). The initial form of these addresses might
3600 not be valid, and it is this function's job to make them valid.
3602 3) a frame address formed from a register and a (possibly zero)
3603 constant offset. As above, these addresses might not be valid and
3604 this function must make them so.
3606 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3607 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3608 address. Return true for any RTL change.
3610 The function is a helper function which does not produce all
3611 transformations (when CHECK_ONLY_P is false) which can be
3612 necessary. It does just basic steps. To do all necessary
3613 transformations use function process_address. */
3615 process_address_1 (int nop
, bool check_only_p
,
3616 rtx_insn
**before
, rtx_insn
**after
)
3618 struct address_info ad
;
3620 HOST_WIDE_INT scale
;
3621 rtx op
= *curr_id
->operand_loc
[nop
];
3622 rtx mem
= extract_mem_from_operand (op
);
3623 const char *constraint
;
3624 enum constraint_num cn
;
3625 bool change_p
= false;
3628 && GET_MODE (mem
) == BLKmode
3629 && GET_CODE (XEXP (mem
, 0)) == SCRATCH
)
3633 = skip_constraint_modifiers (curr_static_id
->operand
[nop
].constraint
);
3634 if (IN_RANGE (constraint
[0], '0', '9'))
3637 unsigned long dup
= strtoul (constraint
, &end
, 10);
3639 = skip_constraint_modifiers (curr_static_id
->operand
[dup
].constraint
);
3641 cn
= lookup_constraint (*constraint
== '\0' ? "X" : constraint
);
3642 /* If we have several alternatives or/and several constraints in an
3643 alternative and we can not say at this stage what constraint will be used,
3644 use unknown constraint. The exception is an address constraint. If
3645 operand has one address constraint, probably all others constraints are
3647 if (constraint
[0] != '\0' && get_constraint_type (cn
) != CT_ADDRESS
3648 && !constraint_unique (constraint
))
3649 cn
= CONSTRAINT__UNKNOWN
;
3650 if (insn_extra_address_constraint (cn
)
3651 /* When we find an asm operand with an address constraint that
3652 doesn't satisfy address_operand to begin with, we clear
3653 is_address, so that we don't try to make a non-address fit.
3654 If the asm statement got this far, it's because other
3655 constraints are available, and we'll use them, disregarding
3656 the unsatisfiable address ones. */
3657 && curr_static_id
->operand
[nop
].is_address
)
3658 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3659 /* Do not attempt to decompose arbitrary addresses generated by combine
3660 for asm operands with loose constraints, e.g 'X'.
3661 Need to extract memory from op for special memory constraint,
3662 i.e. bcst_mem_operand in i386 backend. */
3663 else if (MEM_P (mem
)
3664 && !(INSN_CODE (curr_insn
) < 0
3665 && get_constraint_type (cn
) == CT_FIXED_FORM
3666 && constraint_satisfied_p (op
, cn
)))
3667 decompose_mem_address (&ad
, mem
);
3668 else if (GET_CODE (op
) == SUBREG
3669 && MEM_P (SUBREG_REG (op
)))
3670 decompose_mem_address (&ad
, SUBREG_REG (op
));
3673 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3674 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3675 when INDEX_REG_CLASS is a single register class. */
3676 enum reg_class index_cl
= index_reg_class (curr_insn
);
3677 if (ad
.base_term
!= NULL
3678 && ad
.index_term
!= NULL
3679 && ira_class_hard_regs_num
[index_cl
] == 1
3680 && REG_P (*ad
.base_term
)
3681 && REG_P (*ad
.index_term
)
3682 && in_class_p (*ad
.base_term
, index_cl
, NULL
)
3683 && ! in_class_p (*ad
.index_term
, index_cl
, NULL
))
3685 std::swap (ad
.base
, ad
.index
);
3686 std::swap (ad
.base_term
, ad
.index_term
);
3689 change_p
= equiv_address_substitution (&ad
);
3690 if (ad
.base_term
!= NULL
3691 && (process_addr_reg
3692 (ad
.base_term
, check_only_p
, before
,
3694 && !(REG_P (*ad
.base_term
)
3695 && find_regno_note (curr_insn
, REG_DEAD
,
3696 REGNO (*ad
.base_term
)) != NULL_RTX
)
3698 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3699 get_index_code (&ad
), curr_insn
))))
3702 if (ad
.base_term2
!= NULL
)
3703 *ad
.base_term2
= *ad
.base_term
;
3705 if (ad
.index_term
!= NULL
3706 && process_addr_reg (ad
.index_term
, check_only_p
,
3707 before
, NULL
, index_cl
))
3710 /* Target hooks sometimes don't treat extra-constraint addresses as
3711 legitimate address_operands, so handle them specially. */
3712 if (insn_extra_address_constraint (cn
)
3713 && satisfies_address_constraint_p (&ad
, cn
))
3719 /* There are three cases where the shape of *AD.INNER may now be invalid:
3721 1) the original address was valid, but either elimination or
3722 equiv_address_substitution was applied and that made
3723 the address invalid.
3725 2) the address is an invalid symbolic address created by
3728 3) the address is a frame address with an invalid offset.
3730 4) the address is a frame address with an invalid base.
3732 All these cases involve a non-autoinc address, so there is no
3733 point revalidating other types. */
3734 if (ad
.autoinc_p
|| valid_address_p (op
, &ad
, cn
))
3737 /* Any index existed before LRA started, so we can assume that the
3738 presence and shape of the index is valid. */
3739 push_to_sequence (*before
);
3740 lra_assert (ad
.disp
== ad
.disp_term
);
3741 if (ad
.base
== NULL
)
3743 if (ad
.index
== NULL
)
3746 rtx_insn
*last
= get_last_insn ();
3748 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3751 rtx addr
= *ad
.inner
;
3753 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "addr");
3756 /* addr => lo_sum (new_base, addr), case (2) above. */
3757 insn
= emit_insn (gen_rtx_SET
3759 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3760 code
= recog_memoized (insn
);
3763 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3764 if (!valid_address_p (op
, &ad
, cn
))
3766 /* Try to put lo_sum into register. */
3767 insn
= emit_insn (gen_rtx_SET
3769 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3770 code
= recog_memoized (insn
);
3773 *ad
.inner
= new_reg
;
3774 if (!valid_address_p (op
, &ad
, cn
))
3784 delete_insns_since (last
);
3789 /* addr => new_base, case (2) above. */
3790 lra_emit_move (new_reg
, addr
);
3792 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3794 insn
= NEXT_INSN (insn
))
3795 if (recog_memoized (insn
) < 0)
3797 if (insn
!= NULL_RTX
)
3799 /* Do nothing if we cannot generate right insns.
3800 This is analogous to reload pass behavior. */
3801 delete_insns_since (last
);
3805 *ad
.inner
= new_reg
;
3810 /* index * scale + disp => new base + index * scale,
3812 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3813 GET_CODE (*ad
.index
),
3816 lra_assert (index_cl
!= NO_REGS
);
3817 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "disp");
3818 lra_emit_move (new_reg
, *ad
.disp
);
3819 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3820 new_reg
, *ad
.index
);
3823 else if (ad
.index
== NULL
)
3828 rtx_insn
*insns
, *last_insn
;
3829 /* Try to reload base into register only if the base is invalid
3830 for the address but with valid offset, case (4) above. */
3832 new_reg
= base_to_reg (&ad
);
3834 /* base + disp => new base, cases (1) and (3) above. */
3835 /* Another option would be to reload the displacement into an
3836 index register. However, postreload has code to optimize
3837 address reloads that have the same base and different
3838 displacements, so reloading into an index register would
3839 not necessarily be a win. */
3840 if (new_reg
== NULL_RTX
)
3842 /* See if the target can split the displacement into a
3843 legitimate new displacement from a local anchor. */
3844 gcc_assert (ad
.disp
== ad
.disp_term
);
3845 poly_int64 orig_offset
;
3846 rtx offset1
, offset2
;
3847 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3848 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3852 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3853 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3856 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3858 insns
= get_insns ();
3859 last_insn
= get_last_insn ();
3860 /* If we generated at least two insns, try last insn source as
3861 an address. If we succeed, we generate one less insn. */
3863 && last_insn
!= insns
3864 && (set
= single_set (last_insn
)) != NULL_RTX
3865 && GET_CODE (SET_SRC (set
)) == PLUS
3866 && REG_P (XEXP (SET_SRC (set
), 0))
3867 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3869 *ad
.inner
= SET_SRC (set
);
3870 if (valid_address_p (op
, &ad
, cn
))
3872 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3873 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3874 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3875 get_index_code (&ad
), curr_insn
);
3876 regno
= REGNO (*ad
.base_term
);
3877 if (regno
>= FIRST_PSEUDO_REGISTER
3878 && cl
!= lra_get_allocno_class (regno
))
3879 lra_change_class (regno
, cl
, " Change to", true);
3880 new_reg
= SET_SRC (set
);
3881 delete_insns_since (PREV_INSN (last_insn
));
3886 *ad
.inner
= new_reg
;
3888 else if (ad
.disp_term
!= NULL
)
3890 /* base + scale * index + disp => new base + scale * index,
3892 gcc_assert (ad
.disp
== ad
.disp_term
);
3893 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3894 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3895 new_reg
, *ad
.index
);
3897 else if ((scale
= get_index_scale (&ad
)) == 1)
3899 /* The last transformation to one reg will be made in
3900 curr_insn_transform function. */
3904 else if (scale
!= 0)
3906 /* base + scale * index => base + new_reg,
3908 Index part of address may become invalid. For example, we
3909 changed pseudo on the equivalent memory and a subreg of the
3910 pseudo onto the memory of different mode for which the scale is
3912 new_reg
= index_part_to_reg (&ad
, index_cl
);
3913 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3914 *ad
.base_term
, new_reg
);
3918 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3921 rtx addr
= *ad
.inner
;
3923 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "addr");
3924 /* addr => new_base. */
3925 lra_emit_move (new_reg
, addr
);
3926 *ad
.inner
= new_reg
;
3928 *before
= get_insns ();
3933 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3934 Use process_address_1 as a helper function. Return true for any
3937 If CHECK_ONLY_P is true, just check address correctness. Return
3938 false if the address correct. */
3940 process_address (int nop
, bool check_only_p
,
3941 rtx_insn
**before
, rtx_insn
**after
)
3945 while (process_address_1 (nop
, check_only_p
, before
, after
))
3954 /* Override the generic address_reload_context in order to
3955 control the creation of reload pseudos. */
3956 class lra_autoinc_reload_context
: public address_reload_context
3959 enum reg_class rclass
;
3962 lra_autoinc_reload_context (machine_mode mode
, enum reg_class new_rclass
)
3963 : mode (mode
), rclass (new_rclass
) {}
3965 rtx
get_reload_reg () const override final
3967 return lra_create_new_reg (mode
, NULL_RTX
, rclass
, NULL
, "INC/DEC result");
3971 /* Emit insns to reload VALUE into a new register. VALUE is an
3972 auto-increment or auto-decrement RTX whose operand is a register or
3973 memory location; so reloading involves incrementing that location.
3975 INC_AMOUNT is the number to increment or decrement by (always
3976 positive and ignored for POST_MODIFY/PRE_MODIFY).
3978 Return a pseudo containing the result. */
3980 emit_inc (enum reg_class new_rclass
, rtx value
, poly_int64 inc_amount
)
3982 lra_autoinc_reload_context
context (GET_MODE (value
), new_rclass
);
3983 return context
.emit_autoinc (value
, inc_amount
);
3986 /* Return true if the current move insn does not need processing as we
3987 already know that it satisfies its constraints. */
3989 simple_move_p (void)
3992 enum reg_class dclass
, sclass
;
3994 lra_assert (curr_insn_set
!= NULL_RTX
);
3995 dest
= SET_DEST (curr_insn_set
);
3996 src
= SET_SRC (curr_insn_set
);
3998 /* If the instruction has multiple sets we need to process it even if it
3999 is single_set. This can happen if one or more of the SETs are dead.
4001 if (multiple_sets (curr_insn
))
4004 return ((dclass
= get_op_class (dest
)) != NO_REGS
4005 && (sclass
= get_op_class (src
)) != NO_REGS
4006 /* The backend guarantees that register moves of cost 2
4007 never need reloads. */
4008 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
4011 /* Swap operands NOP and NOP + 1. */
4013 swap_operands (int nop
)
4015 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
4016 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
4017 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
4018 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
4019 /* Swap the duplicates too. */
4020 lra_update_dup (curr_id
, nop
);
4021 lra_update_dup (curr_id
, nop
+ 1);
4024 /* Main entry point of the constraint code: search the body of the
4025 current insn to choose the best alternative. It is mimicking insn
4026 alternative cost calculation model of former reload pass. That is
4027 because machine descriptions were written to use this model. This
4028 model can be changed in future. Make commutative operand exchange
4031 if CHECK_ONLY_P is false, do RTL changes to satisfy the
4032 constraints. Return true if any change happened during function
4035 If CHECK_ONLY_P is true then don't do any transformation. Just
4036 check that the insn satisfies all constraints. If the insn does
4037 not satisfy any constraint, return true. */
4039 curr_insn_transform (bool check_only_p
)
4046 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
4047 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
4048 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
4049 rtx_insn
*before
, *after
;
4051 /* Flag that the insn has been changed through a transformation. */
4055 int max_regno_before
;
4056 int reused_alternative_num
;
4058 curr_insn_set
= single_set (curr_insn
);
4059 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
4061 /* We assume that the corresponding insn alternative has no
4062 earlier clobbers. If it is not the case, don't define move
4063 cost equal to 2 for the corresponding register classes. */
4064 lra_set_used_insn_alternative (curr_insn
, LRA_NON_CLOBBERED_ALT
);
4068 no_input_reloads_p
= no_output_reloads_p
= false;
4069 goal_alt_number
= -1;
4070 change_p
= sec_mem_p
= false;
4072 /* CALL_INSNs are not allowed to have any output reloads. */
4073 if (CALL_P (curr_insn
))
4074 no_output_reloads_p
= true;
4076 n_operands
= curr_static_id
->n_operands
;
4077 n_alternatives
= curr_static_id
->n_alternatives
;
4079 /* Just return "no reloads" if insn has no operands with
4081 if (n_operands
== 0 || n_alternatives
== 0)
4084 max_regno_before
= max_reg_num ();
4086 for (i
= 0; i
< n_operands
; i
++)
4088 goal_alt_matched
[i
][0] = -1;
4089 goal_alt_matches
[i
] = -1;
4092 commutative
= curr_static_id
->commutative
;
4094 /* Now see what we need for pseudos that didn't get hard regs or got
4095 the wrong kind of hard reg. For this, we must consider all the
4096 operands together against the register constraints. */
4098 best_losers
= best_overall
= INT_MAX
;
4099 best_reload_sum
= 0;
4101 curr_swapped
= false;
4102 goal_alt_swapped
= false;
4105 /* Make equivalence substitution and memory subreg elimination
4106 before address processing because an address legitimacy can
4107 depend on memory mode. */
4108 for (i
= 0; i
< n_operands
; i
++)
4111 bool op_change_p
= false;
4113 if (curr_static_id
->operand
[i
].is_operator
)
4116 old
= op
= *curr_id
->operand_loc
[i
];
4117 if (GET_CODE (old
) == SUBREG
)
4118 old
= SUBREG_REG (old
);
4119 subst
= get_equiv_with_elimination (old
, curr_insn
);
4120 original_subreg_reg_mode
[i
] = VOIDmode
;
4121 equiv_substition_p
[i
] = false;
4124 equiv_substition_p
[i
] = true;
4125 subst
= copy_rtx (subst
);
4126 lra_assert (REG_P (old
));
4127 if (GET_CODE (op
) != SUBREG
)
4128 *curr_id
->operand_loc
[i
] = subst
;
4131 SUBREG_REG (op
) = subst
;
4132 if (GET_MODE (subst
) == VOIDmode
)
4133 original_subreg_reg_mode
[i
] = GET_MODE (old
);
4135 if (lra_dump_file
!= NULL
)
4137 fprintf (lra_dump_file
,
4138 "Changing pseudo %d in operand %i of insn %u on equiv ",
4139 REGNO (old
), i
, INSN_UID (curr_insn
));
4140 dump_value_slim (lra_dump_file
, subst
, 1);
4141 fprintf (lra_dump_file
, "\n");
4143 op_change_p
= change_p
= true;
4145 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
4148 lra_update_dup (curr_id
, i
);
4152 /* Reload address registers and displacements. We do it before
4153 finding an alternative because of memory constraints. */
4154 before
= after
= NULL
;
4155 for (i
= 0; i
< n_operands
; i
++)
4156 if (! curr_static_id
->operand
[i
].is_operator
4157 && process_address (i
, check_only_p
, &before
, &after
))
4162 lra_update_dup (curr_id
, i
);
4166 /* If we've changed the instruction then any alternative that
4167 we chose previously may no longer be valid. */
4168 lra_set_used_insn_alternative (curr_insn
, LRA_UNKNOWN_ALT
);
4170 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
4171 && check_and_process_move (&change_p
, &sec_mem_p
))
4176 reused_alternative_num
= check_only_p
? LRA_UNKNOWN_ALT
: curr_id
->used_insn_alternative
;
4177 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
4178 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
4179 reused_alternative_num
, INSN_UID (curr_insn
));
4181 if (process_alt_operands (reused_alternative_num
))
4185 return ! alt_p
|| best_losers
!= 0;
4187 /* If insn is commutative (it's safe to exchange a certain pair of
4188 operands) then we need to try each alternative twice, the second
4189 time matching those two operands as if we had exchanged them. To
4190 do this, really exchange them in operands.
4192 If we have just tried the alternatives the second time, return
4193 operands to normal and drop through. */
4195 if (reused_alternative_num
< 0 && commutative
>= 0)
4197 curr_swapped
= !curr_swapped
;
4200 swap_operands (commutative
);
4204 swap_operands (commutative
);
4207 if (! alt_p
&& ! sec_mem_p
)
4209 /* No alternative works with reloads?? */
4210 if (INSN_CODE (curr_insn
) >= 0)
4211 fatal_insn ("unable to generate reloads for:", curr_insn
);
4212 error_for_asm (curr_insn
,
4213 "inconsistent operand constraints in an %<asm%>");
4214 lra_asm_error_p
= true;
4215 if (! JUMP_P (curr_insn
))
4217 /* Avoid further trouble with this insn. Don't generate use
4218 pattern here as we could use the insn SP offset. */
4219 lra_set_insn_deleted (curr_insn
);
4223 lra_invalidate_insn_data (curr_insn
);
4224 ira_nullify_asm_goto (curr_insn
);
4225 lra_update_insn_regno_info (curr_insn
);
4230 /* If the best alternative is with operands 1 and 2 swapped, swap
4231 them. Update the operand numbers of any reloads already
4234 if (goal_alt_swapped
)
4236 if (lra_dump_file
!= NULL
)
4237 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
4238 INSN_UID (curr_insn
));
4240 /* Swap the duplicates too. */
4241 swap_operands (commutative
);
4245 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4246 too conservatively. So we use the secondary memory only if there
4247 is no any alternative without reloads. */
4248 use_sec_mem_p
= false;
4250 use_sec_mem_p
= true;
4253 for (i
= 0; i
< n_operands
; i
++)
4254 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
4256 use_sec_mem_p
= i
< n_operands
;
4261 int in
= -1, out
= -1;
4262 rtx new_reg
, src
, dest
, rld
;
4263 machine_mode sec_mode
, rld_mode
;
4265 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
4266 dest
= SET_DEST (curr_insn_set
);
4267 src
= SET_SRC (curr_insn_set
);
4268 for (i
= 0; i
< n_operands
; i
++)
4269 if (*curr_id
->operand_loc
[i
] == dest
)
4271 else if (*curr_id
->operand_loc
[i
] == src
)
4273 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
4274 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
4275 out
= curr_static_id
->dup_num
[i
];
4276 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
4277 in
= curr_static_id
->dup_num
[i
];
4278 lra_assert (out
>= 0 && in
>= 0
4279 && curr_static_id
->operand
[out
].type
== OP_OUT
4280 && curr_static_id
->operand
[in
].type
== OP_IN
);
4281 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
4282 rld_mode
= GET_MODE (rld
);
4283 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
4284 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
, NO_REGS
, NULL
,
4286 /* If the mode is changed, it should be wider. */
4287 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
4288 if (sec_mode
!= rld_mode
)
4290 /* If the target says specifically to use another mode for
4291 secondary memory moves we cannot reuse the original
4293 after
= emit_spill_move (false, new_reg
, dest
);
4294 lra_process_new_insns (curr_insn
, NULL
, after
,
4295 "Inserting the sec. move");
4296 /* We may have non null BEFORE here (e.g. after address
4298 push_to_sequence (before
);
4299 before
= emit_spill_move (true, new_reg
, src
);
4301 before
= get_insns ();
4303 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
4304 lra_set_insn_deleted (curr_insn
);
4306 else if (dest
== rld
)
4308 *curr_id
->operand_loc
[out
] = new_reg
;
4309 lra_update_dup (curr_id
, out
);
4310 after
= emit_spill_move (false, new_reg
, dest
);
4311 lra_process_new_insns (curr_insn
, NULL
, after
,
4312 "Inserting the sec. move");
4316 *curr_id
->operand_loc
[in
] = new_reg
;
4317 lra_update_dup (curr_id
, in
);
4318 /* See comments above. */
4319 push_to_sequence (before
);
4320 before
= emit_spill_move (true, new_reg
, src
);
4322 before
= get_insns ();
4324 lra_process_new_insns (curr_insn
, before
, NULL
,
4325 "Inserting the sec. move");
4327 lra_update_insn_regno_info (curr_insn
);
4331 lra_assert (goal_alt_number
>= 0);
4332 lra_set_used_insn_alternative (curr_insn
, goal_reuse_alt_p
4333 ? goal_alt_number
: LRA_UNKNOWN_ALT
);
4335 if (lra_dump_file
!= NULL
)
4339 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4340 goal_alt_number
, INSN_UID (curr_insn
));
4341 print_curr_insn_alt (goal_alt_number
);
4342 if (INSN_CODE (curr_insn
) >= 0
4343 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4344 fprintf (lra_dump_file
, " {%s}", p
);
4345 if (maybe_ne (curr_id
->sp_offset
, 0))
4347 fprintf (lra_dump_file
, " (sp_off=");
4348 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4349 fprintf (lra_dump_file
, ")");
4351 fprintf (lra_dump_file
, "\n");
4354 /* Right now, for any pair of operands I and J that are required to
4355 match, with J < I, goal_alt_matches[I] is J. Add I to
4356 goal_alt_matched[J]. */
4358 for (i
= 0; i
< n_operands
; i
++)
4359 if ((j
= goal_alt_matches
[i
]) >= 0)
4361 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4363 /* We allow matching one output operand and several input
4366 || (curr_static_id
->operand
[j
].type
== OP_OUT
4367 && curr_static_id
->operand
[i
].type
== OP_IN
4368 && (curr_static_id
->operand
4369 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4370 goal_alt_matched
[j
][k
] = i
;
4371 goal_alt_matched
[j
][k
+ 1] = -1;
4374 for (i
= 0; i
< n_operands
; i
++)
4375 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4377 /* Any constants that aren't allowed and can't be reloaded into
4378 registers are here changed into memory references. */
4379 for (i
= 0; i
< n_operands
; i
++)
4380 if (goal_alt_win
[i
])
4383 enum reg_class new_class
;
4384 rtx reg
= *curr_id
->operand_loc
[i
];
4386 if (GET_CODE (reg
) == SUBREG
)
4387 reg
= SUBREG_REG (reg
);
4389 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4391 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4393 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4396 lra_change_class (regno
, new_class
, " Change to", true);
4402 const char *constraint
;
4404 rtx op
= *curr_id
->operand_loc
[i
];
4405 rtx subreg
= NULL_RTX
;
4406 machine_mode mode
= curr_operand_mode
[i
];
4408 if (GET_CODE (op
) == SUBREG
)
4411 op
= SUBREG_REG (op
);
4412 mode
= GET_MODE (op
);
4415 if (CONST_POOL_OK_P (mode
, op
)
4416 && ((targetm
.preferred_reload_class
4417 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4418 || no_input_reloads_p
))
4420 rtx tem
= force_const_mem (mode
, op
);
4423 if (subreg
!= NULL_RTX
)
4424 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4426 *curr_id
->operand_loc
[i
] = tem
;
4427 lra_update_dup (curr_id
, i
);
4428 process_address (i
, false, &before
, &after
);
4430 /* If the alternative accepts constant pool refs directly
4431 there will be no reload needed at all. */
4432 if (subreg
!= NULL_RTX
)
4434 /* Skip alternatives before the one requested. */
4435 constraint
= (curr_static_id
->operand_alternative
4436 [goal_alt_number
* n_operands
+ i
].constraint
);
4438 (c
= *constraint
) && c
!= ',' && c
!= '#';
4439 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4441 enum constraint_num cn
= lookup_constraint (constraint
);
4442 if ((insn_extra_memory_constraint (cn
)
4443 || insn_extra_special_memory_constraint (cn
)
4444 || insn_extra_relaxed_memory_constraint (cn
))
4445 && satisfies_memory_constraint_p (tem
, cn
))
4448 if (c
== '\0' || c
== ',' || c
== '#')
4451 goal_alt_win
[i
] = true;
4456 for (i
= 0; i
< n_operands
; i
++)
4457 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4458 outputs
[n_outputs
++] = i
;
4459 outputs
[n_outputs
] = -1;
4460 for (i
= 0; i
< n_operands
; i
++)
4463 bool optional_p
= false;
4465 rtx op
= *curr_id
->operand_loc
[i
];
4467 if (goal_alt_win
[i
])
4469 if (goal_alt
[i
] == NO_REGS
4471 /* When we assign NO_REGS it means that we will not
4472 assign a hard register to the scratch pseudo by
4473 assigment pass and the scratch pseudo will be
4474 spilled. Spilled scratch pseudos are transformed
4475 back to scratches at the LRA end. */
4476 && ira_former_scratch_operand_p (curr_insn
, i
)
4477 && ira_former_scratch_p (REGNO (op
)))
4479 int regno
= REGNO (op
);
4480 lra_change_class (regno
, NO_REGS
, " Change to", true);
4481 if (lra_get_regno_hard_regno (regno
) >= 0)
4482 /* We don't have to mark all insn affected by the
4483 spilled pseudo as there is only one such insn, the
4485 reg_renumber
[regno
] = -1;
4486 lra_assert (bitmap_single_bit_set_p
4487 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4489 /* We can do an optional reload. If the pseudo got a hard
4490 reg, we might improve the code through inheritance. If
4491 it does not get a hard register we coalesce memory/memory
4492 moves later. Ignore move insns to avoid cycling. */
4494 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4495 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4496 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4497 && regno
< new_regno_start
4498 && ! ira_former_scratch_p (regno
)
4499 && reg_renumber
[regno
] < 0
4500 /* Check that the optional reload pseudo will be able to
4501 hold given mode value. */
4502 && ! (prohibited_class_reg_set_mode_p
4503 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4504 PSEUDO_REGNO_MODE (regno
)))
4505 && (curr_insn_set
== NULL_RTX
4506 || !((REG_P (SET_SRC (curr_insn_set
))
4507 || MEM_P (SET_SRC (curr_insn_set
))
4508 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4509 && (REG_P (SET_DEST (curr_insn_set
))
4510 || MEM_P (SET_DEST (curr_insn_set
))
4511 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4513 else if (goal_alt_matched
[i
][0] != -1
4514 && curr_static_id
->operand
[i
].type
== OP_OUT
4515 && (curr_static_id
->operand_alternative
4516 [goal_alt_number
* n_operands
+ i
].earlyclobber
)
4519 for (j
= 0; goal_alt_matched
[i
][j
] != -1; j
++)
4521 rtx op2
= *curr_id
->operand_loc
[goal_alt_matched
[i
][j
]];
4523 if (REG_P (op2
) && REGNO (op
) != REGNO (op2
))
4526 if (goal_alt_matched
[i
][j
] != -1)
4528 /* Generate reloads for different output and matched
4529 input registers. This is the easiest way to avoid
4530 creation of non-existing register conflicts in
4532 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
],
4533 &goal_alt_exclude_start_hard_regs
[i
], &before
,
4540 enum reg_class rclass
, common_class
;
4542 if (REG_P (op
) && goal_alt
[i
] != NO_REGS
4543 && (regno
= REGNO (op
)) >= new_regno_start
4544 && (rclass
= get_reg_class (regno
)) == ALL_REGS
4545 && ((common_class
= ira_reg_class_subset
[rclass
][goal_alt
[i
]])
4547 && common_class
!= ALL_REGS
4548 && enough_allocatable_hard_regs_p (common_class
,
4550 /* Refine reload pseudo class from chosen alternative
4552 lra_change_class (regno
, common_class
, " Change to", true);
4557 /* Operands that match previous ones have already been handled. */
4558 if (goal_alt_matches
[i
] >= 0)
4561 /* We should not have an operand with a non-offsettable address
4562 appearing where an offsettable address will do. It also may
4563 be a case when the address should be special in other words
4564 not a general one (e.g. it needs no index reg). */
4565 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4567 enum reg_class rclass
;
4568 rtx
*loc
= &XEXP (op
, 0);
4569 enum rtx_code code
= GET_CODE (*loc
);
4571 push_to_sequence (before
);
4572 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4573 MEM
, SCRATCH
, curr_insn
);
4574 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4575 new_reg
= emit_inc (rclass
, *loc
,
4576 /* This value does not matter for MODIFY. */
4577 GET_MODE_SIZE (GET_MODE (op
)));
4578 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
4580 "offsetable address", &new_reg
))
4583 enum rtx_code code
= GET_CODE (addr
);
4584 bool align_p
= false;
4586 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4588 /* (and ... (const_int -X)) is used to align to X bytes. */
4590 addr
= XEXP (*loc
, 0);
4593 addr
= canonicalize_reload_addr (addr
);
4595 lra_emit_move (new_reg
, addr
);
4597 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4599 before
= get_insns ();
4602 lra_update_dup (curr_id
, i
);
4604 else if (goal_alt_matched
[i
][0] == -1)
4609 enum op_type type
= curr_static_id
->operand
[i
].type
;
4611 loc
= curr_id
->operand_loc
[i
];
4612 mode
= curr_operand_mode
[i
];
4613 if (GET_CODE (*loc
) == SUBREG
)
4615 reg
= SUBREG_REG (*loc
);
4616 poly_int64 byte
= SUBREG_BYTE (*loc
);
4618 /* Strict_low_part requires reloading the register and not
4619 just the subreg. Likewise for a strict subreg no wider
4620 than a word for WORD_REGISTER_OPERATIONS targets. */
4621 && (curr_static_id
->operand
[i
].strict_low
4622 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4624 = get_try_hard_regno (REGNO (reg
))) >= 0
4625 && (simplify_subreg_regno
4627 GET_MODE (reg
), byte
, mode
) < 0)
4628 && (goal_alt
[i
] == NO_REGS
4629 || (simplify_subreg_regno
4630 (ira_class_hard_regs
[goal_alt
[i
]][0],
4631 GET_MODE (reg
), byte
, mode
) >= 0)))
4632 || (partial_subreg_p (mode
, GET_MODE (reg
))
4633 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4635 && WORD_REGISTER_OPERATIONS
))
4636 /* Avoid the situation when there are no available hard regs
4637 for the pseudo mode but there are ones for the subreg
4639 && !(goal_alt
[i
] != NO_REGS
4640 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
4641 && (prohibited_class_reg_set_mode_p
4642 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4644 && !(prohibited_class_reg_set_mode_p
4645 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4648 /* An OP_INOUT is required when reloading a subreg of a
4649 mode wider than a word to ensure that data beyond the
4650 word being reloaded is preserved. Also automatically
4651 ensure that strict_low_part reloads are made into
4652 OP_INOUT which should already be true from the backend
4655 && (curr_static_id
->operand
[i
].strict_low
4656 || read_modify_subreg_p (*loc
)))
4658 loc
= &SUBREG_REG (*loc
);
4659 mode
= GET_MODE (*loc
);
4663 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4664 &goal_alt_exclude_start_hard_regs
[i
],
4665 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4668 push_to_sequence (before
);
4669 lra_emit_move (new_reg
, old
);
4670 before
= get_insns ();
4675 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4678 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4680 after
= get_insns ();
4684 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4685 if (goal_alt_dont_inherit_ops
[j
] == i
)
4687 lra_set_regno_unique_value (REGNO (new_reg
));
4690 lra_update_dup (curr_id
, i
);
4692 else if (curr_static_id
->operand
[i
].type
== OP_IN
4693 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4695 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4697 && (operands_match_p
4698 (*curr_id
->operand_loc
[i
],
4699 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4702 /* generate reloads for input and matched outputs. */
4703 match_inputs
[0] = i
;
4704 match_inputs
[1] = -1;
4705 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4706 goal_alt
[i
], &goal_alt_exclude_start_hard_regs
[i
],
4708 curr_static_id
->operand_alternative
4709 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4712 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4713 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4714 && (operands_match_p
4715 (*curr_id
->operand_loc
[i
],
4716 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4718 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4720 /* Generate reloads for output and matched inputs. */
4721 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
],
4722 &goal_alt_exclude_start_hard_regs
[i
], &before
, &after
,
4723 curr_static_id
->operand_alternative
4724 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4725 else if (curr_static_id
->operand
[i
].type
== OP_IN
4726 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4729 /* Generate reloads for matched inputs. */
4730 match_inputs
[0] = i
;
4731 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4732 match_inputs
[j
+ 1] = k
;
4733 match_inputs
[j
+ 1] = -1;
4734 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
],
4735 &goal_alt_exclude_start_hard_regs
[i
],
4736 &before
, &after
, false);
4739 /* We must generate code in any case when function
4740 process_alt_operands decides that it is possible. */
4747 lra_assert (REG_P (reg
));
4748 regno
= REGNO (reg
);
4749 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4750 if (GET_CODE (op
) == SUBREG
)
4751 op
= SUBREG_REG (op
);
4752 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4753 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4754 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4755 if (lra_dump_file
!= NULL
)
4756 fprintf (lra_dump_file
,
4757 " Making reload reg %d for reg %d optional\n",
4761 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4762 || max_regno_before
!= max_reg_num ())
4766 lra_update_operator_dups (curr_id
);
4767 /* Something changes -- process the insn. */
4768 lra_update_insn_regno_info (curr_insn
);
4769 if (asm_noperands (PATTERN (curr_insn
)) >= 0
4770 && ++curr_id
->asm_reloads_num
>= FIRST_PSEUDO_REGISTER
)
4771 /* Most probably there are no enough registers to satisfy asm insn: */
4772 lra_asm_insn_error (curr_insn
);
4774 if (goal_alt_out_sp_reload_p
)
4776 /* We have an output stack pointer reload -- update sp offset: */
4778 bool done_p
= false;
4779 poly_int64 sp_offset
= curr_id
->sp_offset
;
4780 for (rtx_insn
*insn
= after
; insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
4781 if ((set
= single_set (insn
)) != NULL_RTX
4782 && SET_DEST (set
) == stack_pointer_rtx
)
4784 lra_assert (!done_p
);
4786 curr_id
->sp_offset
= 0;
4787 lra_insn_recog_data_t id
= lra_get_insn_recog_data (insn
);
4788 id
->sp_offset
= sp_offset
;
4789 if (lra_dump_file
!= NULL
)
4790 fprintf (lra_dump_file
,
4791 " Moving sp offset from insn %u to %u\n",
4792 INSN_UID (curr_insn
), INSN_UID (insn
));
4794 lra_assert (done_p
);
4796 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4800 /* Return true if INSN satisfies all constraints. In other words, no
4801 reload insns are needed. */
4803 lra_constrain_insn (rtx_insn
*insn
)
4805 int saved_new_regno_start
= new_regno_start
;
4806 int saved_new_insn_uid_start
= new_insn_uid_start
;
4810 curr_id
= lra_get_insn_recog_data (curr_insn
);
4811 curr_static_id
= curr_id
->insn_static_data
;
4812 new_insn_uid_start
= get_max_uid ();
4813 new_regno_start
= max_reg_num ();
4814 change_p
= curr_insn_transform (true);
4815 new_regno_start
= saved_new_regno_start
;
4816 new_insn_uid_start
= saved_new_insn_uid_start
;
4820 /* Return true if X is in LIST. */
4822 in_list_p (rtx x
, rtx list
)
4824 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4825 if (XEXP (list
, 0) == x
)
4830 /* Return true if X contains an allocatable hard register (if
4831 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4833 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4839 code
= GET_CODE (x
);
4842 int regno
= REGNO (x
);
4843 HARD_REG_SET alloc_regs
;
4847 if (regno
>= FIRST_PSEUDO_REGISTER
)
4848 regno
= lra_get_regno_hard_regno (regno
);
4851 alloc_regs
= ~lra_no_alloc_regs
;
4852 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4856 if (regno
< FIRST_PSEUDO_REGISTER
)
4860 return lra_get_regno_hard_regno (regno
) < 0;
4863 fmt
= GET_RTX_FORMAT (code
);
4864 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4868 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4871 else if (fmt
[i
] == 'E')
4873 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4874 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4881 /* Process all regs in location *LOC and change them on equivalent
4882 substitution. Return true if any change was done. */
4884 loc_equivalence_change_p (rtx
*loc
)
4886 rtx subst
, reg
, x
= *loc
;
4887 bool result
= false;
4888 enum rtx_code code
= GET_CODE (x
);
4894 reg
= SUBREG_REG (x
);
4895 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4896 && GET_MODE (subst
) == VOIDmode
)
4898 /* We cannot reload debug location. Simplify subreg here
4899 while we know the inner mode. */
4900 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4901 GET_MODE (reg
), SUBREG_BYTE (x
));
4905 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4911 /* Scan all the operand sub-expressions. */
4912 fmt
= GET_RTX_FORMAT (code
);
4913 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4916 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4917 else if (fmt
[i
] == 'E')
4918 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4920 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4925 /* Similar to loc_equivalence_change_p, but for use as
4926 simplify_replace_fn_rtx callback. DATA is insn for which the
4927 elimination is done. If it null we don't do the elimination. */
4929 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4934 rtx subst
= (data
== NULL
4935 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4942 /* Maximum number of generated reload insns per an insn. It is for
4943 preventing this pass cycling in a bug case. */
4944 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4946 /* The current iteration number of this LRA pass. */
4947 int lra_constraint_iter
;
4949 /* True if we should during assignment sub-pass check assignment
4950 correctness for all pseudos and spill some of them to correct
4951 conflicts. It can be necessary when we substitute equiv which
4952 needs checking register allocation correctness because the
4953 equivalent value contains allocatable hard registers, or when we
4954 restore multi-register pseudo, or when we change the insn code and
4955 its operand became INOUT operand when it was IN one before. */
4956 bool check_and_force_assignment_correctness_p
;
4958 /* Return true if REGNO is referenced in more than one block. */
4960 multi_block_pseudo_p (int regno
)
4962 basic_block bb
= NULL
;
4966 if (regno
< FIRST_PSEUDO_REGISTER
)
4969 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4971 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4972 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4977 /* Return true if LIST contains a deleted insn. */
4979 contains_deleted_insn_p (rtx_insn_list
*list
)
4981 for (; list
!= NULL_RTX
; list
= list
->next ())
4982 if (NOTE_P (list
->insn ())
4983 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4988 /* Return true if X contains a pseudo dying in INSN. */
4990 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4997 return (insn
!= NULL_RTX
4998 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4999 code
= GET_CODE (x
);
5000 fmt
= GET_RTX_FORMAT (code
);
5001 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5005 if (dead_pseudo_p (XEXP (x
, i
), insn
))
5008 else if (fmt
[i
] == 'E')
5010 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5011 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
5018 /* Return true if INSN contains a dying pseudo in INSN right hand
5021 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
5023 rtx set
= single_set (insn
);
5025 gcc_assert (set
!= NULL
);
5026 return dead_pseudo_p (SET_SRC (set
), insn
);
5029 /* Return true if any init insn of REGNO contains a dying pseudo in
5030 insn right hand side. */
5032 init_insn_rhs_dead_pseudo_p (int regno
)
5034 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
5038 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
5039 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
5044 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
5045 reverse only if we have one init insn with given REGNO as a
5048 reverse_equiv_p (int regno
)
5050 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
5055 if (! INSN_P (insns
->insn ())
5056 || insns
->next () != NULL
)
5058 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
5060 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
5063 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
5064 call this function only for non-reverse equivalence. */
5066 contains_reloaded_insn_p (int regno
)
5069 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
5071 for (; list
!= NULL
; list
= list
->next ())
5072 if ((set
= single_set (list
->insn ())) == NULL_RTX
5073 || ! REG_P (SET_DEST (set
))
5074 || (int) REGNO (SET_DEST (set
)) != regno
)
5079 /* Try combine secondary memory reload insn FROM for insn TO into TO insn.
5080 FROM should be a load insn (usually a secondary memory reload insn). Return
5081 TRUE in case of success. */
5083 combine_reload_insn (rtx_insn
*from
, rtx_insn
*to
)
5086 rtx_insn
*saved_insn
;
5087 rtx set
, from_reg
, to_reg
, op
;
5088 enum reg_class to_class
, from_class
;
5090 signed char changed_nops
[MAX_RECOG_OPERANDS
+ 1];
5092 /* Check conditions for second memory reload and original insn: */
5093 if ((targetm
.secondary_memory_needed
5094 == hook_bool_mode_reg_class_t_reg_class_t_false
)
5095 || NEXT_INSN (from
) != to
5096 || !NONDEBUG_INSN_P (to
)
5100 lra_insn_recog_data_t id
= lra_get_insn_recog_data (to
);
5101 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
5103 if (id
->used_insn_alternative
== LRA_UNKNOWN_ALT
5104 || (set
= single_set (from
)) == NULL_RTX
)
5106 from_reg
= SET_DEST (set
);
5107 to_reg
= SET_SRC (set
);
5108 /* Ignore optional reloads: */
5109 if (! REG_P (from_reg
) || ! REG_P (to_reg
)
5110 || bitmap_bit_p (&lra_optional_reload_pseudos
, REGNO (from_reg
)))
5112 to_class
= lra_get_allocno_class (REGNO (to_reg
));
5113 from_class
= lra_get_allocno_class (REGNO (from_reg
));
5114 /* Check that reload insn is a load: */
5115 if (to_class
!= NO_REGS
|| from_class
== NO_REGS
)
5117 for (n
= nop
= 0; nop
< static_id
->n_operands
; nop
++)
5119 if (static_id
->operand
[nop
].type
!= OP_IN
)
5121 op
= *id
->operand_loc
[nop
];
5122 if (!REG_P (op
) || REGNO (op
) != REGNO (from_reg
))
5124 *id
->operand_loc
[nop
] = to_reg
;
5125 changed_nops
[n
++] = nop
;
5127 changed_nops
[n
] = -1;
5128 lra_update_dups (id
, changed_nops
);
5129 lra_update_insn_regno_info (to
);
5130 ok_p
= recog_memoized (to
) >= 0;
5133 /* Check that combined insn does not need any reloads: */
5134 saved_insn
= curr_insn
;
5136 curr_id
= lra_get_insn_recog_data (curr_insn
);
5137 curr_static_id
= curr_id
->insn_static_data
;
5138 for (bool swapped_p
= false;;)
5140 ok_p
= !curr_insn_transform (true);
5141 if (ok_p
|| curr_static_id
->commutative
< 0)
5143 swap_operands (curr_static_id
->commutative
);
5144 if (lra_dump_file
!= NULL
)
5146 fprintf (lra_dump_file
,
5147 " Swapping %scombined insn operands:\n",
5148 swapped_p
? "back " : "");
5149 dump_insn_slim (lra_dump_file
, to
);
5155 curr_insn
= saved_insn
;
5156 curr_id
= lra_get_insn_recog_data (curr_insn
);
5157 curr_static_id
= curr_id
->insn_static_data
;
5161 id
->used_insn_alternative
= -1;
5162 lra_push_insn_and_update_insn_regno_info (to
);
5163 if (lra_dump_file
!= NULL
)
5165 fprintf (lra_dump_file
, " Use combined insn:\n");
5166 dump_insn_slim (lra_dump_file
, to
);
5170 if (lra_dump_file
!= NULL
)
5172 fprintf (lra_dump_file
, " Failed combined insn:\n");
5173 dump_insn_slim (lra_dump_file
, to
);
5175 for (int i
= 0; i
< n
; i
++)
5177 nop
= changed_nops
[i
];
5178 *id
->operand_loc
[nop
] = from_reg
;
5180 lra_update_dups (id
, changed_nops
);
5181 lra_update_insn_regno_info (to
);
5182 if (lra_dump_file
!= NULL
)
5184 fprintf (lra_dump_file
, " Restoring insn after failed combining:\n");
5185 dump_insn_slim (lra_dump_file
, to
);
5190 /* Entry function of LRA constraint pass. Return true if the
5191 constraint pass did change the code. */
5193 lra_constraints (bool first_p
)
5196 int i
, hard_regno
, new_insns_num
;
5197 unsigned int min_len
, new_min_len
, uid
;
5198 rtx set
, x
, reg
, dest_reg
;
5199 rtx_insn
*original_insn
;
5200 basic_block last_bb
;
5203 lra_constraint_iter
++;
5204 if (lra_dump_file
!= NULL
)
5205 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
5206 lra_constraint_iter
);
5208 if (pic_offset_table_rtx
5209 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
5210 check_and_force_assignment_correctness_p
= true;
5212 /* On the first iteration we should check IRA assignment
5213 correctness. In rare cases, the assignments can be wrong as
5214 early clobbers operands are ignored in IRA or usages of
5215 paradoxical sub-registers are not taken into account by
5217 check_and_force_assignment_correctness_p
= true;
5218 new_insn_uid_start
= get_max_uid ();
5219 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
5220 /* Mark used hard regs for target stack size calulations. */
5221 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5222 if (lra_reg_info
[i
].nrefs
!= 0
5223 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5227 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
5228 for (j
= 0; j
< nregs
; j
++)
5229 df_set_regs_ever_live (hard_regno
+ j
, true);
5231 /* Do elimination before the equivalence processing as we can spill
5232 some pseudos during elimination. */
5233 lra_eliminate (false, first_p
);
5234 auto_bitmap
equiv_insn_bitmap (®_obstack
);
5235 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5236 if (lra_reg_info
[i
].nrefs
!= 0)
5238 ira_reg_equiv
[i
].profitable_p
= true;
5239 reg
= regno_reg_rtx
[i
];
5240 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
5242 bool pseudo_p
= contains_reg_p (x
, false, false);
5244 /* After RTL transformation, we cannot guarantee that
5245 pseudo in the substitution was not reloaded which might
5246 make equivalence invalid. For example, in reverse
5253 the memory address register was reloaded before the 2nd
5255 if ((! first_p
&& pseudo_p
)
5256 /* We don't use DF for compilation speed sake. So it
5257 is problematic to update live info when we use an
5258 equivalence containing pseudos in more than one
5260 || (pseudo_p
&& multi_block_pseudo_p (i
))
5261 /* If an init insn was deleted for some reason, cancel
5262 the equiv. We could update the equiv insns after
5263 transformations including an equiv insn deletion
5264 but it is not worthy as such cases are extremely
5266 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
5267 /* If it is not a reverse equivalence, we check that a
5268 pseudo in rhs of the init insn is not dying in the
5269 insn. Otherwise, the live info at the beginning of
5270 the corresponding BB might be wrong after we
5271 removed the insn. When the equiv can be a
5272 constant, the right hand side of the init insn can
5274 || (! reverse_equiv_p (i
)
5275 && (init_insn_rhs_dead_pseudo_p (i
)
5276 /* If we reloaded the pseudo in an equivalence
5277 init insn, we cannot remove the equiv init
5278 insns and the init insns might write into
5279 const memory in this case. */
5280 || contains_reloaded_insn_p (i
)))
5281 /* Prevent access beyond equivalent memory for
5282 paradoxical subregs. */
5284 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
5285 GET_MODE_SIZE (GET_MODE (x
))))
5286 || (pic_offset_table_rtx
5287 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
5288 && (targetm
.preferred_reload_class
5289 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
5290 || contains_symbol_ref_p (x
))))
5291 ira_reg_equiv
[i
].defined_p
5292 = ira_reg_equiv
[i
].caller_save_p
= false;
5293 if (contains_reg_p (x
, false, true))
5294 ira_reg_equiv
[i
].profitable_p
= false;
5295 if (get_equiv (reg
) != reg
)
5296 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
5299 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5301 /* We should add all insns containing pseudos which should be
5302 substituted by their equivalences. */
5303 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
5304 lra_push_insn_by_uid (uid
);
5305 min_len
= lra_insn_stack_length ();
5309 original_insn
= NULL
;
5310 while ((new_min_len
= lra_insn_stack_length ()) != 0)
5312 curr_insn
= lra_pop_insn ();
5314 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5315 if (curr_bb
!= last_bb
)
5318 bb_reload_num
= lra_curr_reload_num
;
5320 if (min_len
> new_min_len
)
5322 min_len
= new_min_len
;
5324 original_insn
= curr_insn
;
5326 else if (combine_reload_insn (curr_insn
, original_insn
))
5330 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
5332 ("maximum number of generated reload insns per insn achieved (%d)",
5333 MAX_RELOAD_INSNS_NUMBER
);
5335 if (DEBUG_INSN_P (curr_insn
))
5337 /* We need to check equivalence in debug insn and change
5338 pseudo to the equivalent value if necessary. */
5339 curr_id
= lra_get_insn_recog_data (curr_insn
);
5340 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
5342 rtx old
= *curr_id
->operand_loc
[0];
5343 *curr_id
->operand_loc
[0]
5344 = simplify_replace_fn_rtx (old
, NULL_RTX
,
5345 loc_equivalence_callback
, curr_insn
);
5346 if (old
!= *curr_id
->operand_loc
[0])
5348 /* If we substitute pseudo by shared equivalence, we can fail
5349 to update LRA reg info and this can result in many
5350 unexpected consequences. So keep rtl unshared: */
5351 *curr_id
->operand_loc
[0]
5352 = copy_rtx (*curr_id
->operand_loc
[0]);
5353 lra_update_insn_regno_info (curr_insn
);
5358 else if (INSN_P (curr_insn
))
5360 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
5362 dest_reg
= SET_DEST (set
);
5363 /* The equivalence pseudo could be set up as SUBREG in a
5364 case when it is a call restore insn in a mode
5365 different from the pseudo mode. */
5366 if (GET_CODE (dest_reg
) == SUBREG
)
5367 dest_reg
= SUBREG_REG (dest_reg
);
5368 if ((REG_P (dest_reg
)
5369 && (x
= get_equiv (dest_reg
)) != dest_reg
5370 /* Remove insns which set up a pseudo whose value
5371 cannot be changed. Such insns might be not in
5372 init_insns because we don't update equiv data
5373 during insn transformations.
5375 As an example, let suppose that a pseudo got
5376 hard register and on the 1st pass was not
5377 changed to equivalent constant. We generate an
5378 additional insn setting up the pseudo because of
5379 secondary memory movement. Then the pseudo is
5380 spilled and we use the equiv constant. In this
5381 case we should remove the additional insn and
5382 this insn is not init_insns list. */
5383 && (! MEM_P (x
) || MEM_READONLY_P (x
)
5384 /* Check that this is actually an insn setting
5385 up the equivalence. */
5386 || in_list_p (curr_insn
,
5388 [REGNO (dest_reg
)].init_insns
)))
5389 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
5390 && in_list_p (curr_insn
,
5392 [REGNO (SET_SRC (set
))].init_insns
)))
5394 /* This is equiv init insn of pseudo which did not get a
5395 hard register -- remove the insn. */
5396 if (lra_dump_file
!= NULL
)
5398 fprintf (lra_dump_file
,
5399 " Removing equiv init insn %i (freq=%d)\n",
5400 INSN_UID (curr_insn
),
5401 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
5402 dump_insn_slim (lra_dump_file
, curr_insn
);
5404 if (contains_reg_p (x
, true, false))
5405 check_and_force_assignment_correctness_p
= true;
5406 lra_set_insn_deleted (curr_insn
);
5410 curr_id
= lra_get_insn_recog_data (curr_insn
);
5411 curr_static_id
= curr_id
->insn_static_data
;
5412 init_curr_insn_input_reloads ();
5413 init_curr_operand_mode ();
5414 if (curr_insn_transform (false))
5416 /* Check non-transformed insns too for equiv change as USE
5417 or CLOBBER don't need reloads but can contain pseudos
5418 being changed on their equivalences. */
5419 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
5420 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
5422 lra_update_insn_regno_info (curr_insn
);
5428 /* If we used a new hard regno, changed_p should be true because the
5429 hard reg is assigned to a new pseudo. */
5430 if (flag_checking
&& !changed_p
)
5432 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5433 if (lra_reg_info
[i
].nrefs
!= 0
5434 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5436 int j
, nregs
= hard_regno_nregs (hard_regno
,
5437 PSEUDO_REGNO_MODE (i
));
5439 for (j
= 0; j
< nregs
; j
++)
5440 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
5444 lra_dump_insns_if_possible ("changed func after local");
5448 static void initiate_invariants (void);
5449 static void finish_invariants (void);
5451 /* Initiate the LRA constraint pass. It is done once per
5454 lra_constraints_init (void)
5456 initiate_invariants ();
5459 /* Finalize the LRA constraint pass. It is done once per
5462 lra_constraints_finish (void)
5464 finish_invariants ();
5469 /* Structure describes invariants for ineheritance. */
5470 struct lra_invariant
5472 /* The order number of the invariant. */
5474 /* The invariant RTX. */
5476 /* The origin insn of the invariant. */
5480 typedef lra_invariant invariant_t
;
5481 typedef invariant_t
*invariant_ptr_t
;
5482 typedef const invariant_t
*const_invariant_ptr_t
;
5484 /* Pointer to the inheritance invariants. */
5485 static vec
<invariant_ptr_t
> invariants
;
5487 /* Allocation pool for the invariants. */
5488 static object_allocator
<lra_invariant
> *invariants_pool
;
5490 /* Hash table for the invariants. */
5491 static htab_t invariant_table
;
5493 /* Hash function for INVARIANT. */
5495 invariant_hash (const void *invariant
)
5497 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
5498 return lra_rtx_hash (inv
);
5501 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5503 invariant_eq_p (const void *invariant1
, const void *invariant2
)
5505 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
5506 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
5508 return rtx_equal_p (inv1
, inv2
);
5511 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5512 invariant which is in the table. */
5513 static invariant_ptr_t
5514 insert_invariant (rtx invariant_rtx
)
5517 invariant_t invariant
;
5518 invariant_ptr_t invariant_ptr
;
5520 invariant
.invariant_rtx
= invariant_rtx
;
5521 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
5522 if (*entry_ptr
== NULL
)
5524 invariant_ptr
= invariants_pool
->allocate ();
5525 invariant_ptr
->invariant_rtx
= invariant_rtx
;
5526 invariant_ptr
->insn
= NULL
;
5527 invariants
.safe_push (invariant_ptr
);
5528 *entry_ptr
= (void *) invariant_ptr
;
5530 return (invariant_ptr_t
) *entry_ptr
;
5533 /* Initiate the invariant table. */
5535 initiate_invariants (void)
5537 invariants
.create (100);
5539 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5540 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5543 /* Finish the invariant table. */
5545 finish_invariants (void)
5547 htab_delete (invariant_table
);
5548 delete invariants_pool
;
5549 invariants
.release ();
5552 /* Make the invariant table empty. */
5554 clear_invariants (void)
5556 htab_empty (invariant_table
);
5557 invariants_pool
->release ();
5558 invariants
.truncate (0);
5563 /* This page contains code to do inheritance/split
5566 /* Number of reloads passed so far in current EBB. */
5567 static int reloads_num
;
5569 /* Number of calls passed so far in current EBB. */
5570 static int calls_num
;
5572 /* Index ID is the CALLS_NUM associated the last call we saw with
5573 ABI identifier ID. */
5574 static int last_call_for_abi
[NUM_ABI_IDS
];
5576 /* Which registers have been fully or partially clobbered by a call
5577 since they were last used. */
5578 static HARD_REG_SET full_and_partial_call_clobbers
;
5580 /* Current reload pseudo check for validity of elements in
5582 static int curr_usage_insns_check
;
5584 /* Info about last usage of registers in EBB to do inheritance/split
5585 transformation. Inheritance transformation is done from a spilled
5586 pseudo and split transformations from a hard register or a pseudo
5587 assigned to a hard register. */
5590 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5591 value INSNS is valid. The insns is chain of optional debug insns
5592 and a finishing non-debug insn using the corresponding reg. The
5593 value is also used to mark the registers which are set up in the
5594 current insn. The negated insn uid is used for this. */
5596 /* Value of global reloads_num at the last insn in INSNS. */
5598 /* Value of global reloads_nums at the last insn in INSNS. */
5600 /* It can be true only for splitting. And it means that the restore
5601 insn should be put after insn given by the following member. */
5603 /* Next insns in the current EBB which use the original reg and the
5604 original reg value is not changed between the current insn and
5605 the next insns. In order words, e.g. for inheritance, if we need
5606 to use the original reg value again in the next insns we can try
5607 to use the value in a hard register from a reload insn of the
5612 /* Map: regno -> corresponding pseudo usage insns. */
5613 static struct usage_insns
*usage_insns
;
5616 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5618 usage_insns
[regno
].check
= curr_usage_insns_check
;
5619 usage_insns
[regno
].insns
= insn
;
5620 usage_insns
[regno
].reloads_num
= reloads_num
;
5621 usage_insns
[regno
].calls_num
= calls_num
;
5622 usage_insns
[regno
].after_p
= after_p
;
5623 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0)
5624 remove_from_hard_reg_set (&full_and_partial_call_clobbers
,
5625 PSEUDO_REGNO_MODE (regno
),
5626 reg_renumber
[regno
]);
5629 /* The function is used to form list REGNO usages which consists of
5630 optional debug insns finished by a non-debug insn using REGNO.
5631 RELOADS_NUM is current number of reload insns processed so far. */
5633 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5635 rtx next_usage_insns
;
5637 if (usage_insns
[regno
].check
== curr_usage_insns_check
5638 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5639 && DEBUG_INSN_P (insn
))
5641 /* Check that we did not add the debug insn yet. */
5642 if (next_usage_insns
!= insn
5643 && (GET_CODE (next_usage_insns
) != INSN_LIST
5644 || XEXP (next_usage_insns
, 0) != insn
))
5645 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5648 else if (NONDEBUG_INSN_P (insn
))
5649 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5651 usage_insns
[regno
].check
= 0;
5654 /* Return first non-debug insn in list USAGE_INSNS. */
5656 skip_usage_debug_insns (rtx usage_insns
)
5660 /* Skip debug insns. */
5661 for (insn
= usage_insns
;
5662 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5663 insn
= XEXP (insn
, 1))
5665 return safe_as_a
<rtx_insn
*> (insn
);
5668 /* Return true if we need secondary memory moves for insn in
5669 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5672 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5673 rtx usage_insns ATTRIBUTE_UNUSED
)
5679 if (inher_cl
== ALL_REGS
5680 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5682 lra_assert (INSN_P (insn
));
5683 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5685 dest
= SET_DEST (set
);
5688 lra_assert (inher_cl
!= NO_REGS
);
5689 cl
= get_reg_class (REGNO (dest
));
5690 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5691 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5694 /* Registers involved in inheritance/split in the current EBB
5695 (inheritance/split pseudos and original registers). */
5696 static bitmap_head check_only_regs
;
5698 /* Reload pseudos cannot be involded in invariant inheritance in the
5700 static bitmap_head invalid_invariant_regs
;
5702 /* Do inheritance transformations for insn INSN, which defines (if
5703 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5704 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5705 form as the "insns" field of usage_insns. Return true if we
5706 succeed in such transformation.
5708 The transformations look like:
5711 ... p <- i (new insn)
5713 <- ... p ... <- ... i ...
5715 ... i <- p (new insn)
5716 <- ... p ... <- ... i ...
5718 <- ... p ... <- ... i ...
5719 where p is a spilled original pseudo and i is a new inheritance pseudo.
5722 The inheritance pseudo has the smallest class of two classes CL and
5723 class of ORIGINAL REGNO. */
5725 inherit_reload_reg (bool def_p
, int original_regno
,
5726 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5728 if (optimize_function_for_size_p (cfun
))
5731 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5732 rtx original_reg
= regno_reg_rtx
[original_regno
];
5733 rtx new_reg
, usage_insn
;
5734 rtx_insn
*new_insns
;
5736 lra_assert (! usage_insns
[original_regno
].after_p
);
5737 if (lra_dump_file
!= NULL
)
5738 fprintf (lra_dump_file
,
5739 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5740 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5742 if (lra_dump_file
!= NULL
)
5744 fprintf (lra_dump_file
,
5745 " Rejecting inheritance for %d "
5746 "because of disjoint classes %s and %s\n",
5747 original_regno
, reg_class_names
[cl
],
5748 reg_class_names
[rclass
]);
5749 fprintf (lra_dump_file
,
5750 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5754 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5755 /* We don't use a subset of two classes because it can be
5756 NO_REGS. This transformation is still profitable in most
5757 cases even if the classes are not intersected as register
5758 move is probably cheaper than a memory load. */
5759 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5761 if (lra_dump_file
!= NULL
)
5762 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5763 reg_class_names
[cl
], reg_class_names
[rclass
]);
5767 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5769 /* Reject inheritance resulting in secondary memory moves.
5770 Otherwise, there is a danger in LRA cycling. Also such
5771 transformation will be unprofitable. */
5772 if (lra_dump_file
!= NULL
)
5774 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5775 rtx set
= single_set (insn
);
5777 lra_assert (set
!= NULL_RTX
);
5779 rtx dest
= SET_DEST (set
);
5781 lra_assert (REG_P (dest
));
5782 fprintf (lra_dump_file
,
5783 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5784 "as secondary mem is needed\n",
5785 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5786 original_regno
, reg_class_names
[rclass
]);
5787 fprintf (lra_dump_file
,
5788 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5792 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5793 rclass
, NULL
, "inheritance");
5796 lra_emit_move (original_reg
, new_reg
);
5798 lra_emit_move (new_reg
, original_reg
);
5799 new_insns
= get_insns ();
5801 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5803 if (lra_dump_file
!= NULL
)
5805 fprintf (lra_dump_file
,
5806 " Rejecting inheritance %d->%d "
5807 "as it results in 2 or more insns:\n",
5808 original_regno
, REGNO (new_reg
));
5809 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5810 fprintf (lra_dump_file
,
5811 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5815 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5816 lra_update_insn_regno_info (insn
);
5818 /* We now have a new usage insn for original regno. */
5819 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5820 if (lra_dump_file
!= NULL
)
5821 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5822 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5823 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5824 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5825 bitmap_set_bit (&check_only_regs
, original_regno
);
5826 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5828 lra_process_new_insns (insn
, NULL
, new_insns
,
5829 "Add original<-inheritance");
5831 lra_process_new_insns (insn
, new_insns
, NULL
,
5832 "Add inheritance<-original");
5833 while (next_usage_insns
!= NULL_RTX
)
5835 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5837 usage_insn
= next_usage_insns
;
5838 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5839 next_usage_insns
= NULL
;
5843 usage_insn
= XEXP (next_usage_insns
, 0);
5844 lra_assert (DEBUG_INSN_P (usage_insn
));
5845 next_usage_insns
= XEXP (next_usage_insns
, 1);
5847 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5848 DEBUG_INSN_P (usage_insn
));
5849 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5850 if (lra_dump_file
!= NULL
)
5852 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5853 fprintf (lra_dump_file
,
5854 " Inheritance reuse change %d->%d (bb%d):\n",
5855 original_regno
, REGNO (new_reg
),
5856 bb
? bb
->index
: -1);
5857 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5860 if (lra_dump_file
!= NULL
)
5861 fprintf (lra_dump_file
,
5862 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5866 /* Return true if we need a caller save/restore for pseudo REGNO which
5867 was assigned to a hard register. */
5869 need_for_call_save_p (int regno
)
5871 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5872 if (usage_insns
[regno
].calls_num
< calls_num
)
5874 unsigned int abis
= 0;
5875 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
5876 if (last_call_for_abi
[i
] > usage_insns
[regno
].calls_num
)
5879 if (call_clobbered_in_region_p (abis
, full_and_partial_call_clobbers
,
5880 PSEUDO_REGNO_MODE (regno
),
5881 reg_renumber
[regno
]))
5887 /* Global registers occurring in the current EBB. */
5888 static bitmap_head ebb_global_regs
;
5890 /* Return true if we need a split for hard register REGNO or pseudo
5891 REGNO which was assigned to a hard register.
5892 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5893 used for reloads since the EBB end. It is an approximation of the
5894 used hard registers in the split range. The exact value would
5895 require expensive calculations. If we were aggressive with
5896 splitting because of the approximation, the split pseudo will save
5897 the same hard register assignment and will be removed in the undo
5898 pass. We still need the approximation because too aggressive
5899 splitting would result in too inaccurate cost calculation in the
5900 assignment pass because of too many generated moves which will be
5901 probably removed in the undo pass. */
5903 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5905 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5907 lra_assert (hard_regno
>= 0);
5908 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5909 /* Don't split eliminable hard registers, otherwise we can
5910 split hard registers like hard frame pointer, which
5911 lives on BB start/end according to DF-infrastructure,
5912 when there is a pseudo assigned to the register and
5913 living in the same BB. */
5914 && (regno
>= FIRST_PSEUDO_REGISTER
5915 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5916 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5917 /* Don't split call clobbered hard regs living through
5918 calls, otherwise we might have a check problem in the
5919 assign sub-pass as in the most cases (exception is a
5920 situation when check_and_force_assignment_correctness_p value is
5921 true) the assign pass assumes that all pseudos living
5922 through calls are assigned to call saved hard regs. */
5923 && (regno
>= FIRST_PSEUDO_REGISTER
5924 || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers
, regno
))
5925 /* We need at least 2 reloads to make pseudo splitting
5926 profitable. We should provide hard regno splitting in
5927 any case to solve 1st insn scheduling problem when
5928 moving hard register definition up might result in
5929 impossibility to find hard register for reload pseudo of
5930 small register class. */
5931 && (usage_insns
[regno
].reloads_num
5932 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5933 && (regno
< FIRST_PSEUDO_REGISTER
5934 /* For short living pseudos, spilling + inheritance can
5935 be considered a substitution for splitting.
5936 Therefore we do not splitting for local pseudos. It
5937 decreases also aggressiveness of splitting. The
5938 minimal number of references is chosen taking into
5939 account that for 2 references splitting has no sense
5940 as we can just spill the pseudo. */
5941 || (regno
>= FIRST_PSEUDO_REGISTER
5942 && lra_reg_info
[regno
].nrefs
> 3
5943 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5944 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5947 /* Return class for the split pseudo created from original pseudo with
5948 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5949 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5950 results in no secondary memory movements. */
5951 static enum reg_class
5952 choose_split_class (enum reg_class allocno_class
,
5953 int hard_regno ATTRIBUTE_UNUSED
,
5954 machine_mode mode ATTRIBUTE_UNUSED
)
5957 enum reg_class cl
, best_cl
= NO_REGS
;
5958 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5959 = REGNO_REG_CLASS (hard_regno
);
5961 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5962 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5963 return allocno_class
;
5965 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5967 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5968 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5969 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5970 && (best_cl
== NO_REGS
5971 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5976 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. It only
5977 makes sense to call this function if NEW_REGNO is always equal to
5978 ORIGINAL_REGNO. Set up defined_p flag when caller_save_p flag is set up and
5979 CALL_SAVE_P is true. */
5982 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
,
5985 if (!ira_reg_equiv
[original_regno
].defined_p
5986 && !(call_save_p
&& ira_reg_equiv
[original_regno
].caller_save_p
))
5989 ira_expand_reg_equiv ();
5990 ira_reg_equiv
[new_regno
].defined_p
= true;
5991 if (ira_reg_equiv
[original_regno
].memory
)
5992 ira_reg_equiv
[new_regno
].memory
5993 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5994 if (ira_reg_equiv
[original_regno
].constant
)
5995 ira_reg_equiv
[new_regno
].constant
5996 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5997 if (ira_reg_equiv
[original_regno
].invariant
)
5998 ira_reg_equiv
[new_regno
].invariant
5999 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
6002 /* Do split transformations for insn INSN, which defines or uses
6003 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
6004 the EBB next uses ORIGINAL_REGNO; it has the same form as the
6005 "insns" field of usage_insns. If TO is not NULL, we don't use
6006 usage_insns, we put restore insns after TO insn. It is a case when
6007 we call it from lra_split_hard_reg_for, outside the inheritance
6010 The transformations look like:
6013 ... s <- p (new insn -- save)
6015 ... p <- s (new insn -- restore)
6016 <- ... p ... <- ... p ...
6018 <- ... p ... <- ... p ...
6019 ... s <- p (new insn -- save)
6021 ... p <- s (new insn -- restore)
6022 <- ... p ... <- ... p ...
6024 where p is an original pseudo got a hard register or a hard
6025 register and s is a new split pseudo. The save is put before INSN
6026 if BEFORE_P is true. Return true if we succeed in such
6029 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
6030 rtx next_usage_insns
, rtx_insn
*to
)
6032 enum reg_class rclass
;
6034 int hard_regno
, nregs
;
6035 rtx new_reg
, usage_insn
;
6036 rtx_insn
*restore
, *save
;
6041 if (original_regno
< FIRST_PSEUDO_REGISTER
)
6043 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
6044 hard_regno
= original_regno
;
6045 call_save_p
= false;
6047 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
6048 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
6049 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as
6050 part of a multi-word register. In that case, just use the reg_rtx
6051 mode. Do the same also if the biggest mode was larger than a register
6052 or we can not compare the modes. Otherwise, limit the size to that of
6053 the biggest access in the function or to the natural mode at least. */
6054 if (mode
== VOIDmode
6055 || !ordered_p (GET_MODE_PRECISION (mode
),
6056 GET_MODE_PRECISION (reg_rtx_mode
))
6057 || paradoxical_subreg_p (mode
, reg_rtx_mode
)
6058 || maybe_gt (GET_MODE_PRECISION (reg_rtx_mode
), GET_MODE_PRECISION (mode
)))
6060 original_reg
= regno_reg_rtx
[hard_regno
];
6061 mode
= reg_rtx_mode
;
6064 original_reg
= gen_rtx_REG (mode
, hard_regno
);
6068 mode
= PSEUDO_REGNO_MODE (original_regno
);
6069 hard_regno
= reg_renumber
[original_regno
];
6070 nregs
= hard_regno_nregs (hard_regno
, mode
);
6071 rclass
= lra_get_allocno_class (original_regno
);
6072 original_reg
= regno_reg_rtx
[original_regno
];
6073 call_save_p
= need_for_call_save_p (original_regno
);
6075 lra_assert (hard_regno
>= 0);
6076 if (lra_dump_file
!= NULL
)
6077 fprintf (lra_dump_file
,
6078 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
6082 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
6083 hard_regno_nregs (hard_regno
, mode
),
6085 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, NULL
, "save");
6089 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
6090 if (rclass
== NO_REGS
)
6092 if (lra_dump_file
!= NULL
)
6094 fprintf (lra_dump_file
,
6095 " Rejecting split of %d(%s): "
6096 "no good reg class for %d(%s)\n",
6098 reg_class_names
[lra_get_allocno_class (original_regno
)],
6100 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
6103 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6107 /* Split_if_necessary can split hard registers used as part of a
6108 multi-register mode but splits each register individually. The
6109 mode used for each independent register may not be supported
6110 so reject the split. Splitting the wider mode should theoretically
6111 be possible but is not implemented. */
6112 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
6114 if (lra_dump_file
!= NULL
)
6116 fprintf (lra_dump_file
,
6117 " Rejecting split of %d(%s): unsuitable mode %s\n",
6119 reg_class_names
[lra_get_allocno_class (original_regno
)],
6120 GET_MODE_NAME (mode
));
6123 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6127 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, NULL
, "split");
6128 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
6130 int new_regno
= REGNO (new_reg
);
6131 save
= emit_spill_move (true, new_reg
, original_reg
);
6132 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
6134 if (lra_dump_file
!= NULL
)
6138 " Rejecting split %d->%d resulting in > 2 save insns:\n",
6139 original_regno
, new_regno
);
6140 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
6141 fprintf (lra_dump_file
,
6142 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6146 restore
= emit_spill_move (false, new_reg
, original_reg
);
6147 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
6149 if (lra_dump_file
!= NULL
)
6151 fprintf (lra_dump_file
,
6152 " Rejecting split %d->%d "
6153 "resulting in > 2 restore insns:\n",
6154 original_regno
, new_regno
);
6155 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
6156 fprintf (lra_dump_file
,
6157 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6161 /* Transfer equivalence information to the spill register, so that
6162 if we fail to allocate the spill register, we have the option of
6163 rematerializing the original value instead of spilling to the stack. */
6164 if (!HARD_REGISTER_NUM_P (original_regno
)
6165 && mode
== PSEUDO_REGNO_MODE (original_regno
))
6166 lra_copy_reg_equiv (new_regno
, original_regno
, call_save_p
);
6167 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
6168 bitmap_set_bit (&lra_split_regs
, new_regno
);
6171 lra_assert (next_usage_insns
== NULL
);
6177 /* We need check_only_regs only inside the inheritance pass. */
6178 bitmap_set_bit (&check_only_regs
, new_regno
);
6179 bitmap_set_bit (&check_only_regs
, original_regno
);
6180 after_p
= usage_insns
[original_regno
].after_p
;
6183 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
6185 usage_insn
= next_usage_insns
;
6188 usage_insn
= XEXP (next_usage_insns
, 0);
6189 lra_assert (DEBUG_INSN_P (usage_insn
));
6190 next_usage_insns
= XEXP (next_usage_insns
, 1);
6191 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
6193 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
6194 if (lra_dump_file
!= NULL
)
6196 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
6197 original_regno
, new_regno
);
6198 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
6202 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
6203 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
6204 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
6205 after_p
? NULL
: restore
,
6206 after_p
? restore
: NULL
,
6208 ? "Add reg<-save" : "Add reg<-split");
6209 lra_process_new_insns (insn
, before_p
? save
: NULL
,
6210 before_p
? NULL
: save
,
6212 ? "Add save<-reg" : "Add split<-reg");
6213 if (nregs
> 1 || original_regno
< FIRST_PSEUDO_REGISTER
)
6214 /* If we are trying to split multi-register. We should check
6215 conflicts on the next assignment sub-pass. IRA can allocate on
6216 sub-register levels, LRA do this on pseudos level right now and
6217 this discrepancy may create allocation conflicts after
6220 If we are trying to split hard register we should also check conflicts
6221 as such splitting can create artificial conflict of the hard register
6222 with another pseudo because of simplified conflict calculation in
6224 check_and_force_assignment_correctness_p
= true;
6225 if (lra_dump_file
!= NULL
)
6226 fprintf (lra_dump_file
,
6227 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6231 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
6232 in the range [FROM, TO]. Return true if did a split. Otherwise,
6235 spill_hard_reg_in_range (int regno
, enum reg_class rclass
, rtx_insn
*from
, rtx_insn
*to
)
6242 HARD_REG_SET ignore
;
6244 lra_assert (from
!= NULL
&& to
!= NULL
);
6245 ignore
= lra_no_alloc_regs
;
6246 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
6248 lra_insn_recog_data_t id
= lra_insn_recog_data
[uid
];
6249 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
6250 struct lra_insn_reg
*reg
;
6252 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6253 if (reg
->regno
< FIRST_PSEUDO_REGISTER
)
6254 SET_HARD_REG_BIT (ignore
, reg
->regno
);
6255 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6256 SET_HARD_REG_BIT (ignore
, reg
->regno
);
6258 rclass_size
= ira_class_hard_regs_num
[rclass
];
6259 for (i
= 0; i
< rclass_size
; i
++)
6261 hard_regno
= ira_class_hard_regs
[rclass
][i
];
6262 if (! TEST_HARD_REG_BIT (lra_reg_info
[regno
].conflict_hard_regs
, hard_regno
)
6263 || TEST_HARD_REG_BIT (ignore
, hard_regno
))
6265 for (insn
= from
; insn
!= NEXT_INSN (to
); insn
= NEXT_INSN (insn
))
6267 struct lra_static_insn_data
*static_id
;
6268 struct lra_insn_reg
*reg
;
6272 if (bitmap_bit_p (&lra_reg_info
[hard_regno
].insn_bitmap
,
6275 static_id
= lra_get_insn_recog_data (insn
)->insn_static_data
;
6276 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6277 if (reg
->regno
== hard_regno
)
6282 if (insn
!= NEXT_INSN (to
))
6284 if (split_reg (true, hard_regno
, from
, NULL
, to
))
6290 /* Recognize that we need a split transformation for insn INSN, which
6291 defines or uses REGNO in its insn biggest MODE (we use it only if
6292 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
6293 hard registers which might be used for reloads since the EBB end.
6294 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
6295 uid before starting INSN processing. Return true if we succeed in
6296 such transformation. */
6298 split_if_necessary (int regno
, machine_mode mode
,
6299 HARD_REG_SET potential_reload_hard_regs
,
6300 bool before_p
, rtx_insn
*insn
, int max_uid
)
6304 rtx next_usage_insns
;
6306 if (regno
< FIRST_PSEUDO_REGISTER
)
6307 nregs
= hard_regno_nregs (regno
, mode
);
6308 for (i
= 0; i
< nregs
; i
++)
6309 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
6310 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
6311 /* To avoid processing the register twice or more. */
6312 && ((GET_CODE (next_usage_insns
) != INSN_LIST
6313 && INSN_UID (next_usage_insns
) < max_uid
)
6314 || (GET_CODE (next_usage_insns
) == INSN_LIST
6315 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
6316 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
6317 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
, NULL
))
6322 /* Return TRUE if rtx X is considered as an invariant for
6325 invariant_p (const_rtx x
)
6332 if (side_effects_p (x
))
6335 code
= GET_CODE (x
);
6336 mode
= GET_MODE (x
);
6340 code
= GET_CODE (x
);
6341 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
6349 int i
, nregs
, regno
= REGNO (x
);
6351 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
6352 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
6353 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
6355 nregs
= hard_regno_nregs (regno
, mode
);
6356 for (i
= 0; i
< nregs
; i
++)
6357 if (! fixed_regs
[regno
+ i
]
6358 /* A hard register may be clobbered in the current insn
6359 but we can ignore this case because if the hard
6360 register is used it should be set somewhere after the
6362 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
6365 fmt
= GET_RTX_FORMAT (code
);
6366 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6370 if (! invariant_p (XEXP (x
, i
)))
6373 else if (fmt
[i
] == 'E')
6375 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6376 if (! invariant_p (XVECEXP (x
, i
, j
)))
6383 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
6384 inheritance transformation (using dest_reg instead invariant in a
6385 subsequent insn). */
6387 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
6389 invariant_ptr_t invariant_ptr
;
6390 rtx_insn
*insn
, *new_insns
;
6391 rtx insn_set
, insn_reg
, new_reg
;
6393 bool succ_p
= false;
6394 int dst_regno
= REGNO (dst_reg
);
6395 machine_mode dst_mode
= GET_MODE (dst_reg
);
6396 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
6398 invariant_ptr
= insert_invariant (invariant_rtx
);
6399 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
6401 /* We have a subsequent insn using the invariant. */
6402 insn_set
= single_set (insn
);
6403 lra_assert (insn_set
!= NULL
);
6404 insn_reg
= SET_DEST (insn_set
);
6405 lra_assert (REG_P (insn_reg
));
6406 insn_regno
= REGNO (insn_reg
);
6407 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
6409 if (dst_mode
== GET_MODE (insn_reg
)
6410 /* We should consider only result move reg insns which are
6412 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
6413 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
6415 if (lra_dump_file
!= NULL
)
6416 fprintf (lra_dump_file
,
6417 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
6418 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
, cl
, NULL
,
6419 "invariant inheritance");
6420 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
6421 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
6422 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
6424 lra_emit_move (new_reg
, dst_reg
);
6425 new_insns
= get_insns ();
6427 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6428 "Add invariant inheritance<-original");
6430 lra_emit_move (SET_DEST (insn_set
), new_reg
);
6431 new_insns
= get_insns ();
6433 lra_process_new_insns (insn
, NULL
, new_insns
,
6434 "Changing reload<-inheritance");
6435 lra_set_insn_deleted (insn
);
6437 if (lra_dump_file
!= NULL
)
6439 fprintf (lra_dump_file
,
6440 " Invariant inheritance reuse change %d (bb%d):\n",
6441 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
6442 dump_insn_slim (lra_dump_file
, insn
);
6443 fprintf (lra_dump_file
,
6444 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
6448 invariant_ptr
->insn
= curr_insn
;
6452 /* Check only registers living at the current program point in the
6454 static bitmap_head live_regs
;
6456 /* Update live info in EBB given by its HEAD and TAIL insns after
6457 inheritance/split transformation. The function removes dead moves
6460 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
6465 rtx_insn
*prev_insn
;
6468 basic_block last_bb
, prev_bb
, curr_bb
;
6470 struct lra_insn_reg
*reg
;
6474 last_bb
= BLOCK_FOR_INSN (tail
);
6476 for (curr_insn
= tail
;
6477 curr_insn
!= PREV_INSN (head
);
6478 curr_insn
= prev_insn
)
6480 prev_insn
= PREV_INSN (curr_insn
);
6481 /* We need to process empty blocks too. They contain
6482 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
6483 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
6485 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6486 if (curr_bb
!= prev_bb
)
6488 if (prev_bb
!= NULL
)
6490 /* Update df_get_live_in (prev_bb): */
6491 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6492 if (bitmap_bit_p (&live_regs
, j
))
6493 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
6495 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
6497 if (curr_bb
!= last_bb
)
6499 /* Update df_get_live_out (curr_bb): */
6500 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6502 live_p
= bitmap_bit_p (&live_regs
, j
);
6504 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
6505 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
6511 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
6513 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
6517 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
6519 if (! NONDEBUG_INSN_P (curr_insn
))
6521 curr_id
= lra_get_insn_recog_data (curr_insn
);
6522 curr_static_id
= curr_id
->insn_static_data
;
6524 if ((set
= single_set (curr_insn
)) != NULL_RTX
6525 && REG_P (SET_DEST (set
))
6526 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
6527 && SET_DEST (set
) != pic_offset_table_rtx
6528 && bitmap_bit_p (&check_only_regs
, regno
)
6529 && ! bitmap_bit_p (&live_regs
, regno
))
6531 /* See which defined values die here. */
6532 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6533 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6534 bitmap_clear_bit (&live_regs
, reg
->regno
);
6535 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6536 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6537 bitmap_clear_bit (&live_regs
, reg
->regno
);
6538 if (curr_id
->arg_hard_regs
!= NULL
)
6539 /* Make clobbered argument hard registers die. */
6540 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6541 if (regno
>= FIRST_PSEUDO_REGISTER
)
6542 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
6543 /* Mark each used value as live. */
6544 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6545 if (reg
->type
!= OP_OUT
6546 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6547 bitmap_set_bit (&live_regs
, reg
->regno
);
6548 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6549 if (reg
->type
!= OP_OUT
6550 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6551 bitmap_set_bit (&live_regs
, reg
->regno
);
6552 if (curr_id
->arg_hard_regs
!= NULL
)
6553 /* Make used argument hard registers live. */
6554 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6555 if (regno
< FIRST_PSEUDO_REGISTER
6556 && bitmap_bit_p (&check_only_regs
, regno
))
6557 bitmap_set_bit (&live_regs
, regno
);
6558 /* It is quite important to remove dead move insns because it
6559 means removing dead store. We don't need to process them for
6563 if (lra_dump_file
!= NULL
)
6565 fprintf (lra_dump_file
, " Removing dead insn:\n ");
6566 dump_insn_slim (lra_dump_file
, curr_insn
);
6568 lra_set_insn_deleted (curr_insn
);
6573 /* The structure describes info to do an inheritance for the current
6574 insn. We need to collect such info first before doing the
6575 transformations because the transformations change the insn
6576 internal representation. */
6579 /* Original regno. */
6581 /* Subsequent insns which can inherit original reg value. */
6585 /* Array containing all info for doing inheritance from the current
6587 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
6589 /* Number elements in the previous array. */
6590 static int to_inherit_num
;
6592 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6593 structure to_inherit. */
6595 add_to_inherit (int regno
, rtx insns
)
6599 for (i
= 0; i
< to_inherit_num
; i
++)
6600 if (to_inherit
[i
].regno
== regno
)
6602 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
6603 to_inherit
[to_inherit_num
].regno
= regno
;
6604 to_inherit
[to_inherit_num
++].insns
= insns
;
6607 /* Return the last non-debug insn in basic block BB, or the block begin
6610 get_last_insertion_point (basic_block bb
)
6614 FOR_BB_INSNS_REVERSE (bb
, insn
)
6615 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
6620 /* Set up RES by registers living on edges FROM except the edge (FROM,
6621 TO) or by registers set up in a jump insn in BB FROM. */
6623 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
6626 struct lra_insn_reg
*reg
;
6630 lra_assert (to
!= NULL
);
6632 FOR_EACH_EDGE (e
, ei
, from
->succs
)
6634 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
6635 last
= get_last_insertion_point (from
);
6636 if (! JUMP_P (last
))
6638 curr_id
= lra_get_insn_recog_data (last
);
6639 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6640 if (reg
->type
!= OP_IN
)
6641 bitmap_set_bit (res
, reg
->regno
);
6644 /* Used as a temporary results of some bitmap calculations. */
6645 static bitmap_head temp_bitmap
;
6647 /* We split for reloads of small class of hard regs. The following
6648 defines how many hard regs the class should have to be qualified as
6649 small. The code is mostly oriented to x86/x86-64 architecture
6650 where some insns need to use only specific register or pair of
6651 registers and these register can live in RTL explicitly, e.g. for
6652 parameter passing. */
6653 static const int max_small_class_regs_num
= 2;
6655 /* Do inheritance/split transformations in EBB starting with HEAD and
6656 finishing on TAIL. We process EBB insns in the reverse order.
6657 Return true if we did any inheritance/split transformation in the
6660 We should avoid excessive splitting which results in worse code
6661 because of inaccurate cost calculations for spilling new split
6662 pseudos in such case. To achieve this we do splitting only if
6663 register pressure is high in given basic block and there are reload
6664 pseudos requiring hard registers. We could do more register
6665 pressure calculations at any given program point to avoid necessary
6666 splitting even more but it is to expensive and the current approach
6667 works well enough. */
6669 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6671 int i
, src_regno
, dst_regno
, nregs
;
6672 bool change_p
, succ_p
, update_reloads_num_p
;
6673 rtx_insn
*prev_insn
, *last_insn
;
6674 rtx next_usage_insns
, curr_set
;
6676 struct lra_insn_reg
*reg
;
6677 basic_block last_processed_bb
, curr_bb
= NULL
;
6678 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6682 bool head_p
, after_p
;
6685 curr_usage_insns_check
++;
6686 clear_invariants ();
6687 reloads_num
= calls_num
= 0;
6688 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
6689 last_call_for_abi
[i
] = 0;
6690 CLEAR_HARD_REG_SET (full_and_partial_call_clobbers
);
6691 bitmap_clear (&check_only_regs
);
6692 bitmap_clear (&invalid_invariant_regs
);
6693 last_processed_bb
= NULL
;
6694 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6695 live_hard_regs
= eliminable_regset
| lra_no_alloc_regs
;
6696 /* We don't process new insns generated in the loop. */
6697 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6699 prev_insn
= PREV_INSN (curr_insn
);
6700 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6701 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6702 if (last_processed_bb
!= curr_bb
)
6704 /* We are at the end of BB. Add qualified living
6705 pseudos for potential splitting. */
6706 to_process
= df_get_live_out (curr_bb
);
6707 if (last_processed_bb
!= NULL
)
6709 /* We are somewhere in the middle of EBB. */
6710 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6712 to_process
= &temp_bitmap
;
6714 last_processed_bb
= curr_bb
;
6715 last_insn
= get_last_insertion_point (curr_bb
);
6716 after_p
= (! JUMP_P (last_insn
)
6717 && (! CALL_P (last_insn
)
6718 || (find_reg_note (last_insn
,
6719 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6720 && ! SIBLING_CALL_P (last_insn
))));
6721 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6722 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6724 if ((int) j
>= lra_constraint_new_regno_start
)
6726 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6728 if (j
< FIRST_PSEUDO_REGISTER
)
6729 SET_HARD_REG_BIT (live_hard_regs
, j
);
6731 add_to_hard_reg_set (&live_hard_regs
,
6732 PSEUDO_REGNO_MODE (j
),
6734 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6738 src_regno
= dst_regno
= -1;
6739 curr_set
= single_set (curr_insn
);
6740 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6741 dst_regno
= REGNO (SET_DEST (curr_set
));
6742 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6743 src_regno
= REGNO (SET_SRC (curr_set
));
6744 update_reloads_num_p
= true;
6745 if (src_regno
< lra_constraint_new_regno_start
6746 && src_regno
>= FIRST_PSEUDO_REGISTER
6747 && reg_renumber
[src_regno
] < 0
6748 && dst_regno
>= lra_constraint_new_regno_start
6749 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6751 /* 'reload_pseudo <- original_pseudo'. */
6752 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6754 update_reloads_num_p
= false;
6756 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6757 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6758 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6759 curr_insn
, next_usage_insns
);
6763 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6764 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6765 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6767 else if (src_regno
< 0
6768 && dst_regno
>= lra_constraint_new_regno_start
6769 && invariant_p (SET_SRC (curr_set
))
6770 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6771 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6772 && ! bitmap_bit_p (&invalid_invariant_regs
,
6773 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6775 /* 'reload_pseudo <- invariant'. */
6776 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6778 update_reloads_num_p
= false;
6779 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6781 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6782 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6784 else if (src_regno
>= lra_constraint_new_regno_start
6785 && dst_regno
< lra_constraint_new_regno_start
6786 && dst_regno
>= FIRST_PSEUDO_REGISTER
6787 && reg_renumber
[dst_regno
] < 0
6788 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6789 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6790 && (next_usage_insns
6791 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6793 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6795 update_reloads_num_p
= false;
6796 /* 'original_pseudo <- reload_pseudo'. */
6797 if (! JUMP_P (curr_insn
)
6798 && inherit_reload_reg (true, dst_regno
, cl
,
6799 curr_insn
, next_usage_insns
))
6802 usage_insns
[dst_regno
].check
= 0;
6803 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6804 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6806 else if (INSN_P (curr_insn
))
6809 int max_uid
= get_max_uid ();
6811 curr_id
= lra_get_insn_recog_data (curr_insn
);
6812 curr_static_id
= curr_id
->insn_static_data
;
6814 /* Process insn definitions. */
6815 for (iter
= 0; iter
< 2; iter
++)
6816 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6819 if (reg
->type
!= OP_IN
6820 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6822 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6823 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6824 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6825 && (next_usage_insns
6826 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6828 struct lra_insn_reg
*r
;
6830 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6831 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6833 /* Don't do inheritance if the pseudo is also
6834 used in the insn. */
6836 /* We cannot do inheritance right now
6837 because the current insn reg info (chain
6838 regs) can change after that. */
6839 add_to_inherit (dst_regno
, next_usage_insns
);
6841 /* We cannot process one reg twice here because of
6842 usage_insns invalidation. */
6843 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6844 || reg_renumber
[dst_regno
] >= 0)
6845 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6849 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6850 potential_reload_hard_regs
,
6851 false, curr_insn
, max_uid
))
6853 CLEAR_HARD_REG_SET (s
);
6854 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6855 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6857 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6858 reg_renumber
[dst_regno
]);
6859 live_hard_regs
&= ~s
;
6860 potential_reload_hard_regs
&= ~s
;
6862 /* We should invalidate potential inheritance or
6863 splitting for the current insn usages to the next
6864 usage insns (see code below) as the output pseudo
6866 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6867 && reg_renumber
[dst_regno
] < 0)
6868 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6869 && (dst_regno
< FIRST_PSEUDO_REGISTER
6870 || reg_renumber
[dst_regno
] >= 0)))
6872 /* Invalidate and mark definitions. */
6873 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6874 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6877 nregs
= hard_regno_nregs (dst_regno
,
6879 for (i
= 0; i
< nregs
; i
++)
6880 usage_insns
[dst_regno
+ i
].check
6881 = -(int) INSN_UID (curr_insn
);
6885 /* Process clobbered call regs. */
6886 if (curr_id
->arg_hard_regs
!= NULL
)
6887 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6888 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6889 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6890 = -(int) INSN_UID (curr_insn
);
6891 if (! JUMP_P (curr_insn
))
6892 for (i
= 0; i
< to_inherit_num
; i
++)
6893 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6894 ALL_REGS
, curr_insn
,
6895 to_inherit
[i
].insns
))
6897 if (CALL_P (curr_insn
))
6899 rtx cheap
, pat
, dest
;
6901 int regno
, hard_regno
;
6904 function_abi callee_abi
= insn_callee_abi (curr_insn
);
6905 last_call_for_abi
[callee_abi
.id ()] = calls_num
;
6906 full_and_partial_call_clobbers
6907 |= callee_abi
.full_and_partial_reg_clobbers ();
6908 if ((cheap
= find_reg_note (curr_insn
,
6909 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6910 && ((cheap
= XEXP (cheap
, 0)), true)
6911 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6912 && (hard_regno
= reg_renumber
[regno
]) >= 0
6913 && usage_insns
[regno
].check
== curr_usage_insns_check
6914 /* If there are pending saves/restores, the
6915 optimization is not worth. */
6916 && usage_insns
[regno
].calls_num
== calls_num
- 1
6917 && callee_abi
.clobbers_reg_p (GET_MODE (cheap
), hard_regno
))
6919 /* Restore the pseudo from the call result as
6920 REG_RETURNED note says that the pseudo value is
6921 in the call result and the pseudo is an argument
6923 pat
= PATTERN (curr_insn
);
6924 if (GET_CODE (pat
) == PARALLEL
)
6925 pat
= XVECEXP (pat
, 0, 0);
6926 dest
= SET_DEST (pat
);
6927 /* For multiple return values dest is PARALLEL.
6928 Currently we handle only single return value case. */
6932 emit_move_insn (cheap
, copy_rtx (dest
));
6933 restore
= get_insns ();
6935 lra_process_new_insns (curr_insn
, NULL
, restore
,
6936 "Inserting call parameter restore");
6937 /* We don't need to save/restore of the pseudo from
6939 usage_insns
[regno
].calls_num
= calls_num
;
6940 remove_from_hard_reg_set
6941 (&full_and_partial_call_clobbers
,
6942 GET_MODE (cheap
), hard_regno
);
6943 bitmap_set_bit (&check_only_regs
, regno
);
6948 /* Process insn usages. */
6949 for (iter
= 0; iter
< 2; iter
++)
6950 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6953 if ((reg
->type
!= OP_OUT
6954 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6955 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6957 if (src_regno
>= FIRST_PSEUDO_REGISTER
6958 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6960 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6961 && (next_usage_insns
6962 = usage_insns
[src_regno
].insns
) != NULL_RTX
6963 && NONDEBUG_INSN_P (curr_insn
))
6964 add_to_inherit (src_regno
, next_usage_insns
);
6965 else if (usage_insns
[src_regno
].check
6966 != -(int) INSN_UID (curr_insn
))
6967 /* Add usages but only if the reg is not set up
6968 in the same insn. */
6969 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6971 else if (src_regno
< FIRST_PSEUDO_REGISTER
6972 || reg_renumber
[src_regno
] >= 0)
6975 rtx_insn
*use_insn
= curr_insn
;
6977 before_p
= (JUMP_P (curr_insn
)
6978 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6979 if (NONDEBUG_INSN_P (curr_insn
)
6980 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6981 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6982 potential_reload_hard_regs
,
6983 before_p
, curr_insn
, max_uid
))
6986 check_and_force_assignment_correctness_p
= true;
6989 usage_insns
[src_regno
].check
= 0;
6991 use_insn
= PREV_INSN (curr_insn
);
6993 if (NONDEBUG_INSN_P (curr_insn
))
6995 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6996 add_to_hard_reg_set (&live_hard_regs
,
6997 reg
->biggest_mode
, src_regno
);
6999 add_to_hard_reg_set (&live_hard_regs
,
7000 PSEUDO_REGNO_MODE (src_regno
),
7001 reg_renumber
[src_regno
]);
7003 if (src_regno
>= FIRST_PSEUDO_REGISTER
)
7004 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
7007 for (i
= 0; i
< hard_regno_nregs (src_regno
, reg
->biggest_mode
); i
++)
7008 add_next_usage_insn (src_regno
+ i
, use_insn
, reloads_num
);
7012 /* Process used call regs. */
7013 if (curr_id
->arg_hard_regs
!= NULL
)
7014 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
7015 if (src_regno
< FIRST_PSEUDO_REGISTER
)
7017 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
7018 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
7020 for (i
= 0; i
< to_inherit_num
; i
++)
7022 src_regno
= to_inherit
[i
].regno
;
7023 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
7024 curr_insn
, to_inherit
[i
].insns
))
7027 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
7030 if (update_reloads_num_p
7031 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
7034 if ((REG_P (SET_DEST (curr_set
))
7035 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
7036 && reg_renumber
[regno
] < 0
7037 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
7038 || (REG_P (SET_SRC (curr_set
))
7039 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
7040 && reg_renumber
[regno
] < 0
7041 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
7043 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
7045 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
7046 potential_reload_hard_regs
|= reg_class_contents
[cl
];
7049 if (NONDEBUG_INSN_P (curr_insn
))
7053 /* Invalidate invariants with changed regs. */
7054 curr_id
= lra_get_insn_recog_data (curr_insn
);
7055 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7056 if (reg
->type
!= OP_IN
)
7058 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
7059 bitmap_set_bit (&invalid_invariant_regs
,
7060 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
7062 curr_static_id
= curr_id
->insn_static_data
;
7063 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
7064 if (reg
->type
!= OP_IN
)
7065 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
7066 if (curr_id
->arg_hard_regs
!= NULL
)
7067 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
7068 if (regno
>= FIRST_PSEUDO_REGISTER
)
7069 bitmap_set_bit (&invalid_invariant_regs
,
7070 regno
- FIRST_PSEUDO_REGISTER
);
7072 /* We reached the start of the current basic block. */
7073 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
7074 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
7076 /* We reached the beginning of the current block -- do
7077 rest of spliting in the current BB. */
7078 to_process
= df_get_live_in (curr_bb
);
7079 if (BLOCK_FOR_INSN (head
) != curr_bb
)
7081 /* We are somewhere in the middle of EBB. */
7082 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
7083 curr_bb
, &temp_bitmap
);
7084 to_process
= &temp_bitmap
;
7087 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
7089 if ((int) j
>= lra_constraint_new_regno_start
)
7091 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
7092 && usage_insns
[j
].check
== curr_usage_insns_check
7093 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
7095 if (need_for_split_p (potential_reload_hard_regs
, j
))
7097 if (lra_dump_file
!= NULL
&& head_p
)
7099 fprintf (lra_dump_file
,
7100 " ----------------------------------\n");
7103 if (split_reg (false, j
, bb_note (curr_bb
),
7104 next_usage_insns
, NULL
))
7107 usage_insns
[j
].check
= 0;
7115 /* This value affects EBB forming. If probability of edge from EBB to
7116 a BB is not greater than the following value, we don't add the BB
7118 #define EBB_PROBABILITY_CUTOFF \
7119 ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
7121 /* Current number of inheritance/split iteration. */
7122 int lra_inheritance_iter
;
7124 /* Entry function for inheritance/split pass. */
7126 lra_inheritance (void)
7129 basic_block bb
, start_bb
;
7132 lra_inheritance_iter
++;
7133 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7135 timevar_push (TV_LRA_INHERITANCE
);
7136 if (lra_dump_file
!= NULL
)
7137 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
7138 lra_inheritance_iter
);
7139 curr_usage_insns_check
= 0;
7140 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
7141 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
7142 usage_insns
[i
].check
= 0;
7143 bitmap_initialize (&check_only_regs
, ®_obstack
);
7144 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
7145 bitmap_initialize (&live_regs
, ®_obstack
);
7146 bitmap_initialize (&temp_bitmap
, ®_obstack
);
7147 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
7148 FOR_EACH_BB_FN (bb
, cfun
)
7151 if (lra_dump_file
!= NULL
)
7152 fprintf (lra_dump_file
, "EBB");
7153 /* Form a EBB starting with BB. */
7154 bitmap_clear (&ebb_global_regs
);
7155 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
7158 if (lra_dump_file
!= NULL
)
7159 fprintf (lra_dump_file
, " %d", bb
->index
);
7160 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
7161 || LABEL_P (BB_HEAD (bb
->next_bb
)))
7163 e
= find_fallthru_edge (bb
->succs
);
7166 if (e
->probability
.initialized_p ()
7167 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
7171 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
7172 if (lra_dump_file
!= NULL
)
7173 fprintf (lra_dump_file
, "\n");
7174 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
7175 /* Remember that the EBB head and tail can change in
7177 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
7179 bitmap_release (&ebb_global_regs
);
7180 bitmap_release (&temp_bitmap
);
7181 bitmap_release (&live_regs
);
7182 bitmap_release (&invalid_invariant_regs
);
7183 bitmap_release (&check_only_regs
);
7185 lra_dump_insns_if_possible ("func after inheritance");
7186 timevar_pop (TV_LRA_INHERITANCE
);
7191 /* This page contains code to undo failed inheritance/split
7194 /* Current number of iteration undoing inheritance/split. */
7195 int lra_undo_inheritance_iter
;
7197 /* Fix BB live info LIVE after removing pseudos created on pass doing
7198 inheritance/split which are REMOVED_PSEUDOS. */
7200 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
7205 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
7206 if (bitmap_clear_bit (live
, regno
)
7207 && REG_P (lra_reg_info
[regno
].restore_rtx
))
7208 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
7211 /* Return regno of the (subreg of) REG. Otherwise, return a negative
7216 if (GET_CODE (reg
) == SUBREG
)
7217 reg
= SUBREG_REG (reg
);
7223 /* Delete a move INSN with destination reg DREGNO and a previous
7224 clobber insn with the same regno. The inheritance/split code can
7225 generate moves with preceding clobber and when we delete such moves
7226 we should delete the clobber insn too to keep the correct life
7229 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
7231 rtx_insn
*prev_insn
= PREV_INSN (insn
);
7233 lra_set_insn_deleted (insn
);
7234 lra_assert (dregno
>= 0);
7235 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
7236 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
7237 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
7238 lra_set_insn_deleted (prev_insn
);
7241 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
7242 return true if we did any change. The undo transformations for
7243 inheritance looks like
7247 p <- i, i <- p, and i <- i3
7248 where p is original pseudo from which inheritance pseudo i was
7249 created, i and i3 are removed inheritance pseudos, i2 is another
7250 not removed inheritance pseudo. All split pseudos or other
7251 occurrences of removed inheritance pseudos are changed on the
7252 corresponding original pseudos.
7254 The function also schedules insns changed and created during
7255 inheritance/split pass for processing by the subsequent constraint
7258 remove_inheritance_pseudos (bitmap remove_pseudos
)
7261 int regno
, sregno
, prev_sregno
, dregno
;
7264 rtx_insn
*prev_insn
;
7265 bool change_p
, done_p
;
7267 change_p
= ! bitmap_empty_p (remove_pseudos
);
7268 /* We cannot finish the function right away if CHANGE_P is true
7269 because we need to marks insns affected by previous
7270 inheritance/split pass for processing by the subsequent
7272 FOR_EACH_BB_FN (bb
, cfun
)
7274 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
7275 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
7276 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
7278 if (! INSN_P (curr_insn
))
7281 sregno
= dregno
= -1;
7282 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
7283 && (set
= single_set (curr_insn
)) != NULL_RTX
)
7285 dregno
= get_regno (SET_DEST (set
));
7286 sregno
= get_regno (SET_SRC (set
));
7289 if (sregno
>= 0 && dregno
>= 0)
7291 if (bitmap_bit_p (remove_pseudos
, dregno
)
7292 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
7294 /* invariant inheritance pseudo <- original pseudo */
7295 if (lra_dump_file
!= NULL
)
7297 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
7298 dump_insn_slim (lra_dump_file
, curr_insn
);
7299 fprintf (lra_dump_file
, "\n");
7301 delete_move_and_clobber (curr_insn
, dregno
);
7304 else if (bitmap_bit_p (remove_pseudos
, sregno
)
7305 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
7307 /* reload pseudo <- invariant inheritance pseudo */
7309 /* We cannot just change the source. It might be
7310 an insn different from the move. */
7311 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
7312 rtx_insn
*new_insns
= get_insns ();
7314 lra_assert (single_set (new_insns
) != NULL
7315 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
7316 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
7317 "Changing reload<-invariant inheritance");
7318 delete_move_and_clobber (curr_insn
, dregno
);
7321 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
7322 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
7323 || (bitmap_bit_p (remove_pseudos
, dregno
)
7324 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7325 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7326 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
7327 || (bitmap_bit_p (remove_pseudos
, dregno
)
7328 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
7329 /* One of the following cases:
7330 original <- removed inheritance pseudo
7331 removed inherit pseudo <- another removed inherit pseudo
7332 removed inherit pseudo <- original pseudo
7334 removed_split_pseudo <- original_reg
7335 original_reg <- removed_split_pseudo */
7337 if (lra_dump_file
!= NULL
)
7339 fprintf (lra_dump_file
, " Removing %s:\n",
7340 bitmap_bit_p (&lra_split_regs
, sregno
)
7341 || bitmap_bit_p (&lra_split_regs
, dregno
)
7342 ? "split" : "inheritance");
7343 dump_insn_slim (lra_dump_file
, curr_insn
);
7345 delete_move_and_clobber (curr_insn
, dregno
);
7348 else if (bitmap_bit_p (remove_pseudos
, sregno
)
7349 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
7351 /* Search the following pattern:
7352 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
7353 original_pseudo <- inherit_or_split_pseudo1
7354 where the 2nd insn is the current insn and
7355 inherit_or_split_pseudo2 is not removed. If it is found,
7356 change the current insn onto:
7357 original_pseudo <- inherit_or_split_pseudo2. */
7358 for (prev_insn
= PREV_INSN (curr_insn
);
7359 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
7360 prev_insn
= PREV_INSN (prev_insn
))
7362 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
7363 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
7364 /* There should be no subregs in insn we are
7365 searching because only the original reg might
7366 be in subreg when we changed the mode of
7367 load/store for splitting. */
7368 && REG_P (SET_DEST (prev_set
))
7369 && REG_P (SET_SRC (prev_set
))
7370 && (int) REGNO (SET_DEST (prev_set
)) == sregno
7371 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
7372 >= FIRST_PSEUDO_REGISTER
)
7373 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
7375 /* As we consider chain of inheritance or
7376 splitting described in above comment we should
7377 check that sregno and prev_sregno were
7378 inheritance/split pseudos created from the
7379 same original regno. */
7380 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7381 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7382 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
7383 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
7385 int restore_regno
= get_regno (lra_reg_info
[sregno
].restore_rtx
);
7386 if (restore_regno
< 0)
7387 restore_regno
= prev_sregno
;
7388 lra_assert (GET_MODE (SET_SRC (prev_set
))
7389 == GET_MODE (regno_reg_rtx
[restore_regno
]));
7390 /* Although we have a single set, the insn can
7391 contain more one sregno register occurrence
7392 as a source. Change all occurrences. */
7393 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
7394 regno_reg_rtx
[restore_regno
],
7396 /* As we are finishing with processing the insn
7397 here, check the destination too as it might
7398 inheritance pseudo for another pseudo. */
7399 if (bitmap_bit_p (remove_pseudos
, dregno
)
7400 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
7402 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
7404 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
7405 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
7407 SET_DEST (set
) = restore_rtx
;
7409 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7410 lra_set_used_insn_alternative_by_uid
7411 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7413 if (lra_dump_file
!= NULL
)
7415 fprintf (lra_dump_file
, " Change reload insn:\n");
7416 dump_insn_slim (lra_dump_file
, curr_insn
);
7423 struct lra_insn_reg
*reg
;
7424 bool restored_regs_p
= false;
7425 bool kept_regs_p
= false;
7427 curr_id
= lra_get_insn_recog_data (curr_insn
);
7428 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7431 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
7432 if (restore_rtx
!= NULL_RTX
)
7434 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
7436 lra_substitute_pseudo_within_insn
7437 (curr_insn
, regno
, restore_rtx
, false);
7438 restored_regs_p
= true;
7444 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
7446 /* The instruction has changed since the previous
7447 constraints pass. */
7448 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7449 lra_set_used_insn_alternative_by_uid
7450 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7452 else if (restored_regs_p
)
7453 /* The instruction has been restored to the form that
7454 it had during the previous constraints pass. */
7455 lra_update_insn_regno_info (curr_insn
);
7456 if (restored_regs_p
&& lra_dump_file
!= NULL
)
7458 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
7459 dump_insn_slim (lra_dump_file
, curr_insn
);
7467 /* If optional reload pseudos failed to get a hard register or was not
7468 inherited, it is better to remove optional reloads. We do this
7469 transformation after undoing inheritance to figure out necessity to
7470 remove optional reloads easier. Return true if we do any
7473 undo_optional_reloads (void)
7475 bool change_p
, keep_p
;
7476 unsigned int regno
, uid
;
7477 bitmap_iterator bi
, bi2
;
7480 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
7482 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
7483 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7486 /* Keep optional reloads from previous subpasses. */
7487 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
7488 /* If the original pseudo changed its allocation, just
7489 removing the optional pseudo is dangerous as the original
7490 pseudo will have longer live range. */
7491 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
7493 else if (reg_renumber
[regno
] >= 0)
7494 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
7496 insn
= lra_insn_recog_data
[uid
]->insn
;
7497 if ((set
= single_set (insn
)) == NULL_RTX
)
7499 src
= SET_SRC (set
);
7500 dest
= SET_DEST (set
);
7501 if ((! REG_P (src
) && ! SUBREG_P (src
))
7502 || (! REG_P (dest
) && ! SUBREG_P (dest
)))
7504 if (get_regno (dest
) == (int) regno
7505 /* Ignore insn for optional reloads itself. */
7506 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7508 /* Check only inheritance on last inheritance pass. */
7509 && get_regno (src
) >= new_regno_start
7510 /* Check that the optional reload was inherited. */
7511 && bitmap_bit_p (&lra_inheritance_pseudos
, get_regno (src
)))
7519 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
7520 if (lra_dump_file
!= NULL
)
7521 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
7524 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
7525 auto_bitmap
insn_bitmap (®_obstack
);
7526 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
7528 if (lra_dump_file
!= NULL
)
7529 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
7530 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
7531 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
7533 /* We may have already removed a clobber. */
7534 if (!lra_insn_recog_data
[uid
])
7536 insn
= lra_insn_recog_data
[uid
]->insn
;
7537 if ((set
= single_set (insn
)) != NULL_RTX
)
7539 src
= SET_SRC (set
);
7540 dest
= SET_DEST (set
);
7541 if ((REG_P (src
) || SUBREG_P (src
))
7542 && (REG_P (dest
) || SUBREG_P (dest
))
7543 && ((get_regno (src
) == (int) regno
7544 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7545 == get_regno (dest
)))
7546 || (get_regno (dest
) == (int) regno
7547 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7548 == get_regno (src
)))))
7550 if (lra_dump_file
!= NULL
)
7552 fprintf (lra_dump_file
, " Deleting move %u\n",
7554 dump_insn_slim (lra_dump_file
, insn
);
7556 delete_move_and_clobber (insn
, get_regno (dest
));
7559 /* We should not worry about generation memory-memory
7560 moves here as if the corresponding inheritance did
7561 not work (inheritance pseudo did not get a hard reg),
7562 we remove the inheritance pseudo and the optional
7565 if (GET_CODE (PATTERN (insn
)) == CLOBBER
7566 && REG_P (SET_DEST (insn
))
7567 && get_regno (SET_DEST (insn
)) == (int) regno
)
7568 /* Refuse to remap clobbers to preexisting pseudos. */
7570 lra_substitute_pseudo_within_insn
7571 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
7572 lra_update_insn_regno_info (insn
);
7573 if (lra_dump_file
!= NULL
)
7575 fprintf (lra_dump_file
,
7576 " Restoring original insn:\n");
7577 dump_insn_slim (lra_dump_file
, insn
);
7581 /* Clear restore_regnos. */
7582 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7583 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7587 /* Entry function for undoing inheritance/split transformation. Return true
7588 if we did any RTL change in this pass. */
7590 lra_undo_inheritance (void)
7594 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
7599 lra_undo_inheritance_iter
++;
7600 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7602 if (lra_dump_file
!= NULL
)
7603 fprintf (lra_dump_file
,
7604 "\n********** Undoing inheritance #%d: **********\n\n",
7605 lra_undo_inheritance_iter
);
7606 auto_bitmap
remove_pseudos (®_obstack
);
7607 n_inherit
= n_all_inherit
= 0;
7608 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7609 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
7612 if (reg_renumber
[regno
] < 0
7613 /* If the original pseudo changed its allocation, just
7614 removing inheritance is dangerous as for changing
7615 allocation we used shorter live-ranges. */
7616 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
7617 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
7618 bitmap_set_bit (remove_pseudos
, regno
);
7622 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
7623 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
7624 n_inherit
, n_all_inherit
,
7625 (double) n_inherit
/ n_all_inherit
* 100);
7626 n_split
= n_all_split
= 0;
7627 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7628 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
7630 int restore_regno
= REGNO (restore_rtx
);
7633 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
7634 ? reg_renumber
[restore_regno
] : restore_regno
);
7635 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
7636 bitmap_set_bit (remove_pseudos
, regno
);
7640 if (lra_dump_file
!= NULL
)
7641 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
7642 regno
, restore_regno
);
7645 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
7646 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
7647 n_split
, n_all_split
,
7648 (double) n_split
/ n_all_split
* 100);
7649 change_p
= remove_inheritance_pseudos (remove_pseudos
);
7650 /* Clear restore_regnos. */
7651 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7652 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7653 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7654 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7655 change_p
= undo_optional_reloads () || change_p
;
7657 lra_dump_insns_if_possible ("changed func after undoing inheritance");