[AArch64] Add combine pattern for storing lane zero of a vector
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / store_lane0_str_1.c
blob4464fec2c1f24c212be4fc6c94b509843fd0058e
1 /* { dg-do compile } */
2 /* { dg-options "-O2" } */
4 typedef int v2si __attribute__ ((vector_size (8)));
5 typedef float v2sf __attribute__ ((vector_size (8)));
6 typedef short v4hi __attribute__ ((vector_size (8)));
7 typedef __fp16 v4hf __attribute__ ((vector_size (8)));
8 typedef char v8qi __attribute__ ((vector_size (8)));
10 typedef int v4si __attribute__ ((vector_size (16)));
11 typedef float v4sf __attribute__ ((vector_size (16)));
12 typedef short v8hi __attribute__ ((vector_size (16)));
13 typedef __fp16 v8hf __attribute__ ((vector_size (16)));
14 typedef char v16qi __attribute__ ((vector_size (16)));
15 typedef long long v2di __attribute__ ((vector_size (16)));
16 typedef double v2df __attribute__ ((vector_size (16)));
18 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
19 #define LANE(N) (N - 1)
20 #else
21 #define LANE(N) 0
22 #endif
24 #define FUNC(T, E, N) \
25 void \
26 store_lane_##T (T x, E *y) \
27 { \
28 y[0] = x[N - 1 - LANE (N)]; \
29 y[3] = x[LANE (N)]; \
32 FUNC (v2si, int, 2)
33 FUNC (v2sf, float, 2)
34 FUNC (v4hi, short, 4)
35 FUNC (v4hf, __fp16, 4)
36 FUNC (v8qi, char, 8)
38 FUNC (v4si, int, 4)
39 FUNC (v4sf, float, 4)
40 FUNC (v8hi, short, 8)
41 FUNC (v8hf, __fp16, 8)
42 FUNC (v16qi, char, 16)
43 FUNC (v2di, long long, 2)
44 FUNC (v2df, double, 2)
46 /* When storing lane zero of a vector we can use the scalar STR instruction
47 that supports more addressing modes. */
49 /* { dg-final { scan-assembler-times "str\ts\[0-9\]+" 4 } } */
50 /* { dg-final { scan-assembler-times "str\tb\[0-9\]+" 2 } } */
51 /* { dg-final { scan-assembler-times "str\th\[0-9\]+" 4 } } */
52 /* { dg-final { scan-assembler-times "str\td\[0-9\]+" 2 } } */
53 /* { dg-final { scan-assembler-not "umov" } } */
54 /* { dg-final { scan-assembler-not "dup" } } */