[AArch64] Add combine pattern for storing lane zero of a vector
commit38a4c04c16d3c915d8dd37c967fbe1e56dbd92aa
authorktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 5 Jun 2017 08:52:02 +0000 (5 08:52 +0000)
committerktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 5 Jun 2017 08:52:02 +0000 (5 08:52 +0000)
treecfc8ea9bf517102b09175cd4e621302b1fa41679
parent25236514370ae7e0881c57529a83d5ce7745b0f5
[AArch64] Add combine pattern for storing lane zero of a vector

* config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>):
New pattern.

* gcc.target/aarch64/store_lane0_str_1.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248871 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog
gcc/config/aarch64/aarch64-simd.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/store_lane0_str_1.c [new file with mode: 0644]