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2008-05-30 Vladimir Makarov <vmakarov@redhat.com>
[official-gcc.git] / gcc / config / m68k / m68k.h
blob521ad84971650e691bf1f49921baafe3e69a7ea2
1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
22 if-statements and ?: on it. This way we have compile-time error checking
23 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
24 to optimize away all constant tests. */
25 #if MOTOROLA /* Use the Motorola assembly syntax. */
26 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
27 #else
28 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
30 #endif
31
32 /* Handle --with-cpu default option from configure script. */
33 #define OPTION_DEFAULT_SPECS \
34 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
35 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
36 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
37 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" },
38
39 /* Pass flags to gas indicating which type of processor we have. This
40 can be simplified when we can rely on the assembler supporting .cpu
41 and .arch directives. */
42
43 #define ASM_CPU_SPEC "\
44 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
45 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\
46 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\
47 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
48 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
49 "
50 #define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \
51 %{msep-data|mid-shared-library:--pcrel} \
52 "
53
54 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)"
55
56 #define EXTRA_SPECS \
57 { "asm_cpu_spec", ASM_CPU_SPEC }, \
58 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \
59 SUBTARGET_EXTRA_SPECS
60
61 #define SUBTARGET_EXTRA_SPECS
62
63 /* Note that some other tm.h files include this one and then override
64 many of the definitions that relate to assembler syntax. */
65
66 #define TARGET_CPU_CPP_BUILTINS() \
67 do \
68 { \
69 builtin_define ("__m68k__"); \
70 builtin_define_std ("mc68000"); \
71 /* The other mc680x0 macros have traditionally been derived \
72 from the tuning setting. For example, -m68020-60 defines \
73 m68060, even though it generates pure 68020 code. */ \
74 switch (m68k_tune) \
75 { \
76 case u68010: \
77 builtin_define_std ("mc68010"); \
78 break; \
79 \
80 case u68020: \
81 builtin_define_std ("mc68020"); \
82 break; \
83 \
84 case u68030: \
85 builtin_define_std ("mc68030"); \
86 break; \
87 \
88 case u68040: \
89 builtin_define_std ("mc68040"); \
90 break; \
91 \
92 case u68060: \
93 builtin_define_std ("mc68060"); \
94 break; \
95 \
96 case u68020_60: \
97 builtin_define_std ("mc68060"); \
98 /* Fall through. */ \
99 case u68020_40: \
100 builtin_define_std ("mc68040"); \
101 builtin_define_std ("mc68030"); \
102 builtin_define_std ("mc68020"); \
103 break; \
104 \
105 case ucpu32: \
106 builtin_define_std ("mc68332"); \
107 builtin_define_std ("mcpu32"); \
108 builtin_define_std ("mc68020"); \
109 break; \
110 \
111 case ucfv1: \
112 builtin_define ("__mcfv1__"); \
113 break; \
114 \
115 case ucfv2: \
116 builtin_define ("__mcfv2__"); \
117 break; \
118 \
119 case ucfv3: \
120 builtin_define ("__mcfv3__"); \
121 break; \
122 \
123 case ucfv4: \
124 builtin_define ("__mcfv4__"); \
125 break; \
126 \
127 case ucfv4e: \
128 builtin_define ("__mcfv4e__"); \
129 break; \
130 \
131 case ucfv5: \
132 builtin_define ("__mcfv5__"); \
133 break; \
134 \
135 default: \
136 break; \
137 } \
138 \
139 if (TARGET_68881) \
140 builtin_define ("__HAVE_68881__"); \
141 \
142 if (TARGET_COLDFIRE) \
143 { \
144 const char *tmp; \
145 \
146 tmp = m68k_cpp_cpu_ident ("cf"); \
147 if (tmp) \
148 builtin_define (tmp); \
149 tmp = m68k_cpp_cpu_family ("cf"); \
150 if (tmp) \
151 builtin_define (tmp); \
152 builtin_define ("__mcoldfire__"); \
153 \
154 if (TARGET_ISAC) \
155 builtin_define ("__mcfisac__"); \
156 else if (TARGET_ISAB) \
157 { \
158 builtin_define ("__mcfisab__"); \
159 /* ISA_B: Legacy 5407 defines. */ \
160 builtin_define ("__mcf5400__"); \
161 builtin_define ("__mcf5407__"); \
162 } \
163 else if (TARGET_ISAAPLUS) \
164 { \
165 builtin_define ("__mcfisaaplus__"); \
166 /* ISA_A+: legacy defines. */ \
167 builtin_define ("__mcf528x__"); \
168 builtin_define ("__mcf5200__"); \
169 } \
170 else \
171 { \
172 builtin_define ("__mcfisaa__"); \
173 /* ISA_A: legacy defines. */ \
174 switch (m68k_tune) \
175 { \
176 case ucfv2: \
177 builtin_define ("__mcf5200__"); \
178 break; \
179 \
180 case ucfv3: \
181 builtin_define ("__mcf5307__"); \
182 builtin_define ("__mcf5300__"); \
183 break; \
184 \
185 default: \
186 break; \
187 } \
188 } \
189 } \
190 \
191 if (TARGET_COLDFIRE_FPU) \
192 builtin_define ("__mcffpu__"); \
193 \
194 if (TARGET_CF_HWDIV) \
195 builtin_define ("__mcfhwdiv__"); \
196 \
197 if (TARGET_FIDOA) \
198 builtin_define ("__mfido__"); \
199 \
200 builtin_assert ("cpu=m68k"); \
201 builtin_assert ("machine=m68k"); \
202 } \
203 while (0)
204
205 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
206 quantities. */
207 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
208 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
209 #define INT_OP_NO_DOT 2 /* byte, short, long */
210 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
211
212 /* Set the default. */
213 #define INT_OP_GROUP INT_OP_DOT_WORD
214
215 /* Bit values used by m68k-devices.def to identify processor capabilities. */
216 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
217 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
218 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
219 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
220 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
221 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
222 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
223 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
224 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
225 #define FL_ISA_68000 (1 << 9)
226 #define FL_ISA_68010 (1 << 10)
227 #define FL_ISA_68020 (1 << 11)
228 #define FL_ISA_68040 (1 << 12)
229 #define FL_ISA_A (1 << 13)
230 #define FL_ISA_APLUS (1 << 14)
231 #define FL_ISA_B (1 << 15)
232 #define FL_ISA_C (1 << 16)
233 #define FL_FIDOA (1 << 17)
234 #define FL_MMU 0 /* Used by multilib machinery. */
235
236 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
237 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
238 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
239 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
240 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
241 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
242 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0)
243
244 /* Size (in bytes) of FPU registers. */
245 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
246
247 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
248 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
249 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
250
251 /* Some instructions are common to more than one ISA. */
252 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC)
253 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC)
254
255 #define TUNE_68000 (m68k_tune == u68000)
256 #define TUNE_68010 (m68k_tune == u68010)
257 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
258 #define TUNE_68030 (m68k_tune == u68030 \
259 || m68k_tune == u68020_40 \
260 || m68k_tune == u68020_60)
261 #define TUNE_68040 (m68k_tune == u68040 \
262 || m68k_tune == u68020_40 \
263 || m68k_tune == u68020_60)
264 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
265 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
266 #define TUNE_CPU32 (m68k_tune == ucpu32)
267 #define TUNE_CFV1 (m68k_tune == ucfv1)
268 #define TUNE_CFV2 (m68k_tune == ucfv2)
269 #define TUNE_CFV3 (m68k_tune == ucfv3)
270 #define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e)
271
272 #define OVERRIDE_OPTIONS override_options()
273
274 /* These are meant to be redefined in the host dependent files */
275 #define SUBTARGET_OVERRIDE_OPTIONS
276 \f
277 /* target machine storage layout */
278
279 /* "long double" is the same as "double" on ColdFire and fido
280 targets. */
281
282 #define LONG_DOUBLE_TYPE_SIZE \
283 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80)
284
285 /* We need to know the size of long double at compile-time in libgcc2. */
286
287 #if defined(__mcoldfire__) || defined(__mfido__)
288 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
289 #else
290 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
291 #endif
292
293 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
294 instructions, we get proper intermediate rounding, otherwise we
295 get extended precision results. */
296 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
297
298 #define BITS_BIG_ENDIAN 1
299 #define BYTES_BIG_ENDIAN 1
300 #define WORDS_BIG_ENDIAN 1
301
302 #define UNITS_PER_WORD 4
303
304 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
305 #define STACK_BOUNDARY 16
306 #define FUNCTION_BOUNDARY 16
307 #define EMPTY_FIELD_BOUNDARY 16
308 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */
309 #define PREFERRED_STACK_BOUNDARY \
310 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16)
311
312 /* No data type wants to be aligned rounder than this.
313 Most published ABIs say that ints should be aligned on 16-bit
314 boundaries, but CPUs with 32-bit busses get better performance
315 aligned on 32-bit boundaries. */
316 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
317
318 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
319 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1
320
321 #define DWARF_CIE_DATA_ALIGNMENT -2
322
323 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
324
325 /* Define these to avoid dependence on meaning of `int'. */
326 #define WCHAR_TYPE "long int"
327 #define WCHAR_TYPE_SIZE 32
328
329 /* Maximum number of library IDs we permit with -mid-shared-library. */
330 #define MAX_LIBRARY_ID 255
331
332 \f
333 /* Standard register usage. */
334
335 /* For the m68k, we give the data registers numbers 0-7,
336 the address registers numbers 010-017 (8-15),
337 and the 68881 floating point registers numbers 020-027 (16-23).
338 We also have a fake `arg-pointer' register 030 (24) used for
339 register elimination. */
340 #define FIRST_PSEUDO_REGISTER 25
341
342 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
343 #define PIC_OFFSET_TABLE_REGNUM \
344 (!flag_pic ? INVALID_REGNUM \
345 : reload_completed ? REGNO (pic_offset_table_rtx) \
346 : PIC_REG)
347
348 /* 1 for registers that have pervasive standard uses
349 and are not available for the register allocator.
350 On the m68k, only the stack pointer is such.
351 Our fake arg-pointer is obviously fixed as well. */
352 #define FIXED_REGISTERS \
353 {/* Data registers. */ \
354 0, 0, 0, 0, 0, 0, 0, 0, \
355 \
356 /* Address registers. */ \
357 0, 0, 0, 0, 0, 0, 0, 1, \
358 \
359 /* Floating point registers \
360 (if available). */ \
361 0, 0, 0, 0, 0, 0, 0, 0, \
362 \
363 /* Arg pointer. */ \
364 1 }
365
366 /* 1 for registers not available across function calls.
367 These must include the FIXED_REGISTERS and also any
368 registers that can be used without being saved.
369 The latter must include the registers where values are returned
370 and the register where structure-value addresses are passed.
371 Aside from that, you can include as many other registers as you like. */
372 #define CALL_USED_REGISTERS \
373 {/* Data registers. */ \
374 1, 1, 0, 0, 0, 0, 0, 0, \
375 \
376 /* Address registers. */ \
377 1, 1, 0, 0, 0, 0, 0, 1, \
378 \
379 /* Floating point registers \
380 (if available). */ \
381 1, 1, 0, 0, 0, 0, 0, 0, \
382 \
383 /* Arg pointer. */ \
384 1 }
385
386 #define REG_ALLOC_ORDER \
387 { /* d0/d1/a0/a1 */ \
388 0, 1, 8, 9, \
389 /* d2-d7 */ \
390 2, 3, 4, 5, 6, 7, \
391 /* a2-a7/arg */ \
392 10, 11, 12, 13, 14, 15, 24, \
393 /* fp0-fp7 */ \
394 16, 17, 18, 19, 20, 21, 22, 23\
395 }
396
397
398 /* Make sure everything's fine if we *don't* have a given processor.
399 This assumes that putting a register in fixed_regs will keep the
400 compiler's mitts completely off it. We don't bother to zero it out
401 of register classes. */
402 #define CONDITIONAL_REGISTER_USAGE \
403 { \
404 int i; \
405 HARD_REG_SET x; \
406 if (!TARGET_HARD_FLOAT) \
407 { \
408 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
409 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
410 if (TEST_HARD_REG_BIT (x, i)) \
411 fixed_regs[i] = call_used_regs[i] = 1; \
412 } \
413 if (flag_pic) \
414 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; \
415 }
416
417 /* On the m68k, ordinary registers hold 32 bits worth;
418 for the 68881 registers, a single register is always enough for
419 anything that can be stored in them at all. */
420 #define HARD_REGNO_NREGS(REGNO, MODE) \
421 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
422 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
423
424 /* A C expression that is nonzero if hard register NEW_REG can be
425 considered for use as a rename register for OLD_REG register. */
426
427 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
428 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
429
430 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
431 m68k_regno_mode_ok ((REGNO), (MODE))
432
433 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
434 m68k_secondary_reload_class (CLASS, MODE, X)
435
436 #define MODES_TIEABLE_P(MODE1, MODE2) \
437 (! TARGET_HARD_FLOAT \
438 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
439 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
440 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
441 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
442
443 /* Specify the registers used for certain standard purposes.
444 The values of these macros are register numbers. */
445
446 #define STACK_POINTER_REGNUM SP_REG
447
448 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
449 ABI uses %a6 for shared library calls, therefore the frame
450 pointer is shifted to %a5 on this target. */
451 #define FRAME_POINTER_REGNUM A6_REG
452
453 #define FRAME_POINTER_REQUIRED 0
454
455 /* Base register for access to arguments of the function.
456 * This isn't a hardware register. It will be eliminated to the
457 * stack pointer or frame pointer.
458 */
459 #define ARG_POINTER_REGNUM 24
460
461 #define STATIC_CHAIN_REGNUM A0_REG
462 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
463
464 /* Register in which address to store a structure value
465 is passed to a function. */
466 #define M68K_STRUCT_VALUE_REGNUM A1_REG
467
468 \f
469
470 /* The m68k has three kinds of registers, so eight classes would be
471 a complete set. One of them is not needed. */
472 enum reg_class {
473 NO_REGS, DATA_REGS,
474 ADDR_REGS, FP_REGS,
475 GENERAL_REGS, DATA_OR_FP_REGS,
476 ADDR_OR_FP_REGS, ALL_REGS,
477 LIM_REG_CLASSES };
478
479 #define N_REG_CLASSES (int) LIM_REG_CLASSES
480
481 #define REG_CLASS_NAMES \
482 { "NO_REGS", "DATA_REGS", \
483 "ADDR_REGS", "FP_REGS", \
484 "GENERAL_REGS", "DATA_OR_FP_REGS", \
485 "ADDR_OR_FP_REGS", "ALL_REGS" }
486
487 #define REG_CLASS_CONTENTS \
488 { \
489 {0x00000000}, /* NO_REGS */ \
490 {0x000000ff}, /* DATA_REGS */ \
491 {0x0100ff00}, /* ADDR_REGS */ \
492 {0x00ff0000}, /* FP_REGS */ \
493 {0x0100ffff}, /* GENERAL_REGS */ \
494 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
495 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
496 {0x01ffffff}, /* ALL_REGS */ \
497 }
498
499 extern enum reg_class regno_reg_class[];
500 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
501 #define INDEX_REG_CLASS GENERAL_REGS
502 #define BASE_REG_CLASS ADDR_REGS
503
504 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
505 m68k_preferred_reload_class (X, CLASS)
506
507 /* On the m68k, this is the size of MODE in words,
508 except in the FP regs, where a single reg is always enough. */
509 #define CLASS_MAX_NREGS(CLASS, MODE) \
510 ((CLASS) == FP_REGS ? 1 \
511 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
512
513 /* Moves between fp regs and other regs are two insns. */
514 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
515 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
516 \f
517 /* Stack layout; function entry, exit and calling. */
518
519 #define STACK_GROWS_DOWNWARD 1
520 #define FRAME_GROWS_DOWNWARD 1
521 #define STARTING_FRAME_OFFSET 0
522
523 /* On the 680x0, sp@- in a byte insn really pushes a word.
524 On the ColdFire, sp@- in a byte insn pushes just a byte. */
525 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
526
527 #define FIRST_PARM_OFFSET(FNDECL) 8
528
529 /* On the 68000, the RTS insn cannot pop anything.
530 On the 68010, the RTD insn may be used to pop them if the number
531 of args is fixed, but if the number is variable then the caller
532 must pop them all. RTD can't be used for library calls now
533 because the library is compiled with the Unix compiler.
534 Use of RTD is a selectable option, since it is incompatible with
535 standard Unix calling sequences. If the option is not selected,
536 the caller must always pop the args. */
537 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
538 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
539 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
540 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
541 == void_type_node))) \
542 ? (SIZE) : 0)
543
544 /* On the m68k the return value defaults to D0. */
545 #define FUNCTION_VALUE(VALTYPE, FUNC) \
546 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG)
547
548 /* On the m68k the return value defaults to D0. */
549 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG)
550
551 /* On the m68k, D0 is usually the only register used. */
552 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG)
553
554 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
555 more than one register.
556 XXX This macro is m68k specific and used only for m68kemb.h. */
557 #define NEEDS_UNTYPED_CALL 0
558
559 /* On the m68k, all arguments are usually pushed on the stack. */
560 #define FUNCTION_ARG_REGNO_P(N) 0
561 \f
562 /* On the m68k, this is a single integer, which is a number of bytes
563 of arguments scanned so far. */
564 #define CUMULATIVE_ARGS int
565
566 /* On the m68k, the offset starts at 0. */
567 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
568 ((CUM) = 0)
569
570 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
571 ((CUM) += ((MODE) != BLKmode \
572 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
573 : (int_size_in_bytes (TYPE) + 3) & ~3))
574
575 /* On the m68k all args are always pushed. */
576 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
577
578 #define FUNCTION_PROFILER(FILE, LABELNO) \
579 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
580
581 #define EXIT_IGNORE_STACK 1
582
583 /* Output assembler code for a block containing the constant parts
584 of a trampoline, leaving space for the variable parts.
585
586 On the m68k, the trampoline looks like this:
587 movl #STATIC,a0
588 jmp FUNCTION
589
590 WARNING: Targets that may run on 68040+ cpus must arrange for
591 the instruction cache to be flushed. Previous incarnations of
592 the m68k trampoline code attempted to get around this by either
593 using an out-of-line transfer function or pc-relative data, but
594 the fact remains that the code to jump to the transfer function
595 or the code to load the pc-relative data needs to be flushed
596 just as much as the "variable" portion of the trampoline.
597 Recognizing that a cache flush is going to be required anyway,
598 dispense with such notions and build a smaller trampoline.
599
600 Since more instructions are required to move a template into
601 place than to create it on the spot, don't use a template. */
602
603 #define TRAMPOLINE_SIZE 12
604 #define TRAMPOLINE_ALIGNMENT 16
605
606 /* Targets redefine this to invoke code to either flush the cache,
607 or enable stack execution (or both). */
608 #ifndef FINALIZE_TRAMPOLINE
609 #define FINALIZE_TRAMPOLINE(TRAMP)
610 #endif
611
612 /* We generate a two-instructions program at address TRAMP :
613 movea.l &CXT,%a0
614 jmp FNADDR */
615 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
616 { \
617 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \
618 GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \
619 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
620 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
621 GEN_INT(0x4EF9)); \
622 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
623 FINALIZE_TRAMPOLINE(TRAMP); \
624 }
625
626 /* This is the library routine that is used to transfer control from the
627 trampoline to the actual nested function. It is defined for backward
628 compatibility, for linking with object code that used the old trampoline
629 definition.
630
631 A colon is used with no explicit operands to cause the template string
632 to be scanned for %-constructs.
633
634 The function name __transfer_from_trampoline is not actually used.
635 The function definition just permits use of "asm with operands"
636 (though the operand list is empty). */
637 #define TRANSFER_FROM_TRAMPOLINE \
638 void \
639 __transfer_from_trampoline () \
640 { \
641 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
642 asm (GLOBAL_ASM_OP "___trampoline"); \
643 asm ("___trampoline:"); \
644 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
645 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
646 asm ("rts":); \
647 }
648 \f
649 /* There are two registers that can always be eliminated on the m68k.
650 The frame pointer and the arg pointer can be replaced by either the
651 hard frame pointer or to the stack pointer, depending upon the
652 circumstances. The hard frame pointer is not used before reload and
653 so it is not eligible for elimination. */
654 #define ELIMINABLE_REGS \
655 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
656 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
657 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
658
659 #define CAN_ELIMINATE(FROM, TO) \
660 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
661
662 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
663 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
664 \f
665 /* Addressing modes, and classification of registers for them. */
666
667 #define HAVE_POST_INCREMENT 1
668 #define HAVE_PRE_DECREMENT 1
669
670 /* Macros to check register numbers against specific register classes. */
671
672 /* True for data registers, D0 through D7. */
673 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7)
674
675 /* True for address registers, A0 through A7. */
676 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15)
677
678 /* True for integer registers, D0 through D7 and A0 through A7. */
679 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15)
680
681 /* True for floating point registers, FP0 through FP7. */
682 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23)
683
684 #define REGNO_OK_FOR_INDEX_P(REGNO) \
685 (INT_REGNO_P (REGNO) \
686 || INT_REGNO_P (reg_renumber[REGNO]))
687
688 #define REGNO_OK_FOR_BASE_P(REGNO) \
689 (ADDRESS_REGNO_P (REGNO) \
690 || ADDRESS_REGNO_P (reg_renumber[REGNO]))
691
692 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
693 (INT_REGNO_P (REGNO) \
694 || REGNO == ARG_POINTER_REGNUM \
695 || REGNO >= FIRST_PSEUDO_REGISTER)
696
697 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
698 (ADDRESS_REGNO_P (REGNO) \
699 || REGNO == ARG_POINTER_REGNUM \
700 || REGNO >= FIRST_PSEUDO_REGISTER)
701
702 /* Now macros that check whether X is a register and also,
703 strictly, whether it is in a specified class.
704
705 These macros are specific to the m68k, and may be used only
706 in code for printing assembler insns and in conditions for
707 define_optimization. */
708
709 /* 1 if X is a data register. */
710 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X)))
711
712 /* 1 if X is an fp register. */
713 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
714
715 /* 1 if X is an address register */
716 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X)))
717 \f
718 /* True if SYMBOL + OFFSET constants must refer to something within
719 SYMBOL's section. */
720 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
721 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
722 #endif
723
724 #define MAX_REGS_PER_ADDRESS 2
725
726 #define CONSTANT_ADDRESS_P(X) \
727 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
728 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
729 || GET_CODE (X) == HIGH) \
730 && LEGITIMATE_CONSTANT_P (X))
731
732 /* Nonzero if the constant value X is a legitimate general operand.
733 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
734 #define LEGITIMATE_CONSTANT_P(X) \
735 (GET_MODE (X) != XFmode \
736 && !m68k_illegitimate_symbolic_constant_p (X))
737
738 #ifndef REG_OK_STRICT
739 #define REG_STRICT_P 0
740 #else
741 #define REG_STRICT_P 1
742 #endif
743
744 #define LEGITIMATE_PIC_OPERAND_P(X) \
745 (!symbolic_operand (X, VOIDmode) \
746 || (TARGET_PCREL && REG_STRICT_P))
747
748 #define REG_OK_FOR_BASE_P(X) \
749 m68k_legitimate_base_reg_p (X, REG_STRICT_P)
750
751 #define REG_OK_FOR_INDEX_P(X) \
752 m68k_legitimate_index_reg_p (X, REG_STRICT_P)
753
754 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
755 do \
756 { \
757 if (m68k_legitimate_address_p (MODE, X, REG_STRICT_P)) \
758 goto ADDR; \
759 } \
760 while (0)
761
762 /* This address is OK as it stands. */
763 #define PIC_CASE_VECTOR_ADDRESS(index) index
764 \f
765 /* For the 68000, we handle X+REG by loading X into a register R and
766 using R+REG. R will go in an address reg and indexing will be used.
767 However, if REG is a broken-out memory address or multiplication,
768 nothing needs to be done because REG can certainly go in an address reg. */
769 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
770 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
771 { register int ch = (X) != (OLDX); \
772 if (GET_CODE (X) == PLUS) \
773 { int copied = 0; \
774 if (GET_CODE (XEXP (X, 0)) == MULT) \
775 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
776 if (GET_CODE (XEXP (X, 1)) == MULT) \
777 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
778 if (ch && GET_CODE (XEXP (X, 1)) == REG \
779 && GET_CODE (XEXP (X, 0)) == REG) \
780 { if (TARGET_COLDFIRE_FPU \
781 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
782 { COPY_ONCE (X); X = force_operand (X, 0);} \
783 goto WIN; } \
784 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
785 if (GET_CODE (XEXP (X, 0)) == REG \
786 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
787 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
788 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
789 { register rtx temp = gen_reg_rtx (Pmode); \
790 register rtx val = force_operand (XEXP (X, 1), 0); \
791 emit_move_insn (temp, val); \
792 COPY_ONCE (X); \
793 XEXP (X, 1) = temp; \
794 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
795 && GET_CODE (XEXP (X, 0)) == REG) \
796 X = force_operand (X, 0); \
797 goto WIN; } \
798 else if (GET_CODE (XEXP (X, 1)) == REG \
799 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
800 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
801 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
802 { register rtx temp = gen_reg_rtx (Pmode); \
803 register rtx val = force_operand (XEXP (X, 0), 0); \
804 emit_move_insn (temp, val); \
805 COPY_ONCE (X); \
806 XEXP (X, 0) = temp; \
807 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
808 && GET_CODE (XEXP (X, 1)) == REG) \
809 X = force_operand (X, 0); \
810 goto WIN; }}}
811
812 /* On the 68000, only predecrement and postincrement address depend thus
813 (the amount of decrement or increment being the length of the operand).
814 These are now treated generically in recog.c. */
815 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
816 \f
817 #define CASE_VECTOR_MODE HImode
818 #define CASE_VECTOR_PC_RELATIVE 1
819
820 #define DEFAULT_SIGNED_CHAR 1
821 #define MOVE_MAX 4
822 #define SLOW_BYTE_ACCESS 0
823
824 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
825
826 /* The ColdFire FF1 instruction returns 32 for zero. */
827 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
828
829 #define STORE_FLAG_VALUE (-1)
830
831 #define Pmode SImode
832 #define FUNCTION_MODE QImode
833
834 \f
835 /* Tell final.c how to eliminate redundant test instructions. */
836
837 /* Here we define machine-dependent flags and fields in cc_status
838 (see `conditions.h'). */
839
840 /* Set if the cc value is actually in the 68881, so a floating point
841 conditional branch must be output. */
842 #define CC_IN_68881 04000
843
844 /* On the 68000, all the insns to store in an address register fail to
845 set the cc's. However, in some cases these instructions can make it
846 possibly invalid to use the saved cc's. In those cases we clear out
847 some or all of the saved cc's so they won't be used. */
848 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
849
850 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
851 do { if (cc_prev_status.flags & CC_IN_68881) \
852 return FLOAT; \
853 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
854 return NO_OV; \
855 return NORMAL; } while (0)
856 \f
857 /* Control the assembler format that we output. */
858
859 #define ASM_APP_ON "#APP\n"
860 #define ASM_APP_OFF "#NO_APP\n"
861 #define TEXT_SECTION_ASM_OP "\t.text"
862 #define DATA_SECTION_ASM_OP "\t.data"
863 #define GLOBAL_ASM_OP "\t.globl\t"
864 #define REGISTER_PREFIX ""
865 #define LOCAL_LABEL_PREFIX ""
866 #define USER_LABEL_PREFIX "_"
867 #define IMMEDIATE_PREFIX "#"
868
869 #define REGISTER_NAMES \
870 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
871 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
872 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
873 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
874 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
875 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
876 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
877 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
878 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
879
880 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
881
882 /* Return a register name by index, handling %fp nicely.
883 We don't replace %fp for targets that don't map it to %a6
884 since it may confuse GAS. */
885 #define M68K_REGNAME(r) ( \
886 ((FRAME_POINTER_REGNUM == A6_REG) \
887 && ((r) == FRAME_POINTER_REGNUM) \
888 && frame_pointer_needed) ? \
889 M68K_FP_REG_NAME : reg_names[(r)])
890
891 /* On the Sun-3, the floating point registers have numbers
892 18 to 25, not 16 to 23 as they do in the compiler. */
893 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
894
895 /* Before the prologue, RA is at 0(%sp). */
896 #define INCOMING_RETURN_ADDR_RTX \
897 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
898
899 /* After the prologue, RA is at 4(AP) in the current frame. */
900 #define RETURN_ADDR_RTX(COUNT, FRAME) \
901 ((COUNT) == 0 \
902 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
903 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
904
905 /* We must not use the DBX register numbers for the DWARF 2 CFA column
906 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
907 Instead use the identity mapping. */
908 #define DWARF_FRAME_REGNUM(REG) \
909 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM)
910
911 /* The return column was originally 24, but gcc used 25 for a while too.
912 Define both registers 24 and 25 as Pmode ones and use 24 in our own
913 unwind information. */
914 #define DWARF_FRAME_REGISTERS 25
915 #define DWARF_FRAME_RETURN_COLUMN 24
916 #define DWARF_ALT_FRAME_RETURN_COLUMN 25
917
918 /* Before the prologue, the top of the frame is at 4(%sp). */
919 #define INCOMING_FRAME_SP_OFFSET 4
920
921 /* All registers are live on exit from an interrupt routine. */
922 #define EPILOGUE_USES(REGNO) \
923 (reload_completed \
924 && (m68k_get_function_kind (current_function_decl) \
925 == m68k_fk_interrupt_handler))
926
927 /* Describe how we implement __builtin_eh_return. */
928 #define EH_RETURN_DATA_REGNO(N) \
929 ((N) < 2 ? (N) : INVALID_REGNUM)
930 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG)
931 #define EH_RETURN_HANDLER_RTX \
932 gen_rtx_MEM (Pmode, \
933 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
934 plus_constant (EH_RETURN_STACKADJ_RTX, \
935 UNITS_PER_WORD)))
936
937 /* Select a format to encode pointers in exception handling data. CODE
938 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
939 true if the symbol may be affected by dynamic relocations.
940
941 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
942 a read-only text segment without imposing a fixed gap between the
943 text and data segments. As a result, the text segment cannot refer
944 to anything in the data segment, even in PC-relative form. Because
945 .eh_frame refers to both code and data, it follows that .eh_frame
946 must be in the data segment itself, and that the offset between
947 .eh_frame and code will not be a link-time constant.
948
949 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
950 | DW_EH_PE_indirect for all code references. However, gcc currently
951 handles indirect references using a per-TU constant pool. This means
952 that if a function and its eh_frame are removed by the linker, the
953 eh_frame's indirect references to the removed function will not be
954 removed, leading to an unresolved symbol error.
955
956 It isn't clear that any -msep-data or -mid-shared-library target
957 would benefit from a read-only .eh_frame anyway. In particular,
958 no known target that supports these options has a feature like
959 PT_GNU_RELRO. Without any such feature to motivate them, indirect
960 references would be unnecessary bloat, so we simply use an absolute
961 pointer for code and global references. We still use pc-relative
962 references to data, as this avoids a relocation. */
963 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
964 (flag_pic \
965 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \
966 && ((GLOBAL) || (CODE))) \
967 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
968 : DW_EH_PE_absptr)
969
970 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
971 asm_fprintf (FILE, "%U%s", NAME)
972
973 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
974 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
975
976 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
977 asm_fprintf (FILE, (MOTOROLA \
978 ? "\tmove.l %s,-(%Rsp)\n" \
979 : "\tmovel %s,%Rsp@-\n"), \
980 reg_names[REGNO])
981
982 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
983 asm_fprintf (FILE, (MOTOROLA \
984 ? "\tmove.l (%Rsp)+,%s\n" \
985 : "\tmovel %Rsp@+,%s\n"), \
986 reg_names[REGNO])
987
988 /* The m68k does not use absolute case-vectors, but we must define this macro
989 anyway. */
990 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
991 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
992
993 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
994 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
995
996 /* We don't have a way to align to more than a two-byte boundary, so do the
997 best we can and don't complain. */
998 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
999 if ((LOG) >= 1) \
1000 fprintf (FILE, "\t.even\n");
1001
1002 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1003 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1004
1005 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1006 ( fputs (".comm ", (FILE)), \
1007 assemble_name ((FILE), (NAME)), \
1008 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1009
1010 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1011 ( fputs (".lcomm ", (FILE)), \
1012 assemble_name ((FILE), (NAME)), \
1013 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1014
1015 /* Output a float value (represented as a C double) as an immediate operand.
1016 This macro is m68k-specific. */
1017 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1018 do { \
1019 if (CODE == 'f') \
1020 { \
1021 char dstr[30]; \
1022 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1023 asm_fprintf ((FILE), "%I0r%s", dstr); \
1024 } \
1025 else \
1026 { \
1027 long l; \
1028 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1029 asm_fprintf ((FILE), "%I0x%lx", l); \
1030 } \
1031 } while (0)
1032
1033 /* Output a double value (represented as a C double) as an immediate operand.
1034 This macro is m68k-specific. */
1035 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1036 do { char dstr[30]; \
1037 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1038 asm_fprintf (FILE, "%I0r%s", dstr); \
1039 } while (0)
1040
1041 /* Note, long double immediate operands are not actually
1042 generated by m68k.md. */
1043 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1044 do { char dstr[30]; \
1045 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1046 asm_fprintf (FILE, "%I0r%s", dstr); \
1047 } while (0)
1048
1049 /* On the 68000, we use several CODE characters:
1050 '.' for dot needed in Motorola-style opcode names.
1051 '-' for an operand pushing on the stack:
1052 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1053 '+' for an operand pushing on the stack:
1054 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1055 '@' for a reference to the top word on the stack:
1056 sp@, (sp) or (%sp) depending on the style of syntax.
1057 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1058 but & in SGS syntax).
1059 '!' for the fpcr register (used in some float-to-fixed conversions).
1060 '$' for the letter `s' in an op code, but only on the 68040.
1061 '&' for the letter `d' in an op code, but only on the 68040.
1062 '/' for register prefix needed by longlong.h.
1063 '?' for m68k_library_id_string
1064
1065 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1066 'd' to force memory addressing to be absolute, not relative.
1067 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1068 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1069 or print pair of registers as rx:ry. */
1070
1071 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1072 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1073 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1074 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?')
1075
1076
1077 /* See m68k.c for the m68k specific codes. */
1078 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1079
1080 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1081
1082 /* Values used in the MICROARCH argument to M68K_DEVICE. */
1083 enum uarch_type
1084 {
1085 u68000,
1086 u68010,
1087 u68020,
1088 u68020_40,
1089 u68020_60,
1090 u68030,
1091 u68040,
1092 u68060,
1093 ucpu32,
1094 ucfv1,
1095 ucfv2,
1096 ucfv3,
1097 ucfv4,
1098 ucfv4e,
1099 ucfv5,
1100 unk_arch
1101 };
1102
1103 /* An enumeration of all supported target devices. */
1104 enum target_device
1105 {
1106 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
1107 ENUM_VALUE,
1108 #include "m68k-devices.def"
1109 #undef M68K_DEVICE
1110 unk_device
1111 };
1112
1113 enum fpu_type
1114 {
1115 FPUTYPE_NONE,
1116 FPUTYPE_68881,
1117 FPUTYPE_COLDFIRE
1118 };
1119
1120 enum m68k_function_kind
1121 {
1122 m68k_fk_normal_function,
1123 m68k_fk_interrupt_handler,
1124 m68k_fk_interrupt_thread
1125 };
1126
1127 /* Variables in m68k.c; see there for details. */
1128 extern const char *m68k_library_id_string;
1129 extern int m68k_last_compare_had_fp_operands;
1130 extern enum target_device m68k_cpu;
1131 extern enum uarch_type m68k_tune;
1132 extern enum fpu_type m68k_fpu;
1133 extern unsigned int m68k_cpu_flags;
1134 extern const char *m68k_symbolic_call;
1135 extern const char *m68k_symbolic_jump;
1136
1137 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR,
1138 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P };
1139
1140 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
1141
1142 /* ??? HOST_WIDE_INT is not being defined for auto-generated files.
1143 Workaround that. */
1144 #ifdef HOST_WIDE_INT
1145 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ }
1146 M68K_CONST_METHOD;
1147
1148 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT);
1149 #endif
1150
1151 extern void m68k_emit_move_double (rtx [2]);
1152
1153 extern int m68k_sched_address_bypass_p (rtx, rtx);
1154 extern int m68k_sched_indexed_address_bypass_p (rtx, rtx);
1155
1156 #define CPU_UNITS_QUERY 1
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