1 /* ZPU emulation library
3 * (c) 2011, Martin Strubel <hackfin@section5.ch>
5 * Limited functionality: Only one core in chain supported.
9 // These headers must be implemented by the JTAG interface to your
12 #include "jtag_intern.h"
16 #include "zpu-opcodes.h"
59 void select_dr(CpuContext
*c
, uint8_t dr
)
61 jtag_goto_state(c
->jtag
, s_jtag_shift_ir
);
62 reg_set(&ir_r
, 0, IRSIZE
, dr
);
63 shift_generic(c
->jtag
, &ir_r
, NULL
, ir_r
.nbits
, UPDATE
);
66 void shiftout32(CpuContext
*c
, REGISTER
*r
, int mode
)
69 jtag_goto_state(c
->jtag
, s_jtag_shift_dr
);
70 shift_generic(c
->jtag
, &data_r
, &data_r
, data_r
.nbits
, mode
);
71 *r
= reg_get(&data_r
, 0, 32);
74 void shiftin16(CpuContext
*c
, REGISTER r
, int mode
)
76 jtag_goto_state(c
->jtag
, s_jtag_shift_dr
);
77 reg_set(&ctrl_r
, 0, 16, r
);
78 shift_generic(c
->jtag
, &ctrl_r
, NULL
, ctrl_r
.nbits
, mode
);
81 void shiftout16(CpuContext
*c
, REGISTER
*r
, int mode
)
83 jtag_goto_state(c
->jtag
, s_jtag_shift_dr
);
84 shift_generic(c
->jtag
, &ctrl_r
, &ctrl_r
, ctrl_r
.nbits
, mode
);
85 *r
= reg_get(&ctrl_r
, 0, 16);
91 void push_opcode(CpuContext
*c
, uint8_t opcode
, int mode
)
93 opcode_r
.data
[0] = opcode
;
94 jtag_goto_state(c
->jtag
, s_jtag_shift_dr
);
95 shift_generic(c
->jtag
, &opcode_r
, NULL
, opcode_r
.nbits
, mode
);
100 void push_val16(CpuContext
*c
, uint16_t val
)
103 push_opcode(c
, OPCODE_IM
| ((val
>> i
) & 0x7f), EXEC
); i
-= 7;
104 push_opcode(c
, OPCODE_IM
| ((val
>> i
) & 0x7f), EXEC
); i
-= 7;
105 push_opcode(c
, OPCODE_IM
| ((val
>> i
) & 0x7f), EXEC
);
106 push_opcode(c
, OPCODE_NOP
, EXEC
);
111 void push_val32(CpuContext
*c
, uint32_t val
)
114 push_opcode(c
, OPCODE_IM
| ((val
>> i
) & 0x7f), EXEC
); i
-= 7;
115 push_opcode(c
, OPCODE_IM
| ((val
>> i
) & 0x7f), EXEC
); i
-= 7;
116 push_opcode(c
, OPCODE_IM
| ((val
>> i
) & 0x7f), EXEC
); i
-= 7;
117 push_opcode(c
, OPCODE_IM
| ((val
>> i
) & 0x7f), EXEC
); i
-= 7;
118 push_opcode(c
, OPCODE_IM
| ((val
>> i
) & 0x7f), EXEC
);
119 push_opcode(c
, OPCODE_NOP
, EXEC
);
123 uint32_t mem_read32(CpuContext
*c
, uint32_t addr
)
126 int q
= jtag_queue(c
->jtag
, 1);
127 select_dr(c
, TAP_EMUIR
);
128 push_opcode(c
, OPCODE_PUSHSP
, EXEC
);
130 push_opcode(c
, OPCODE_LOAD
, EXEC
);
131 push_opcode(c
, OPCODE_NOP
, EXEC
);
132 select_dr(c
, TAP_EMUDATA
);
133 shiftout32(c
, &r
, UPDATE
); // Execute Stack fixup
134 select_dr(c
, TAP_EMUIR
);
135 push_opcode(c
, OPCODE_LOADSP
| (LOADSP_INV
^ 0x01), EXEC
);
136 push_opcode(c
, OPCODE_POPSP
, EXEC
);
137 push_opcode(c
, OPCODE_NOP
, EXEC
);
138 jtag_queue(c
->jtag
, q
);
142 // Little read cache:
146 } g_cache
= { 0xffffffff, 0 };
149 uint32_t mem_read32_cached(CpuContext
*c
, ADDR a
)
151 if (a
!= g_cache
.addr
) {
152 g_cache
.val
= mem_read32(c
, a
);
154 // printf("Read %08x\n", g_cache.val);
159 uint8_t mem_read8(CpuContext
*c
, ADDR a
)
162 int shift
= (3 - (a
& 0x3)) << 3;
164 // printf("shift: %d\n", shift);
165 v
= mem_read32_cached(c
, a
) >> shift
;
169 uint16_t mem_read16(CpuContext
*c
, ADDR a
)
172 int shift
= (2 - (a
& 0x2)) << 3;
174 // printf("shift: %d\n", shift);
175 v
= mem_read32_cached(c
, a
) >> shift
;
179 void mem_write32(CpuContext
*c
, uint32_t addr
, uint32_t val
)
181 // Invalidate cache, when we're writing to the same addr:
182 if (g_cache
.addr
== (addr
)) {
183 g_cache
.addr
= 0xffffffff;
185 select_dr(c
, TAP_EMUIR
);
186 push_opcode(c
, OPCODE_PUSHSP
, EXEC
);
188 push_val32(c
, addr
); // Address
189 push_opcode(c
, OPCODE_STORE
, EXEC
);
190 push_opcode(c
, OPCODE_LOADSP
| (LOADSP_INV
^ 0x00), EXEC
);
191 push_opcode(c
, OPCODE_POPSP
, EXEC
);
192 push_opcode(c
, OPCODE_NOP
, UPDATE
);
196 void mem_write16(CpuContext
*c
, uint32_t addr
, uint16_t val
)
198 int shift
= (2 - (addr
& 0x2)) << 3;
202 v
= mem_read32_cached(c
, addr
);
204 v
= (v
& ~(0xffff << shift
)) | (val
<< shift
);
205 mem_write32(c
, addr
, v
);
208 void mem_write8(CpuContext
*c
, uint32_t addr
, uint8_t val
)
210 int shift
= (3 - (addr
& 0x3)) << 3;
214 v
= mem_read32_cached(c
, addr
);
216 v
= (v
& ~(0xff << shift
)) | (val
<< shift
);
217 mem_write32(c
, addr
, v
);
220 int enter_emulation(CpuContext
*c
)
224 g_cache
.addr
= 0xffffffff; // Invalidate cache
226 // puts(">>> Enter emulation");
227 select_dr(c
, TAP_EMUCTRL
);
229 shiftin16(c
, r
, UPDATE
);
234 int leave_emulation(CpuContext
*c
)
238 // Turn off emulation bit
239 select_dr(c
, TAP_EMUCTRL
);
240 shiftin16(c
, 0, UPDATE
);
242 // Run some emulated opcodes:
243 // Return from emulation:
244 select_dr(c
, TAP_EMUIR
);
245 push_opcode(c
, OPCODE_EMULEAVE
, EXEC
);
249 ////////////////////////////////////////////////////////////////////////////
252 int zpu_emuinit(CpuContext
*c
, CONTROLLER jtag
)
258 int zpu_getid(CpuContext
*c
, uint32_t *code
)
260 select_dr(c
, TAP_IDCODE
);
261 shiftout32(c
, code
, UPDATE
);
265 int zpu_resume(CpuContext
*c
, int step
)
269 select_dr(c
, TAP_EMUCTRL
);
270 shiftin16(c
, EMUREQ
, UPDATE
);
271 select_dr(c
, TAP_EMUIR
);
272 push_opcode(c
, OPCODE_EMULEAVE
, EXEC
);
279 int zpu_emulation(CpuContext
*c
, int which
)
281 // FIXME: for multicore, this needs to change.
291 int zpu_state(CpuContext
*c
, uint16_t *state
)
296 select_dr(c
, TAP_EMUSTAT
);
297 shiftout16(c
, &r
, UPDATE
);
302 int zpu_reset(CpuContext
*c
, int mode
)
304 // TODO: Implement system control register on zealot
308 int zpu_setreg(CpuContext
*c
, int regno
, REGISTER val
)
312 select_dr(c
, TAP_EMUIR
);
314 push_opcode(c
, OPCODE_POPPC
, EXEC
);
317 select_dr(c
, TAP_EMUIR
);
319 push_opcode(c
, OPCODE_POPSP
, EXEC
);
326 int zpu_getreg(CpuContext
*c
, int regno
, REGISTER
*val
)
329 int q
= jtag_queue(c
->jtag
, 1);
332 // XXX needed to update dbg_o.<signal>:
333 select_dr(c
, TAP_EMUIR
); // XXX
334 push_opcode(c
, OPCODE_NOP
, EXEC
); // XXX
335 select_dr(c
, TAP_DBGPC
);
336 shiftout32(c
, &r
, UPDATE
);
339 select_dr(c
, TAP_EMUIR
);
340 push_opcode(c
, OPCODE_PUSHSP
, EXEC
);
341 // XXX needed to update dbg_o.<signal>:
342 push_opcode(c
, OPCODE_NOP
, EXEC
); // XXX
343 push_opcode(c
, OPCODE_POPSP
, UPDATE
); // queue, exec later
344 select_dr(c
, TAP_EMUDATA
);
345 shiftout32(c
, &r
, EXEC
); // (here)
350 jtag_queue(c
->jtag
, q
);
354 void zpu_dumpstat(CpuContext
*c
)
358 select_dr(c
, TAP_EMUSTAT
);
359 shiftout16(c
, &r
, UPDATE
);
360 printf("EMUSTAT: %04x -", r
& 0xffff);
362 if (r
& ZPU_IDIM
) printf(" [IDIM]");
363 if (r
& ZPU_INRESET
) printf(" [RESET]");
364 if (r
& ZPU_BREAK
) printf(" [BREAK]");
365 if (r
& EMUACK
) printf(" [EMUACK]");
366 if (r
& EMURDY
) printf(" [EMURDY]");
367 if (r
& ZPU_MEMBUSY
) printf(" [MEM_BUSY]");
370 select_dr(c
, TAP_COUNT1
);
371 shiftout32(c
, &r
, UPDATE
);
372 printf("COUNT1: %012d\n", r
);
373 select_dr(c
, TAP_COUNT2
);
374 shiftout16(c
, &r
, UPDATE
);
375 printf("COUNT2: %08d\n", r
);
378 int guess_access(ADDR addr
, unsigned int *count
)
381 // I/O space wants to be addressed long word wise:
382 if (addr
>= 0x80080000 && *count
== 4) {
386 // if we have even addresses and even count, we can
387 // use word size transfers instead of byte wise.
390 switch (*count
% 4) {
405 if (*count
% 2 == 0) {
419 int zpu_mem_read(CpuContext
*c
, ADDR addr
, unsigned int count
,
424 int q
= jtag_queue(c
->jtag
, 1);
426 sz
= guess_access(addr
, &count
);
431 *buf
++ = mem_read8(c
, addr
++);
436 v
= mem_read16(c
, addr
); addr
+= 2;
444 v
= mem_read32(c
, addr
); addr
+= 4;
454 jtag_queue(c
->jtag
, q
);
458 int zpu_mem_write(CpuContext
*c
, ADDR addr
, unsigned int count
,
459 const unsigned char *buf
)
463 int q
= jtag_queue(c
->jtag
, 1);
465 sz
= guess_access(addr
, &count
);
469 // XXX: Could be optimized further
472 mem_write8(c
, addr
, v
); addr
++;
477 v
= (buf
[0] << 8) | buf
[1];
478 mem_write16(c
, addr
, v
);
484 v
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
485 mem_write32(c
, addr
, v
);
491 jtag_queue(c
->jtag
, q
);