| blob | 751d825334acfdc2ef4887e061af9d9df74e03bf |
1 ------------------------------------------------------------------------------\r
2 ---- ----\r
3 ---- ZPU Package ----\r
4 ---- ----\r
5 ---- http://www.opencores.org/ ----\r
6 ---- ----\r
7 ---- Description: ----\r
8 ---- ZPU is a 32 bits small stack cpu. This is the package. ----\r
9 ---- ----\r
10 ---- To Do: ----\r
11 ---- - ----\r
12 ---- ----\r
13 ---- Author: ----\r
14 ---- - Øyvind Harboe, oyvind.harboe zylin.com ----\r
15 ---- - Salvador E. Tropea, salvador inti.gob.ar ----\r
16 ---- ----\r
17 ------------------------------------------------------------------------------\r
18 ---- ----\r
19 ---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----\r
20 ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----\r
21 ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----\r
22 ---- ----\r
23 ---- Distributed under the BSD license ----\r
24 ---- ----\r
25 ------------------------------------------------------------------------------\r
26 ---- ----\r
27 ---- Design unit: zpupkg, UART (Package) ----\r
28 ---- File name: zpu_medium.vhdl ----\r
29 ---- Note: None ----\r
30 ---- Limitations: None known ----\r
31 ---- Errors: None known ----\r
32 ---- Library: zpu ----\r
33 ---- Dependencies: IEEE.std_logic_1164 ----\r
34 ---- IEEE.numeric_std ----\r
35 ---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----\r
36 ---- Language: VHDL ----\r
37 ---- Wishbone: No ----\r
38 ---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----\r
39 ---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----\r
40 ---- Text editor: SETEdit 0.5.x ----\r
41 ---- ----\r
42 ------------------------------------------------------------------------------\r
43 \r
44 library IEEE;\r
45 use IEEE.std_logic_1164.all;\r
46 use IEEE.numeric_std.all;\r
47 \r
48 package zpupkg is\r
49 constant OPCODE_W : integer:=8;\r
50 \r
51 -- Debug structure, currently only for the trace module\r
52 type zpu_dbgo_t is record\r
53 b_inst : std_logic;\r
54 opcode : unsigned(OPCODE_W-1 downto 0);\r
55 pc : unsigned(31 downto 0);\r
56 sp : unsigned(31 downto 0);\r
57 stk_a : unsigned(31 downto 0);\r
58 stk_b : unsigned(31 downto 0);\r
59 idim : std_logic; -- Debugging: idim flag\r
60 end record;\r
61 \r
62 component Trace is\r
63 generic(\r
64 LOG_FILE : string:="trace.txt"; -- Name of the trace file\r
65 ADDR_W : integer:=16; -- Address width\r
66 WORD_SIZE : integer:=32); -- 16/32\r
67 port(\r
68 clk_i : in std_logic;\r
69 dbg_i : in zpu_dbgo_t;\r
70 emu_i : in std_logic;\r
71 stop_i : in std_logic;\r
72 busy_i : in std_logic\r
73 );\r
74 end component Trace;\r
75 \r
76 component ZPUSmallCore is\r
77 generic(\r
78 WORD_SIZE : integer:=32; -- Data width 16/32\r
79 ADDR_W : integer:=16; -- Total address space width (incl. I/O)\r
80 MEM_W : integer:=15; -- Memory (prog+data+stack) width\r
81 D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits\r
82 port(\r
83 clk_i : in std_logic; -- System Clock\r
84 reset_i : in std_logic; -- Synchronous Reset\r
85 interrupt_i : in std_logic; -- Interrupt\r
86 \r
87 -- Emulation pins:\r
88 emureq_i : in std_logic;\r
89 emuexec_i : in std_logic; -- exec pulse. 1 clk cycle wide!\r
90 emuack_o : out std_logic;\r
91 emurdy_o : out std_logic;\r
92 pulse_o : out std_logic; -- Debug pulse for event counter\r
93 emuir : in std_logic_vector(OPCODE_W-1 downto 0);\r
94 \r
95 break_o : out std_logic; -- Breakpoint opcode executed\r
96 dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)\r
97 -- BRAM (text, data, bss and stack)\r
98 a_we_o : out std_logic; -- BRAM A port Write Enable\r
99 a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address\r
100 a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port\r
101 a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port\r
102 b_we_o : out std_logic; -- BRAM B port Write Enable\r
103 b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address\r
104 b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port\r
105 b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port\r
106 -- Memory mapped I/O\r
107 mem_busy_i : in std_logic;\r
108 data_i : in unsigned(WORD_SIZE-1 downto 0);\r
109 data_o : out unsigned(WORD_SIZE-1 downto 0);\r
110 addr_o : out unsigned(ADDR_W-1 downto 0);\r
111 write_en_o : out std_logic;\r
112 read_en_o : out std_logic);\r
113 end component ZPUSmallCore;\r
114 \r
115 component ZPUMediumCore is\r
116 generic(\r
117 WORD_SIZE : integer:=32; -- Data width 16/32\r
118 ADDR_W : integer:=16; -- Total address space width (incl. I/O)\r
119 MEM_W : integer:=15; -- Memory (prog+data+stack) width\r
120 D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits\r
121 MULT_PIPE : boolean:=false; -- Pipeline multiplication\r
122 BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)\r
123 ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd\r
124 ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub\r
125 ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel\r
126 ENA_LSHR : boolean:=true; -- lshiftright\r
127 ENA_IDLE : boolean:=false; -- Enable the enable_i input\r
128 FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states\r
129 port(\r
130 clk_i : in std_logic; -- CPU Clock\r
131 reset_i : in std_logic; -- Sync Reset\r
132 enable_i : in std_logic; -- Hold the CPU (after reset)\r
133 break_o : out std_logic; -- Break instruction executed\r
134 dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)\r
135 -- Memory interface\r
136 mem_busy_i : in std_logic; -- Memory is busy\r
137 data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem\r
138 data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem\r
139 addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address\r
140 write_en_o : out std_logic; -- Memory write enable\r
141 read_en_o : out std_logic); -- Memory read enable\r
142 end component ZPUMediumCore;\r
143 \r
144 component Timer is\r
145 port(\r
146 clk_i : in std_logic;\r
147 reset_i : in std_logic;\r
148 we_i : in std_logic;\r
149 data_i : in unsigned(31 downto 0);\r
150 addr_i : in unsigned(0 downto 0);\r
151 data_o : out unsigned(31 downto 0));\r
152 end component Timer;\r
153 \r
154 component ZPUPhiIO is\r
155 generic(\r
156 BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4\r
157 ENA_LOG : boolean:=true; -- Enable log\r
158 LOG_FILE : string:="log.txt"); -- Name for the log file\r
159 port(\r
160 clk_i : in std_logic; -- System Clock\r
161 reset_i : in std_logic; -- Synchronous Reset\r
162 busy_o : out std_logic; -- I/O is busy\r
163 we_i : in std_logic; -- Write Enable\r
164 re_i : in std_logic; -- Read Enable\r
165 data_i : in unsigned(31 downto 0);\r
166 data_o : out unsigned(31 downto 0);\r
167 addr_i : in unsigned(2 downto 0); -- Address bits 4-2\r
168 rs232_rx_i : in std_logic; -- UART Rx input\r
169 rs232_tx_o : out std_logic; -- UART Tx output\r
170 br_clk_i : in std_logic); -- UART base clock (enable)\r
171 end component ZPUPhiIO;\r
172 \r
173 -- Opcode decode constants\r
174 -- Note: these are the basic opcodes, always implemented using hardware.\r
175 constant OPCODE_IM : unsigned(7 downto 7):="1";\r
176 constant OPCODE_STORESP : unsigned(7 downto 5):="010";\r
177 constant OPCODE_LOADSP : unsigned(7 downto 5):="011";\r
178 constant OPCODE_EMULATE : unsigned(7 downto 5):="001";\r
179 constant OPCODE_ADDSP : unsigned(7 downto 4):="0001";\r
180 constant OPCODE_SHORT : unsigned(7 downto 4):="0000";\r
181 \r
182 constant OPCODE_BREAK : unsigned(3 downto 0):="0000";\r
183 constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";\r
184 constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010";\r
185 constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011";\r
186 \r
187 constant OPCODE_POPPC : unsigned(3 downto 0):="0100";\r
188 constant OPCODE_ADD : unsigned(3 downto 0):="0101";\r
189 constant OPCODE_AND : unsigned(3 downto 0):="0110";\r
190 constant OPCODE_OR : unsigned(3 downto 0):="0111";\r
191 \r
192 constant OPCODE_LOAD : unsigned(3 downto 0):="1000";\r
193 constant OPCODE_NOT : unsigned(3 downto 0):="1001";\r
194 constant OPCODE_FLIP : unsigned(3 downto 0):="1010";\r
195 constant OPCODE_NOP : unsigned(3 downto 0):="1011";\r
196 \r
197 constant OPCODE_STORE : unsigned(3 downto 0):="1100";\r
198 constant OPCODE_POPSP : unsigned(3 downto 0):="1101";\r
199 constant OPCODE_COMPARE : unsigned(3 downto 0):="1110";\r
200 constant OPCODE_POPINT : unsigned(3 downto 0):="1111";\r
201 \r
202 -- The following instructions are emulated in the small version and\r
203 -- implemented as hardware in the full version.\r
204 -- The constants correpond to the "emulated" instruction number.\r
205 \r
206 -- Enabled by the ENA_LEVEL0 generic:\r
207 constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6);\r
208 constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6);\r
209 constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6);\r
210 constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6);\r
211 -- Enabled by the ENA_LEVEL1 generic:\r
212 constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6);\r
213 constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6);\r
214 constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6);\r
215 constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6);\r
216 constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6);\r
217 constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6);\r
218 -- Enabled by the ENA_LEVEL2 generic:\r
219 constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6);\r
220 constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);\r
221 constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6);\r
222 constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6);\r
223 -- Enabled by the ENA_LSHR generic:\r
224 constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6);\r
225 -- The following opcodes are always emulated.\r
226 constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6);\r
227 constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6);\r
228 constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6);\r
229 constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6);\r
230 constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6);\r
231 constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6);\r
232 constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6);\r
233 constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6);\r
234 constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6);\r
235 constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6);\r
236 constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6);\r
237 constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6);\r
238 end package zpupkg;\r
239 \r
240 library IEEE;\r
241 use IEEE.std_logic_1164.all;\r
242 use IEEE.numeric_std.all;\r
243 \r
244 package UART is\r
245 ----------------------\r
246 -- Very simple UART --\r
247 ----------------------\r
248 component RxUnit is\r
249 port(\r
250 clk_i : in std_logic; -- System clock signal\r
251 reset_i : in std_logic; -- Reset input (sync)\r
252 enable_i : in std_logic; -- Enable input (rate*4)\r
253 read_i : in std_logic; -- Received Byte Read\r
254 rxd_i : in std_logic; -- RS-232 data input\r
255 rxav_o : out std_logic; -- Byte available\r
256 datao_o : out std_logic_vector(7 downto 0)); -- Byte received\r
257 end component RxUnit;\r
258 \r
259 component TxUnit is\r
260 port (\r
261 clk_i : in std_logic; -- Clock signal\r
262 reset_i : in std_logic; -- Reset input\r
263 enable_i : in std_logic; -- Enable input\r
264 load_i : in std_logic; -- Load input\r
265 txd_o : out std_logic; -- RS-232 data output\r
266 busy_o : out std_logic; -- Tx Busy\r
267 datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit\r
268 end component TxUnit;\r
269 \r
270 component BRGen is\r
271 generic(\r
272 COUNT : integer range 0 to 65535);-- Count revolution\r
273 port (\r
274 clk_i : in std_logic; -- Clock\r
275 reset_i : in std_logic; -- Reset input\r
276 ce_i : in std_logic; -- Chip Enable\r
277 o_o : out std_logic); -- Output\r
278 end component BRGen;\r
279 end package UART;\r
280 \r