zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl

   1 ------------------------------------------------------------------------------
   2 ----                                                                      ----
   3 ----  Testbench for the ZPU Medium connection to the FPGA                 ----
   4 ----                                                                      ----
   5 ----  http://www.opencores.org/                                           ----
   6 ----                                                                      ----
   7 ----  Description:                                                        ----
   8 ----  This is a testbench to simulate the ZPU_Med1 core as used in the    ----
   9 ----  dmips_med1.vhdl                                                     ----
  10 ----                                                                      ----
  11 ----  To Do:                                                              ----
  12 ----  -                                                                   ----
  13 ----                                                                      ----
  14 ----  Author:                                                             ----
  15 ----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
  16 ----                                                                      ----
  17 ------------------------------------------------------------------------------
  18 ----                                                                      ----
  19 ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
  20 ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
  21 ----                                                                      ----
  22 ---- Distributed under the BSD license                                    ----
  23 ----                                                                      ----
  24 ------------------------------------------------------------------------------
  25 ----                                                                      ----
  26 ---- Design unit:      DMIPS_Med1_TB(Behave) (Entity and architecture)    ----
  27 ---- File name:        dmips_med1_tb.vhdl                                 ----
  28 ---- Note:             None                                               ----
  29 ---- Limitations:      None known                                         ----
  30 ---- Errors:           None known                                         ----
  31 ---- Library:          work                                               ----
  32 ---- Dependencies:     IEEE.std_logic_1164                                ----
  33 ----                   IEEE.numeric_std                                   ----
  34 ----                   zpu.zpupkg                                         ----
  35 ----                   zpu.txt_util                                       ----
  36 ----                   work.zpu_memory                                    ----
  37 ---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
  38 ---- Language:         VHDL                                               ----
  39 ---- Wishbone:         No                                                 ----
  40 ---- Synthesis tools:  N/A                                                ----
  41 ---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
  42 ---- Text editor:      SETEdit 0.5.x                                      ----
  43 ----                                                                      ----
  44 ------------------------------------------------------------------------------
  45
  46 library IEEE;
  47 use IEEE.std_logic_1164.all;
  48 use IEEE.numeric_std.all;
  49
  50 library zpu;
  51 use zpu.zpupkg.all;
  52 use zpu.txt_util.all;
  53
  54 library work;
  55 use work.zpu_memory.all;
  56
  57 entity DMIPS_Med1_TB is
  58 end entity DMIPS_Med1_TB;
  59
  60 architecture Behave of DMIPS_Med1_TB is
  61    constant WORD_SIZE  : natural:=32; -- 32 bits data path
  62    constant ADDR_W     : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
  63    constant BRAM_W     : natural:=15; -- 15 bits RAM space=32 kB
  64    constant D_CARE_VAL : std_logic:='0'; -- Fill value
  65    constant CLK_FREQ   : positive:=50; -- 50 MHz clock
  66    constant CLK_S_PER  : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
  67    constant BRATE      : positive:=115200;
  68
  69    component ZPU_Med1 is
  70       generic(
  71          WORD_SIZE  : natural:=32;  -- 32 bits data path
  72          D_CARE_VAL : std_logic:='X'; -- Fill value
  73          CLK_FREQ   : positive:=50; -- 50 MHz clock
  74          BRATE      : positive:=9600; -- RS232 baudrate
  75          ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
  76          BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
  77       port(
  78          clk_i      : in  std_logic;  -- CPU clock
  79          rst_i      : in  std_logic;  -- Reset
  80          break_o    : out std_logic;  -- Break executed
  81          dbg_o      : out zpu_dbgo_t; -- Debug info
  82          rs232_tx_o : out std_logic;  -- UART Tx
  83          rs232_rx_i : in  std_logic); -- UART Rx
  84    end component ZPU_Med1;
  85
  86    signal clk          : std_logic;
  87    signal reset        : std_logic:='1';
  88
  89    signal break        : std_logic;
  90    signal dbg          : zpu_dbgo_t; -- Debug info
  91    signal rs232_tx     : std_logic;
  92    signal rs232_rx     : std_logic;
  93 begin
  94    zpu : ZPU_Med1
  95       generic map(
  96          WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
  97          CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
  98          BRAM_W => BRAM_W)
  99       port map(
 100          clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
 101          rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg);
 102
 103    trace_mod : Trace
 104       generic map(
 105          ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE,
 106          LOG_FILE => "dmips_med1.log")
 107       port map(
 108          clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0');
 109
 110    do_clock:
 111    process
 112    begin
 113       clk <= '0';
 114       wait for CLK_S_PER;
 115       clk <= '1';
 116       wait for CLK_S_PER;
 117       if break='1' then
 118          print("* Break asserted, end of test");
 119          wait;
 120       end if;
 121    end process do_clock;
 122
 123    do_reset:
 124    process
 125    begin
 126       wait until rising_edge(clk);
 127       reset <= '0';
 128    end process do_reset;
 129 end architecture Behave; -- Entity: DMIPS_Med1_TB