1 ------------------------------------------------------------------------------
3 ---- ZPU Small + PHI I/O + BRAM ----
5 ---- http://www.opencores.org/ ----
8 ---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ----
9 ---- small version, the PHI I/O basic layout and a program BRAM. ----
15 ---- - Salvador E. Tropea, salvador inti.gob.ar ----
17 ------------------------------------------------------------------------------
19 ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
20 ---- Copyright (c) 2008 Instituto Nacional de TecnologĂa Industrial ----
22 ---- Distributed under the BSD license ----
24 ------------------------------------------------------------------------------
26 ---- Design unit: ZPU_Small1(Structural) (Entity and architecture) ----
27 ---- File name: zpu_small1.vhdl ----
29 ---- Limitations: None known ----
30 ---- Errors: None known ----
31 ---- Library: work ----
32 ---- Dependencies: IEEE.std_logic_1164 ----
33 ---- IEEE.numeric_std ----
35 ---- work.zpu_memory ----
36 ---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
37 ---- Language: VHDL ----
38 ---- Wishbone: No ----
39 ---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
40 ---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
41 ---- Text editor: SETEdit 0.5.x ----
43 ------------------------------------------------------------------------------
46 use IEEE.std_logic_1164.all;
47 use IEEE.numeric_std.all;
54 use work.zpu_memory.all;
58 WORD_SIZE : natural:=32; -- 32 bits data path
59 D_CARE_VAL : std_logic:='0'; -- Fill value
60 CLK_FREQ : positive:=50; -- 50 MHz clock
61 BRATE : positive:=115200; -- RS232 baudrate
62 ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
63 BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
65 clk_i : in std_logic; -- CPU clock
66 rst_i : in std_logic; -- Reset
69 emureq_i : in std_logic;
70 emuexec_i : in std_logic;
71 emuack_o : out std_logic;
72 emurdy_o : out std_logic;
73 emuir : in std_logic_vector(OPCODE_W-1 downto 0);
75 break_o : out std_logic; -- Break executed
76 dbg_o : out zpu_dbgo_t; -- Debug info
77 rs232_tx_o : out std_logic; -- UART Tx
78 rs232_rx_i : in std_logic); -- UART Rx
79 end entity ZPU_Small1;
81 architecture Structural of ZPU_Small1 is
82 constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
83 constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
84 constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4;
86 -- Program+data+stack BRAM
88 signal a_we : std_logic;
89 signal a_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
90 signal a_write : unsigned(WORD_SIZE-1 downto 0);
91 signal a_read : unsigned(WORD_SIZE-1 downto 0);
93 signal b_we : std_logic;
94 signal b_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
95 signal b_write : unsigned(WORD_SIZE-1 downto 0);
96 signal b_read : unsigned(WORD_SIZE-1 downto 0);
99 signal io_busy : std_logic;
100 signal io_write : unsigned(WORD_SIZE-1 downto 0);
101 signal io_read : unsigned(WORD_SIZE-1 downto 0);
102 signal io_addr : unsigned(ADDR_W-1 downto 0);
103 signal phi_addr : unsigned(2 downto 0);
104 signal io_we : std_logic;
105 signal io_re : std_logic;
109 WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
113 a_we_i => a_we, a_addr_i => a_addr, a_write_i => a_write,
116 b_we_i => b_we, b_addr_i => b_addr, b_write_i => b_write,
122 BRDIVISOR => BRDIVISOR, LOG_FILE => "zpu_small1_io.log")
124 clk_i => clk_i, reset_i => rst_i, busy_o => io_busy, we_i => io_we,
125 re_i => io_re, data_i => io_write, data_o => io_read,
126 addr_i => phi_addr, rs232_rx_i => rs232_rx_i, rs232_tx_o => rs232_tx_o,
128 phi_addr <= io_addr(4 downto 2);
132 WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
133 D_CARE_VAL => D_CARE_VAL)
135 clk_i => clk_i, reset_i => rst_i, interrupt_i => '0',
136 emureq_i => emureq_i,
137 emuexec_i => emuexec_i,
138 emuack_o => emuack_o,
139 emurdy_o => emurdy_o,
141 break_o => break_o, dbg_o => dbg_o,
143 -- BRAM (text, data, bss and stack)
144 a_we_o => a_we, a_addr_o => a_addr, a_o => a_write, a_i => a_read,
145 b_we_o => b_we, b_addr_o => b_addr, b_o => b_write, b_i => b_read,
147 mem_busy_i => io_busy, data_i => io_read, data_o => io_write,
148 addr_o => io_addr, write_en_o => io_we, read_en_o => io_re);
149 end architecture Structural; -- Entity: ZPU_Small1