zpu/hdl/wishbone/wishbone_pkg.vhd

   1 -- ZPU
   2 --
   3 -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
   4 --
   5 -- The FreeBSD license
   6 --
   7 -- Redistribution and use in source and binary forms, with or without
   8 -- modification, are permitted provided that the following conditions
   9 -- are met:
  10 --
  11 -- 1. Redistributions of source code must retain the above copyright
  12 --    notice, this list of conditions and the following disclaimer.
  13 -- 2. Redistributions in binary form must reproduce the above
  14 --    copyright notice, this list of conditions and the following
  15 --    disclaimer in the documentation and/or other materials
  16 --    provided with the distribution.
  17 --
  18 -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
  19 -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  20 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  21 -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  22 -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  23 -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24 -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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  32 -- are those of the authors and should not be interpreted as representing
  33 -- official policies, either expressed or implied, of the ZPU Project.
  34
  35 library IEEE;
  36 use IEEE.STD_LOGIC_1164.all;
  37 use IEEE.STD_LOGIC_UNSIGNED.ALL;
  38
  39 package wishbone_pkg is
  40
  41         type wishbone_bus_in is record
  42                 adr                     : std_logic_vector(31 downto 0);
  43                 sel                     : std_logic_vector(3 downto 0);
  44                 we                      : std_logic;
  45                 dat                     : std_logic_vector(31 downto 0);        -- Note! Data written with 'we'
  46                 cyc                     : std_logic;
  47                 stb                     : std_logic;
  48         end record;
  49
  50         type wishbone_bus_out is record
  51                 dat             : std_logic_vector(31 downto 0);
  52                 ack                     : std_logic;
  53         end record;
  54
  55         type wishbone_bus is record
  56                 insig           : wishbone_bus_in;
  57                 outsig          : wishbone_bus_out;
  58         end record;
  59
  60         component atomic32_access is
  61         port (  cpu_clk                 : in std_logic;
  62                         areset                  : in std_logic;
  63
  64                         -- Wishbone from CPU interface
  65                         wb_16_i                 : in wishbone_bus_in;
  66                         wb_16_o         : out wishbone_bus_out;
  67                         -- Wishbone to FPGA registers and ethernet core
  68                         wb_32_i                 : in wishbone_bus_out;
  69                         wb_32_o                 : out wishbone_bus_in);
  70         end component;
  71
  72         component eth_access_corr is
  73         port (  cpu_clk                 : in std_logic;
  74                         areset                  : in std_logic;
  75
  76                         -- Wishbone from Wishbone MUX
  77                         eth_raw_o               : out wishbone_bus_out;
  78                         eth_raw_i               : in wishbone_bus_in;
  79
  80                         -- Wishbone ethernet core
  81                         eth_slave_i     : in wishbone_bus_out;
  82                         eth_slave_o             : out wishbone_bus_in);
  83         end component;
  84
  85
  86 end wishbone_pkg;