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preprocessor cleanup: __xpv
[unleashed.git] / usr / src / uts / i86pc / io / mp_platform_common.c
bloba055b81c12b86e6607f8a74a8865abf744ec9895
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2016 Nexenta Systems, Inc.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29
30 /*
31 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
32 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
33 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
34 * PSMI 1.5 extensions are supported in Solaris Nevada.
35 * PSMI 1.6 extensions are supported in Solaris Nevada.
36 * PSMI 1.7 extensions are supported in Solaris Nevada.
37 */
38 #define PSMI_1_7
39
40 #include <sys/processor.h>
41 #include <sys/time.h>
42 #include <sys/psm.h>
43 #include <sys/smp_impldefs.h>
44 #include <sys/cram.h>
45 #include <sys/acpi/acpi.h>
46 #include <sys/acpica.h>
47 #include <sys/psm_common.h>
48 #include <sys/apic.h>
49 #include <sys/apic_timer.h>
50 #include <sys/pit.h>
51 #include <sys/ddi.h>
52 #include <sys/sunddi.h>
53 #include <sys/ddi_impldefs.h>
54 #include <sys/pci.h>
55 #include <sys/promif.h>
56 #include <sys/x86_archext.h>
57 #include <sys/cpc_impl.h>
58 #include <sys/uadmin.h>
59 #include <sys/panic.h>
60 #include <sys/debug.h>
61 #include <sys/archsystm.h>
62 #include <sys/trap.h>
63 #include <sys/machsystm.h>
64 #include <sys/cpuvar.h>
65 #include <sys/rm_platter.h>
66 #include <sys/privregs.h>
67 #include <sys/cyclic.h>
68 #include <sys/note.h>
69 #include <sys/pci_intr_lib.h>
70 #include <sys/sunndi.h>
71 #include <sys/hpet.h>
72 #include <sys/clock.h>
73
74 /*
75 * Local Function Prototypes
76 */
77 static int apic_handle_defconf();
78 static int apic_parse_mpct(caddr_t mpct, int bypass);
79 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
80 static int apic_checksum(caddr_t bptr, int len);
81 static int apic_find_bus_type(char *bus);
82 static int apic_find_bus(int busid);
83 static struct apic_io_intr *apic_find_io_intr(int irqno);
84 static int apic_find_free_irq(int start, int end);
85 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
86 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
87 static void apic_free_apic_cpus(void);
88 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
89 static int apic_acpi_enter_apicmode(void);
90
91 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
92 int child_ipin, struct apic_io_intr **intrp);
93 int apic_find_bus_id(int bustype);
94 int apic_find_intin(uchar_t ioapic, uchar_t intin);
95 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
96
97 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
98
99 /* ACPI SCI interrupt configuration; -1 if SCI not used */
100 int apic_sci_vect = -1;
101 iflag_t apic_sci_flags;
102
103 /* ACPI HPET interrupt configuration; -1 if HPET not used */
104 int apic_hpet_vect = -1;
105 iflag_t apic_hpet_flags;
106
107 /*
108 * psm name pointer
109 */
110 char *psm_name;
111
112 /* ACPI support routines */
113 static int acpi_probe(char *);
114 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
115 int *pci_irqp, iflag_t *intr_flagp);
116
117 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
118 int ipin, int *pci_irqp, iflag_t *intr_flagp);
119 uchar_t acpi_find_ioapic(int irq);
120 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
121
122 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
123 int apic_max_reps_clear_pending = 1000;
124
125 int apic_intr_policy = INTR_ROUND_ROBIN;
126
127 int apic_next_bind_cpu = 1; /* For round robin assignment */
128 /* start with cpu 1 */
129
130 /*
131 * If enabled, the distribution works as follows:
132 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
133 * and the irq corresponding to the ipl is also set in the aci_current array.
134 * interrupt exit and setspl (due to soft interrupts) will cause the current
135 * ipl to be be changed. This is cache friendly as these frequently used
136 * paths write into a per cpu structure.
137 *
138 * Sampling is done by checking the structures for all CPUs and incrementing
139 * the busy field of the irq (if any) executing on each CPU and the busy field
140 * of the corresponding CPU.
141 * In periodic mode this is done on every clock interrupt.
142 * In one-shot mode, this is done thru a cyclic with an interval of
143 * apic_redistribute_sample_interval (default 10 milli sec).
144 *
145 * Every apic_sample_factor_redistribution times we sample, we do computations
146 * to decide which interrupt needs to be migrated (see comments
147 * before apic_intr_redistribute().
148 */
149
150 /*
151 * Following 3 variables start as % and can be patched or set using an
152 * API to be defined in future. They will be scaled to
153 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
154 * mode), or 101 in one-shot mode to stagger it away from one sec processing
155 */
156
157 int apic_int_busy_mark = 60;
158 int apic_int_free_mark = 20;
159 int apic_diff_for_redistribution = 10;
160
161 /* sampling interval for interrupt redistribution for dynamic migration */
162 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
163
164 /*
165 * number of times we sample before deciding to redistribute interrupts
166 * for dynamic migration
167 */
168 int apic_sample_factor_redistribution = 101;
169
170 int apic_redist_cpu_skip = 0;
171 int apic_num_imbalance = 0;
172 int apic_num_rebind = 0;
173
174 /*
175 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
176 * allocation of CPU ids is disabled.
177 */
178 int apic_max_nproc = -1;
179 int apic_nproc = 0;
180 size_t apic_cpus_size = 0;
181 int apic_defconf = 0;
182 int apic_irq_translate = 0;
183 int apic_spec_rev = 0;
184 int apic_imcrp = 0;
185
186 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */
187 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
188
189 /*
190 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
191 * will be assigned (via _SRS). If it is not set, use the current
192 * irq setting (via _CRS), but only if that irq is in the set of possible
193 * irqs (returned by _PRS) for the device.
194 */
195 int apic_unconditional_srs = 1;
196
197 /*
198 * For interrupt link devices, if apic_prefer_crs is set when we are
199 * assigning an IRQ resource to a device, prefer the current IRQ setting
200 * over other possible irq settings under same conditions.
201 */
202
203 int apic_prefer_crs = 1;
204
205 uchar_t apic_io_id[MAX_IO_APIC];
206 volatile uint32_t *apicioadr[MAX_IO_APIC];
207 uchar_t apic_io_ver[MAX_IO_APIC];
208 uchar_t apic_io_vectbase[MAX_IO_APIC];
209 uchar_t apic_io_vectend[MAX_IO_APIC];
210 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
211 uint32_t apic_physaddr[MAX_IO_APIC];
212
213 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
214
215 /*
216 * First available slot to be used as IRQ index into the apic_irq_table
217 * for those interrupts (like MSI/X) that don't have a physical IRQ.
218 */
219 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ;
220
221 /*
222 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
223 * and bound elements of cpus_info and the temp_cpu element of irq_struct
224 */
225 lock_t apic_ioapic_lock;
226
227 int apic_io_max = 0; /* no. of i/o apics enabled */
228
229 struct apic_io_intr *apic_io_intrp = NULL;
230 static struct apic_bus *apic_busp;
231
232 uchar_t apic_resv_vector[MAXIPL+1];
233
234 char apic_level_intr[APIC_MAX_VECTOR+1];
235
236 uint32_t eisa_level_intr_mask = 0;
237 /* At least MSB will be set if EISA bus */
238
239 int apic_pci_bus_total = 0;
240 uchar_t apic_single_pci_busid = 0;
241
242 /*
243 * airq_mutex protects additions to the apic_irq_table - the first
244 * pointer and any airq_nexts off of that one. It also protects
245 * apic_max_device_irq & apic_min_device_irq. It also guarantees
246 * that share_id is unique as new ids are generated only when new
247 * irq_t structs are linked in. Once linked in the structs are never
248 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
249 * or allocated. Note that there is a slight gap between allocating in
250 * apic_introp_xlate and programming in addspl.
251 */
252 kmutex_t airq_mutex;
253 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
254 int apic_max_device_irq = 0;
255 int apic_min_device_irq = APIC_MAX_VECTOR;
256
257 typedef struct prs_irq_list_ent {
258 int list_prio;
259 int32_t irq;
260 iflag_t intrflags;
261 acpi_prs_private_t prsprv;
262 struct prs_irq_list_ent *next;
263 } prs_irq_list_t;
264
265
266 /*
267 * ACPI variables
268 */
269 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
270 int apic_enable_acpi = 0;
271
272 /* ACPI Multiple APIC Description Table ptr */
273 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
274
275 /* ACPI Interrupt Source Override Structure ptr */
276 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
277 int acpi_iso_cnt = 0;
278
279 /* ACPI Non-maskable Interrupt Sources ptr */
280 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
281 static int acpi_nmi_scnt = 0;
282 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
283 static int acpi_nmi_ccnt = 0;
284
285 /*
286 * The following added to identify a software poweroff method if available.
287 */
288
289 static struct {
290 int poweroff_method;
291 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */
292 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */
293 } apic_mps_ids[] = {
294 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */
295 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */
296 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */
297 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */
298 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */
299 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */
300 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */
301 };
302
303 int apic_poweroff_method = APIC_POWEROFF_NONE;
304
305 /*
306 * Auto-configuration routines
307 */
308
309 /*
310 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
311 * May work with 1.1 - but not guaranteed.
312 * According to the MP Spec, the MP floating pointer structure
313 * will be searched in the order described below:
314 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
315 * 2. Within the last kilobyte of system base memory
316 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
317 * Once we find the right signature with proper checksum, we call
318 * either handle_defconf or parse_mpct to get all info necessary for
319 * subsequent operations.
320 */
321 int
322 apic_probe_common(char *modname)
323 {
324 uint32_t mpct_addr, ebda_start = 0, base_mem_end;
325 caddr_t biosdatap;
326 caddr_t mpct = 0;
327 caddr_t fptr;
328 int i, mpct_size, mapsize, retval = PSM_FAILURE;
329 ushort_t ebda_seg, base_mem_size;
330 struct apic_mpfps_hdr *fpsp;
331 struct apic_mp_cnf_hdr *hdrp;
332 int bypass_cpu_and_ioapics_in_mptables;
333 int acpi_user_options;
334
335 if (apic_forceload < 0)
336 return (retval);
337
338 /*
339 * Remember who we are
340 */
341 psm_name = modname;
342
343 /* Allow override for MADT-only mode */
344 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
345 "acpi-user-options", 0);
346 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
347
348 /* Allow apic_use_acpi to override MADT-only mode */
349 if (!apic_use_acpi)
350 apic_use_acpi_madt_only = 0;
351
352 retval = acpi_probe(modname);
353
354 /*
355 * mapin the bios data area 40:0
356 * 40:13h - two-byte location reports the base memory size
357 * 40:0Eh - two-byte location for the exact starting address of
358 * the EBDA segment for EISA
359 */
360 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
361 if (!biosdatap)
362 goto apic_ret;
363 fpsp = NULL;
364 mapsize = MPFPS_RAM_WIN_LEN;
365 /*LINTED: pointer cast may result in improper alignment */
366 ebda_seg = *((ushort_t *)(biosdatap+0xe));
367 /* check the 1k of EBDA */
368 if (ebda_seg) {
369 ebda_start = ((uint32_t)ebda_seg) << 4;
370 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
371 if (fptr) {
372 if (!(fpsp =
373 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
374 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
375 }
376 }
377 /* If not in EBDA, check the last k of system base memory */
378 if (!fpsp) {
379 /*LINTED: pointer cast may result in improper alignment */
380 base_mem_size = *((ushort_t *)(biosdatap + 0x13));
381
382 if (base_mem_size > 512)
383 base_mem_end = 639 * 1024;
384 else
385 base_mem_end = 511 * 1024;
386 /* if ebda == last k of base mem, skip to check BIOS ROM */
387 if (base_mem_end != ebda_start) {
388
389 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
390 PROT_READ);
391
392 if (fptr) {
393 if (!(fpsp = apic_find_fps_sig(fptr,
394 MPFPS_RAM_WIN_LEN)))
395 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
396 }
397 }
398 }
399 psm_unmap_phys(biosdatap, 0x20);
400
401 /* If still cannot find it, check the BIOS ROM space */
402 if (!fpsp) {
403 mapsize = MPFPS_ROM_WIN_LEN;
404 fptr = psm_map_phys(MPFPS_ROM_WIN_START,
405 MPFPS_ROM_WIN_LEN, PROT_READ);
406 if (fptr) {
407 if (!(fpsp =
408 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
409 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
410 goto apic_ret;
411 }
412 }
413 }
414
415 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
416 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
417 goto apic_ret;
418 }
419
420 apic_spec_rev = fpsp->mpfps_spec_rev;
421 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
422 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
423 goto apic_ret;
424 }
425
426 /* check IMCR is present or not */
427 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
428
429 /* check default configuration (dual CPUs) */
430 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
431 psm_unmap_phys(fptr, mapsize);
432 if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
433 return (retval);
434
435 goto apic_ret;
436 }
437
438 /* MP Configuration Table */
439 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
440
441 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
442
443 /*
444 * Map in enough memory for the MP Configuration Table Header.
445 * Use this table to read the total length of the BIOS data and
446 * map in all the info
447 */
448 /*LINTED: pointer cast may result in improper alignment */
449 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
450 sizeof (struct apic_mp_cnf_hdr), PROT_READ);
451 if (!hdrp)
452 goto apic_ret;
453
454 /* check mp configuration table signature PCMP */
455 if (hdrp->mpcnf_sig != 0x504d4350) {
456 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
457 goto apic_ret;
458 }
459 mpct_size = (int)hdrp->mpcnf_tbl_length;
460
461 apic_set_pwroff_method_from_mpcnfhdr(hdrp);
462
463 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
464
465 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
466 /* This is an ACPI machine No need for further checks */
467 goto apic_ret;
468 }
469
470 /*
471 * Map in the entries for this machine, ie. Processor
472 * Entry Tables, Bus Entry Tables, etc.
473 * They are in fixed order following one another
474 */
475 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
476 if (!mpct)
477 goto apic_ret;
478
479 if (apic_checksum(mpct, mpct_size) != 0)
480 goto apic_fail1;
481
482 /*LINTED: pointer cast may result in improper alignment */
483 hdrp = (struct apic_mp_cnf_hdr *)mpct;
484 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
485 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
486 if (!apicadr)
487 goto apic_fail1;
488
489 /* Parse all information in the tables */
490 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
491 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
492 PSM_SUCCESS) {
493 retval = PSM_SUCCESS;
494 goto apic_ret;
495 }
496
497 apic_fail1:
498 psm_unmap_phys(mpct, mpct_size);
499 mpct = NULL;
500
501 apic_ret:
502 if (retval == PSM_SUCCESS) {
503 extern int apic_ioapic_method_probe();
504
505 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS)
506 return (PSM_SUCCESS);
507 }
508
509 for (i = 0; i < apic_io_max; i++)
510 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
511 if (apic_cpus) {
512 kmem_free(apic_cpus, apic_cpus_size);
513 apic_cpus = NULL;
514 }
515 if (apicadr) {
516 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
517 apicadr = NULL;
518 }
519 if (mpct)
520 psm_unmap_phys(mpct, mpct_size);
521
522 return (retval);
523 }
524
525 static void
526 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
527 {
528 int i;
529
530 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
531 i++) {
532 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
533 strlen(apic_mps_ids[i].oem_id)) == 0) &&
534 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
535 strlen(apic_mps_ids[i].prod_id)) == 0)) {
536
537 apic_poweroff_method = apic_mps_ids[i].poweroff_method;
538 break;
539 }
540 }
541
542 if (apic_debug_mps_id != 0) {
543 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
544 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
545 psm_name,
546 hdrp->mpcnf_oem_str[0],
547 hdrp->mpcnf_oem_str[1],
548 hdrp->mpcnf_oem_str[2],
549 hdrp->mpcnf_oem_str[3],
550 hdrp->mpcnf_oem_str[4],
551 hdrp->mpcnf_oem_str[5],
552 hdrp->mpcnf_oem_str[6],
553 hdrp->mpcnf_oem_str[7],
554 hdrp->mpcnf_prod_str[0],
555 hdrp->mpcnf_prod_str[1],
556 hdrp->mpcnf_prod_str[2],
557 hdrp->mpcnf_prod_str[3],
558 hdrp->mpcnf_prod_str[4],
559 hdrp->mpcnf_prod_str[5],
560 hdrp->mpcnf_prod_str[6],
561 hdrp->mpcnf_prod_str[7],
562 hdrp->mpcnf_prod_str[8],
563 hdrp->mpcnf_prod_str[9],
564 hdrp->mpcnf_prod_str[10],
565 hdrp->mpcnf_prod_str[11]);
566 }
567 }
568
569 static void
570 apic_free_apic_cpus(void)
571 {
572 if (apic_cpus != NULL) {
573 kmem_free(apic_cpus, apic_cpus_size);
574 apic_cpus = NULL;
575 apic_cpus_size = 0;
576 }
577 }
578
579 static int
580 acpi_probe(char *modname)
581 {
582 int i, intmax, index;
583 uint32_t id, ver;
584 int acpi_verboseflags = 0;
585 int madt_seen, madt_size;
586 ACPI_SUBTABLE_HEADER *ap;
587 ACPI_MADT_LOCAL_APIC *mpa;
588 ACPI_MADT_LOCAL_X2APIC *mpx2a;
589 ACPI_MADT_IO_APIC *mia;
590 ACPI_MADT_IO_SAPIC *misa;
591 ACPI_MADT_INTERRUPT_OVERRIDE *mio;
592 ACPI_MADT_NMI_SOURCE *mns;
593 ACPI_MADT_INTERRUPT_SOURCE *mis;
594 ACPI_MADT_LOCAL_APIC_NMI *mlan;
595 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan;
596 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao;
597 int sci;
598 iflag_t sci_flags;
599 volatile uint32_t *ioapic;
600 int ioapic_ix;
601 uint32_t *local_ids;
602 uint32_t *proc_ids;
603 uchar_t hid;
604 int warned = 0;
605
606 if (!apic_use_acpi)
607 return (PSM_FAILURE);
608
609 if (AcpiGetTable(ACPI_SIG_MADT, 1,
610 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK)
611 return (PSM_FAILURE);
612
613 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
614 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
615 if (!apicadr)
616 return (PSM_FAILURE);
617
618 if ((local_ids = kmem_zalloc(NCPU * sizeof (uint32_t),
619 KM_NOSLEEP)) == NULL)
620 return (PSM_FAILURE);
621
622 if ((proc_ids = kmem_zalloc(NCPU * sizeof (uint32_t),
623 KM_NOSLEEP)) == NULL) {
624 kmem_free(local_ids, NCPU * sizeof (uint32_t));
625 return (PSM_FAILURE);
626 }
627
628 id = apic_reg_ops->apic_read(APIC_LID_REG);
629 local_ids[0] = (uchar_t)(id >> 24);
630 apic_nproc = index = 1;
631 apic_io_max = 0;
632
633 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
634 madt_size = acpi_mapic_dtp->Header.Length;
635 madt_seen = sizeof (*acpi_mapic_dtp);
636
637 while (madt_seen < madt_size) {
638 switch (ap->Type) {
639 case ACPI_MADT_TYPE_LOCAL_APIC:
640 mpa = (ACPI_MADT_LOCAL_APIC *) ap;
641 if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
642 if (mpa->Id == 255) {
643 cmn_err(CE_WARN, "!%s: encountered "
644 "invalid entry in MADT: CPU %d "
645 "has Local APIC Id equal to 255 ",
646 psm_name, mpa->ProcessorId);
647 }
648 if (mpa->Id == local_ids[0]) {
649 ASSERT(index == 1);
650 proc_ids[0] = mpa->ProcessorId;
651 } else if (apic_nproc < NCPU && use_mp &&
652 apic_nproc < boot_ncpus) {
653 local_ids[index] = mpa->Id;
654 proc_ids[index] = mpa->ProcessorId;
655 index++;
656 apic_nproc++;
657 } else if (apic_nproc == NCPU && !warned) {
658 cmn_err(CE_WARN, "%s: CPU limit "
659 "exceeded"
660 #if !defined(__amd64)
661 " for 32-bit mode"
662 #endif
663 "; Solaris will use %d CPUs.",
664 psm_name, NCPU);
665 warned = 1;
666 }
667 }
668 break;
669
670 case ACPI_MADT_TYPE_IO_APIC:
671 mia = (ACPI_MADT_IO_APIC *) ap;
672 if (apic_io_max < MAX_IO_APIC) {
673 ioapic_ix = apic_io_max;
674 apic_io_id[apic_io_max] = mia->Id;
675 apic_io_vectbase[apic_io_max] =
676 mia->GlobalIrqBase;
677 apic_physaddr[apic_io_max] =
678 (uint32_t)mia->Address;
679 ioapic = apicioadr[apic_io_max] =
680 mapin_ioapic((uint32_t)mia->Address,
681 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
682 if (!ioapic)
683 goto cleanup;
684 ioapic_mask_workaround[apic_io_max] =
685 apic_is_ioapic_AMD_813x(mia->Address);
686 apic_io_max++;
687 }
688 break;
689
690 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
691 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
692 if (acpi_isop == NULL)
693 acpi_isop = mio;
694 acpi_iso_cnt++;
695 break;
696
697 case ACPI_MADT_TYPE_NMI_SOURCE:
698 /* UNIMPLEMENTED */
699 mns = (ACPI_MADT_NMI_SOURCE *) ap;
700 if (acpi_nmi_sp == NULL)
701 acpi_nmi_sp = mns;
702 acpi_nmi_scnt++;
703
704 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n",
705 mns->GlobalIrq, mns->IntiFlags);
706 break;
707
708 case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
709 /* UNIMPLEMENTED */
710 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
711 if (acpi_nmi_cp == NULL)
712 acpi_nmi_cp = mlan;
713 acpi_nmi_ccnt++;
714
715 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n",
716 mlan->ProcessorId, mlan->IntiFlags,
717 mlan->Lint);
718 break;
719
720 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
721 /* UNIMPLEMENTED */
722 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
723 cmn_err(CE_NOTE, "!apic: address override: %lx\n",
724 (long)mao->Address);
725 break;
726
727 case ACPI_MADT_TYPE_IO_SAPIC:
728 /* UNIMPLEMENTED */
729 misa = (ACPI_MADT_IO_SAPIC *) ap;
730
731 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n",
732 misa->Id, misa->GlobalIrqBase,
733 (long)misa->Address);
734 break;
735
736 case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
737 /* UNIMPLEMENTED */
738 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
739
740 cmn_err(CE_NOTE,
741 "!apic: irq source: %d %d %d 0x%x %d %d\n",
742 mis->Id, mis->Eid, mis->GlobalIrq,
743 mis->IntiFlags, mis->Type,
744 mis->IoSapicVector);
745 break;
746
747 case ACPI_MADT_TYPE_LOCAL_X2APIC:
748 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
749
750 /*
751 * All logical processors with APIC ID values
752 * of 255 and greater will have their APIC
753 * reported through Processor X2APIC structure.
754 * All logical processors with APIC ID less than
755 * 255 will have their APIC reported through
756 * Processor Local APIC.
757 *
758 * Some systems apparently don't care and report all
759 * processors through Processor X2APIC structures. We
760 * warn about that but don't ignore those CPUs.
761 */
762 if (mpx2a->LocalApicId < 255) {
763 cmn_err(CE_WARN, "!%s: ignoring invalid entry "
764 "in MADT: CPU %d has X2APIC Id %d (< 255)",
765 psm_name, mpx2a->Uid, mpx2a->LocalApicId);
766 }
767 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
768 if (mpx2a->LocalApicId == local_ids[0]) {
769 ASSERT(index == 1);
770 proc_ids[0] = mpx2a->Uid;
771 } else if (apic_nproc < NCPU && use_mp &&
772 apic_nproc < boot_ncpus) {
773 local_ids[index] = mpx2a->LocalApicId;
774 proc_ids[index] = mpx2a->Uid;
775 index++;
776 apic_nproc++;
777 } else if (apic_nproc == NCPU && !warned) {
778 cmn_err(CE_WARN, "%s: CPU limit "
779 "exceeded"
780 #if !defined(__amd64)
781 " for 32-bit mode"
782 #endif
783 "; Solaris will use %d CPUs.",
784 psm_name, NCPU);
785 warned = 1;
786 }
787 }
788
789 break;
790
791 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
792 /* UNIMPLEMENTED */
793 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
794 if (mx2alan->Uid >> 8)
795 acpi_nmi_ccnt++;
796
797 #ifdef DEBUG
798 cmn_err(CE_NOTE,
799 "!apic: local x2apic nmi: %d 0x%x %d\n",
800 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
801 #endif
802
803 break;
804
805 case ACPI_MADT_TYPE_RESERVED:
806 default:
807 break;
808 }
809
810 /* advance to next entry */
811 madt_seen += ap->Length;
812 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
813 }
814
815 /*
816 * allocate enough space for possible hot-adding of CPUs.
817 * max_ncpus may be less than apic_nproc if it's set by user.
818 */
819 if (plat_dr_support_cpu()) {
820 apic_max_nproc = max_ncpus;
821 }
822 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
823 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
824 goto cleanup;
825
826 /*
827 * ACPI doesn't provide the local apic ver, get it directly from the
828 * local apic
829 */
830 ver = apic_reg_ops->apic_read(APIC_VERS_REG);
831 for (i = 0; i < apic_nproc; i++) {
832 apic_cpus[i].aci_local_id = local_ids[i];
833 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
834 apic_cpus[i].aci_processor_id = proc_ids[i];
835 /* Only build mapping info for CPUs present at boot. */
836 if (i < boot_ncpus)
837 (void) acpica_map_cpu(i, proc_ids[i]);
838 }
839
840 /*
841 * To support CPU dynamic reconfiguration, the apic CPU info structure
842 * for each possible CPU will be pre-allocated at boot time.
843 * The state for each apic CPU info structure will be assigned according
844 * to the following rules:
845 * Rule 1:
846 * Slot index range: [0, min(apic_nproc, boot_ncpus))
847 * State flags: 0
848 * Note: cpu exists and will be configured/enabled at boot time
849 * Rule 2:
850 * Slot index range: [boot_ncpus, apic_nproc)
851 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
852 * Note: cpu exists but won't be configured/enabled at boot time
853 * Rule 3:
854 * Slot index range: [apic_nproc, boot_ncpus)
855 * State flags: APIC_CPU_FREE
856 * Note: cpu doesn't exist at boot time
857 * Rule 4:
858 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
859 * State flags: APIC_CPU_FREE
860 * Note: cpu doesn't exist at boot time
861 */
862 CPUSET_ZERO(apic_cpumask);
863 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
864 CPUSET_ADD(apic_cpumask, i);
865 apic_cpus[i].aci_status = 0;
866 }
867 for (i = boot_ncpus; i < apic_nproc; i++) {
868 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
869 }
870 for (i = apic_nproc; i < boot_ncpus; i++) {
871 apic_cpus[i].aci_status = APIC_CPU_FREE;
872 }
873 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
874 apic_cpus[i].aci_status = APIC_CPU_FREE;
875 }
876
877 for (i = 0; i < apic_io_max; i++) {
878 ioapic_ix = i;
879
880 /*
881 * need to check Sitka on the following acpi problem
882 * On the Sitka, the ioapic's apic_id field isn't reporting
883 * the actual io apic id. We have reported this problem
884 * to Intel. Until they fix the problem, we will get the
885 * actual id directly from the ioapic.
886 */
887 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
888 hid = (uchar_t)(id >> 24);
889
890 if (hid != apic_io_id[i]) {
891 if (apic_io_id[i] == 0)
892 apic_io_id[i] = hid;
893 else { /* set ioapic id to whatever reported by ACPI */
894 id = ((uint32_t)apic_io_id[i]) << 24;
895 ioapic_write(ioapic_ix, APIC_ID_CMD, id);
896 }
897 }
898 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
899 apic_io_ver[i] = (uchar_t)(ver & 0xff);
900 intmax = (ver >> 16) & 0xff;
901 apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
902 if (apic_first_avail_irq <= apic_io_vectend[i])
903 apic_first_avail_irq = apic_io_vectend[i] + 1;
904 }
905
906
907 /*
908 * Process SCI configuration here
909 * An error may be returned here if
910 * acpi-user-options specifies legacy mode
911 * (no SCI, no ACPI mode)
912 */
913 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
914 sci = -1;
915
916 /*
917 * Now call acpi_init() to generate namespaces
918 * If this fails, we don't attempt to use ACPI
919 * even if we were able to get a MADT above
920 */
921 if (acpica_init() != AE_OK)
922 goto cleanup;
923
924 /*
925 * Call acpica_build_processor_map() now that we have
926 * ACPI namesspace access
927 */
928 (void) acpica_build_processor_map();
929
930 /*
931 * Squirrel away the SCI and flags for later on
932 * in apic_picinit() when we're ready
933 */
934 apic_sci_vect = sci;
935 apic_sci_flags = sci_flags;
936
937 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
938 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
939
940 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
941 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
942
943 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
944 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
945
946 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
947 goto cleanup;
948
949 /* Enable ACPI APIC interrupt routing */
950 if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
951 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
952 apic_enable_acpi = 1;
953 if (apic_sci_vect > 0) {
954 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
955 }
956 if (apic_use_acpi_madt_only) {
957 cmn_err(CE_CONT,
958 "?Using ACPI for CPU/IOAPIC information ONLY\n");
959 }
960
961 /*
962 * probe ACPI for hpet information here which is used later
963 * in apic_picinit().
964 */
965 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) {
966 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n");
967 }
968
969 kmem_free(local_ids, NCPU * sizeof (uint32_t));
970 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
971 return (PSM_SUCCESS);
972 }
973 /* if setting APIC mode failed above, we fall through to cleanup */
974
975 cleanup:
976 apic_free_apic_cpus();
977 if (apicadr != NULL) {
978 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
979 apicadr = NULL;
980 }
981 apic_max_nproc = -1;
982 apic_nproc = 0;
983 for (i = 0; i < apic_io_max; i++) {
984 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
985 apicioadr[i] = NULL;
986 }
987 apic_io_max = 0;
988 acpi_isop = NULL;
989 acpi_iso_cnt = 0;
990 acpi_nmi_sp = NULL;
991 acpi_nmi_scnt = 0;
992 acpi_nmi_cp = NULL;
993 acpi_nmi_ccnt = 0;
994 kmem_free(local_ids, NCPU * sizeof (uint32_t));
995 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
996 return (PSM_FAILURE);
997 }
998
999 /*
1000 * Handle default configuration. Fill in reqd global variables & tables
1001 * Fill all details as MP table does not give any more info
1002 */
1003 static int
1004 apic_handle_defconf()
1005 {
1006 uint_t lid;
1007
1008 /* Failed to probe ACPI MADT tables, disable CPU DR. */
1009 apic_max_nproc = -1;
1010 apic_free_apic_cpus();
1011 plat_dr_disable_cpu();
1012
1013 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1014 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1015 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1016 APIC_LOCAL_MEMLEN, PROT_READ);
1017 apic_cpus_size = 2 * sizeof (*apic_cpus);
1018 apic_cpus = (apic_cpus_info_t *)
1019 kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1020 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1021 goto apic_handle_defconf_fail;
1022 CPUSET_ONLY(apic_cpumask, 0);
1023 CPUSET_ADD(apic_cpumask, 1);
1024 apic_nproc = 2;
1025 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1026 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET);
1027 /*
1028 * According to the PC+MP spec 1.1, the local ids
1029 * for the default configuration has to be 0 or 1
1030 */
1031 if (apic_cpus[0].aci_local_id == 1)
1032 apic_cpus[1].aci_local_id = 0;
1033 else if (apic_cpus[0].aci_local_id == 0)
1034 apic_cpus[1].aci_local_id = 1;
1035 else
1036 goto apic_handle_defconf_fail;
1037
1038 apic_io_id[0] = 2;
1039 apic_io_max = 1;
1040 if (apic_defconf >= 5) {
1041 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1042 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1043 apic_io_ver[0] = APIC_INTEGRATED_VERS;
1044 } else {
1045 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */
1046 apic_cpus[1].aci_local_ver = 0;
1047 apic_io_ver[0] = 0;
1048 }
1049 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1050 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1051 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1052 return (PSM_SUCCESS);
1053
1054 apic_handle_defconf_fail:
1055 if (apicadr)
1056 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1057 if (apicioadr[0])
1058 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1059 return (PSM_FAILURE);
1060 }
1061
1062 /* Parse the entries in MP configuration table and collect info that we need */
1063 static int
1064 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1065 {
1066 struct apic_procent *procp;
1067 struct apic_bus *busp;
1068 struct apic_io_entry *ioapicp;
1069 struct apic_io_intr *intrp;
1070 int ioapic_ix;
1071 uint_t lid;
1072 uint32_t id;
1073 uchar_t hid;
1074 int warned = 0;
1075
1076 /*LINTED: pointer cast may result in improper alignment */
1077 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1078
1079 /* No need to count cpu entries if we won't use them */
1080 if (!bypass_cpus_and_ioapics) {
1081
1082 /* Find max # of CPUS and allocate structure accordingly */
1083 apic_nproc = 0;
1084 CPUSET_ZERO(apic_cpumask);
1085 while (procp->proc_entry == APIC_CPU_ENTRY) {
1086 if (procp->proc_cpuflags & CPUFLAGS_EN) {
1087 if (apic_nproc < NCPU && use_mp &&
1088 apic_nproc < boot_ncpus) {
1089 CPUSET_ADD(apic_cpumask, apic_nproc);
1090 apic_nproc++;
1091 } else if (apic_nproc == NCPU && !warned) {
1092 cmn_err(CE_WARN, "%s: CPU limit "
1093 "exceeded"
1094 #if !defined(__amd64)
1095 " for 32-bit mode"
1096 #endif
1097 "; Solaris will use %d CPUs.",
1098 psm_name, NCPU);
1099 warned = 1;
1100 }
1101
1102 }
1103 procp++;
1104 }
1105 apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1106 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1107 kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1108 return (PSM_FAILURE);
1109 }
1110
1111 /*LINTED: pointer cast may result in improper alignment */
1112 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1113
1114 /*
1115 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1116 * if we're bypassing this information, it has already been filled
1117 * in by acpi_probe(), so don't overwrite it.
1118 */
1119 if (!bypass_cpus_and_ioapics)
1120 apic_nproc = 1;
1121
1122 while (procp->proc_entry == APIC_CPU_ENTRY) {
1123 /* check whether the cpu exists or not */
1124 if (!bypass_cpus_and_ioapics &&
1125 procp->proc_cpuflags & CPUFLAGS_EN) {
1126 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1127 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1128 apic_cpus[0].aci_local_id = procp->proc_apicid;
1129 if (apic_cpus[0].aci_local_id !=
1130 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) {
1131 return (PSM_FAILURE);
1132 }
1133 apic_cpus[0].aci_local_ver =
1134 procp->proc_version;
1135 } else if (apic_nproc < NCPU && use_mp &&
1136 apic_nproc < boot_ncpus) {
1137 apic_cpus[apic_nproc].aci_local_id =
1138 procp->proc_apicid;
1139
1140 apic_cpus[apic_nproc].aci_local_ver =
1141 procp->proc_version;
1142 apic_nproc++;
1143
1144 }
1145 }
1146 procp++;
1147 }
1148
1149 /*
1150 * Save start of bus entries for later use.
1151 * Get EISA level cntrl if EISA bus is present.
1152 * Also get the CPI bus id for single CPI bus case
1153 */
1154 apic_busp = busp = (struct apic_bus *)procp;
1155 while (busp->bus_entry == APIC_BUS_ENTRY) {
1156 lid = apic_find_bus_type((char *)&busp->bus_str1);
1157 if (lid == BUS_EISA) {
1158 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1159 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1160 } else if (lid == BUS_PCI) {
1161 /*
1162 * apic_single_pci_busid will be used only if
1163 * apic_pic_bus_total is equal to 1
1164 */
1165 apic_pci_bus_total++;
1166 apic_single_pci_busid = busp->bus_id;
1167 }
1168 busp++;
1169 }
1170
1171 ioapicp = (struct apic_io_entry *)busp;
1172
1173 if (!bypass_cpus_and_ioapics)
1174 apic_io_max = 0;
1175 do {
1176 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1177 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1178 apic_io_id[apic_io_max] = ioapicp->io_apicid;
1179 apic_io_ver[apic_io_max] = ioapicp->io_version;
1180 apicioadr[apic_io_max] =
1181 (void *)mapin_ioapic(
1182 (uint32_t)ioapicp->io_apic_addr,
1183 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1184
1185 if (!apicioadr[apic_io_max])
1186 return (PSM_FAILURE);
1187
1188 ioapic_mask_workaround[apic_io_max] =
1189 apic_is_ioapic_AMD_813x(
1190 ioapicp->io_apic_addr);
1191
1192 ioapic_ix = apic_io_max;
1193 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1194 hid = (uchar_t)(id >> 24);
1195
1196 if (hid != apic_io_id[apic_io_max]) {
1197 if (apic_io_id[apic_io_max] == 0)
1198 apic_io_id[apic_io_max] = hid;
1199 else {
1200 /*
1201 * set ioapic id to whatever
1202 * reported by MPS
1203 *
1204 * may not need to set index
1205 * again ???
1206 * take it out and try
1207 */
1208
1209 id = ((uint32_t)
1210 apic_io_id[apic_io_max]) <<
1211 24;
1212
1213 ioapic_write(ioapic_ix,
1214 APIC_ID_CMD, id);
1215 }
1216 }
1217 apic_io_max++;
1218 }
1219 }
1220 ioapicp++;
1221 } while (ioapicp->io_entry == APIC_IO_ENTRY);
1222
1223 apic_io_intrp = (struct apic_io_intr *)ioapicp;
1224
1225 intrp = apic_io_intrp;
1226 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1227 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1228 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1229 apic_irq_translate = 1;
1230 break;
1231 }
1232 intrp++;
1233 }
1234
1235 return (PSM_SUCCESS);
1236 }
1237
1238 boolean_t
1239 apic_cpu_in_range(int cpu)
1240 {
1241 cpu &= ~IRQ_USER_BOUND;
1242 /* Check whether cpu id is in valid range. */
1243 if (cpu < 0 || cpu >= apic_nproc) {
1244 return (B_FALSE);
1245 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1246 /*
1247 * Check whether cpuid is in valid range if CPU DR is enabled.
1248 */
1249 return (B_FALSE);
1250 } else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1251 return (B_FALSE);
1252 }
1253
1254 return (B_TRUE);
1255 }
1256
1257 processorid_t
1258 apic_get_next_bind_cpu(void)
1259 {
1260 int i, count;
1261 processorid_t cpuid = 0;
1262
1263 for (count = 0; count < apic_nproc; count++) {
1264 if (apic_next_bind_cpu >= apic_nproc) {
1265 apic_next_bind_cpu = 0;
1266 }
1267 i = apic_next_bind_cpu++;
1268 if (apic_cpu_in_range(i)) {
1269 cpuid = i;
1270 break;
1271 }
1272 }
1273
1274 return (cpuid);
1275 }
1276
1277 uint16_t
1278 apic_get_apic_version()
1279 {
1280 int i;
1281 uchar_t min_io_apic_ver = 0;
1282 static uint16_t version; /* Cache as value is constant */
1283 static boolean_t found = B_FALSE; /* Accomodate zero version */
1284
1285 if (found == B_FALSE) {
1286 found = B_TRUE;
1287
1288 /*
1289 * Don't assume all IO APICs in the system are the same.
1290 *
1291 * Set to the minimum version.
1292 */
1293 for (i = 0; i < apic_io_max; i++) {
1294 if ((apic_io_ver[i] != 0) &&
1295 ((min_io_apic_ver == 0) ||
1296 (min_io_apic_ver >= apic_io_ver[i])))
1297 min_io_apic_ver = apic_io_ver[i];
1298 }
1299
1300 /* Assume all local APICs are of the same version. */
1301 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1302 }
1303 return (version);
1304 }
1305
1306 static struct apic_mpfps_hdr *
1307 apic_find_fps_sig(caddr_t cptr, int len)
1308 {
1309 int i;
1310
1311 /* Look for the pattern "_MP_" */
1312 for (i = 0; i < len; i += 16) {
1313 if ((*(cptr+i) == '_') &&
1314 (*(cptr+i+1) == 'M') &&
1315 (*(cptr+i+2) == 'P') &&
1316 (*(cptr+i+3) == '_'))
1317 /*LINTED: pointer cast may result in improper alignment */
1318 return ((struct apic_mpfps_hdr *)(cptr + i));
1319 }
1320 return (NULL);
1321 }
1322
1323 static int
1324 apic_checksum(caddr_t bptr, int len)
1325 {
1326 int i;
1327 uchar_t cksum;
1328
1329 cksum = 0;
1330 for (i = 0; i < len; i++)
1331 cksum += *bptr++;
1332 return ((int)cksum);
1333 }
1334
1335 /*
1336 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1337 * needs special handling. We may need to chase up the device tree,
1338 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1339 * to find the IPIN at the root bus that relates to the IPIN on the
1340 * subsidiary bus (for ACPI or MP). We may, however, have an entry
1341 * in the MP table or the ACPI namespace for this device itself.
1342 * We handle both cases in the search below.
1343 */
1344 /* this is the non-acpi version */
1345 int
1346 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1347 struct apic_io_intr **intrp)
1348 {
1349 dev_info_t *dipp, *dip;
1350 int pci_irq;
1351 ddi_acc_handle_t cfg_handle;
1352 int bridge_devno, bridge_bus;
1353 int ipin;
1354
1355 dip = idip;
1356
1357 /*CONSTCOND*/
1358 while (1) {
1359 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1360 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1361 return (-1);
1362 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1363 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1364 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1365 pci_config_teardown(&cfg_handle);
1366 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1367 NULL) != 0)
1368 return (-1);
1369 /*
1370 * This is the rotating scheme documented in the
1371 * PCI-to-PCI spec. If the PCI-to-PCI bridge is
1372 * behind another PCI-to-PCI bridge, then it needs
1373 * to keep ascending until an interrupt entry is
1374 * found or the root is reached.
1375 */
1376 ipin = (child_devno + child_ipin) % PCI_INTD;
1377 if (bridge_bus == 0 && apic_pci_bus_total == 1)
1378 bridge_bus = (int)apic_single_pci_busid;
1379 pci_irq = ((bridge_devno & 0x1f) << 2) |
1380 (ipin & 0x3);
1381 if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1382 bridge_bus)) != NULL) {
1383 return (pci_irq);
1384 }
1385 dip = dipp;
1386 child_devno = bridge_devno;
1387 child_ipin = ipin;
1388 } else {
1389 pci_config_teardown(&cfg_handle);
1390 return (-1);
1391 }
1392 }
1393 /*LINTED: function will not fall off the bottom */
1394 }
1395
1396 uchar_t
1397 acpi_find_ioapic(int irq)
1398 {
1399 int i;
1400
1401 for (i = 0; i < apic_io_max; i++) {
1402 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1403 return ((uchar_t)i);
1404 }
1405 return (0xFF); /* shouldn't happen */
1406 }
1407
1408 /*
1409 * See if two irqs are compatible for sharing a vector.
1410 * Currently we only support sharing of PCI devices.
1411 */
1412 static int
1413 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1414 {
1415 uint_t level1, po1;
1416 uint_t level2, po2;
1417
1418 /* Assume active high by default */
1419 po1 = 0;
1420 po2 = 0;
1421
1422 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1423 return (0);
1424
1425 if (iflag1.intr_el == INTR_EL_CONFORM)
1426 level1 = AV_LEVEL;
1427 else
1428 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1429
1430 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1431 (iflag1.intr_po == INTR_PO_CONFORM)))
1432 po1 = AV_ACTIVE_LOW;
1433
1434 if (iflag2.intr_el == INTR_EL_CONFORM)
1435 level2 = AV_LEVEL;
1436 else
1437 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1438
1439 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1440 (iflag2.intr_po == INTR_PO_CONFORM)))
1441 po2 = AV_ACTIVE_LOW;
1442
1443 if ((level1 == level2) && (po1 == po2))
1444 return (1);
1445
1446 return (0);
1447 }
1448
1449 struct apic_io_intr *
1450 apic_find_io_intr_w_busid(int irqno, int busid)
1451 {
1452 struct apic_io_intr *intrp;
1453
1454 /*
1455 * It can have more than 1 entry with same source bus IRQ,
1456 * but unique with the source bus id
1457 */
1458 intrp = apic_io_intrp;
1459 if (intrp != NULL) {
1460 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1461 if (intrp->intr_irq == irqno &&
1462 intrp->intr_busid == busid &&
1463 intrp->intr_type == IO_INTR_INT)
1464 return (intrp);
1465 intrp++;
1466 }
1467 }
1468 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1469 "busid %x:%x\n", irqno, busid));
1470 return (NULL);
1471 }
1472
1473
1474 struct mps_bus_info {
1475 char *bus_name;
1476 int bus_id;
1477 } bus_info_array[] = {
1478 "ISA ", BUS_ISA,
1479 "PCI ", BUS_PCI,
1480 "EISA ", BUS_EISA,
1481 "XPRESS", BUS_XPRESS,
1482 "PCMCIA", BUS_PCMCIA,
1483 "VL ", BUS_VL,
1484 "CBUS ", BUS_CBUS,
1485 "CBUSII", BUS_CBUSII,
1486 "FUTURE", BUS_FUTURE,
1487 "INTERN", BUS_INTERN,
1488 "MBI ", BUS_MBI,
1489 "MBII ", BUS_MBII,
1490 "MPI ", BUS_MPI,
1491 "MPSA ", BUS_MPSA,
1492 "NUBUS ", BUS_NUBUS,
1493 "TC ", BUS_TC,
1494 "VME ", BUS_VME,
1495 "PCI-E ", BUS_PCIE
1496 };
1497
1498 static int
1499 apic_find_bus_type(char *bus)
1500 {
1501 int i = 0;
1502
1503 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1504 if (strncmp(bus, bus_info_array[i].bus_name,
1505 strlen(bus_info_array[i].bus_name)) == 0)
1506 return (bus_info_array[i].bus_id);
1507 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1508 return (0);
1509 }
1510
1511 static int
1512 apic_find_bus(int busid)
1513 {
1514 struct apic_bus *busp;
1515
1516 busp = apic_busp;
1517 while (busp->bus_entry == APIC_BUS_ENTRY) {
1518 if (busp->bus_id == busid)
1519 return (apic_find_bus_type((char *)&busp->bus_str1));
1520 busp++;
1521 }
1522 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1523 return (0);
1524 }
1525
1526 int
1527 apic_find_bus_id(int bustype)
1528 {
1529 struct apic_bus *busp;
1530
1531 busp = apic_busp;
1532 while (busp->bus_entry == APIC_BUS_ENTRY) {
1533 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1534 return (busp->bus_id);
1535 busp++;
1536 }
1537 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1538 bustype));
1539 return (-1);
1540 }
1541
1542 /*
1543 * Check if a particular irq need to be reserved for any io_intr
1544 */
1545 static struct apic_io_intr *
1546 apic_find_io_intr(int irqno)
1547 {
1548 struct apic_io_intr *intrp;
1549
1550 intrp = apic_io_intrp;
1551 if (intrp != NULL) {
1552 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1553 if (intrp->intr_irq == irqno &&
1554 intrp->intr_type == IO_INTR_INT)
1555 return (intrp);
1556 intrp++;
1557 }
1558 }
1559 return (NULL);
1560 }
1561
1562 /*
1563 * Check if the given ioapicindex intin combination has already been assigned
1564 * an irq. If so return irqno. Else -1
1565 */
1566 int
1567 apic_find_intin(uchar_t ioapic, uchar_t intin)
1568 {
1569 apic_irq_t *irqptr;
1570 int i;
1571
1572 /* find ioapic and intin in the apic_irq_table[] and return the index */
1573 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1574 irqptr = apic_irq_table[i];
1575 while (irqptr) {
1576 if ((irqptr->airq_mps_intr_index >= 0) &&
1577 (irqptr->airq_intin_no == intin) &&
1578 (irqptr->airq_ioapicindex == ioapic)) {
1579 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1580 "entry for ioapic:intin %x:%x "
1581 "shared interrupts ?", ioapic, intin));
1582 return (i);
1583 }
1584 irqptr = irqptr->airq_next;
1585 }
1586 }
1587 return (-1);
1588 }
1589
1590 int
1591 apic_allocate_irq(int irq)
1592 {
1593 int freeirq, i;
1594
1595 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1)
1596 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1597 (irq - 1))) == -1) {
1598 /*
1599 * if BIOS really defines every single irq in the mps
1600 * table, then don't worry about conflicting with
1601 * them, just use any free slot in apic_irq_table
1602 */
1603 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1604 if ((apic_irq_table[i] == NULL) ||
1605 apic_irq_table[i]->airq_mps_intr_index ==
1606 FREE_INDEX) {
1607 freeirq = i;
1608 break;
1609 }
1610 }
1611 if (freeirq == -1) {
1612 /* This shouldn't happen, but just in case */
1613 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1614 return (-1);
1615 }
1616 }
1617 if (apic_irq_table[freeirq] == NULL) {
1618 apic_irq_table[freeirq] =
1619 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1620 if (apic_irq_table[freeirq] == NULL) {
1621 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1622 psm_name);
1623 return (-1);
1624 }
1625 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1626 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1627 }
1628 return (freeirq);
1629 }
1630
1631 static int
1632 apic_find_free_irq(int start, int end)
1633 {
1634 int i;
1635
1636 for (i = start; i <= end; i++)
1637 /* Check if any I/O entry needs this IRQ */
1638 if (apic_find_io_intr(i) == NULL) {
1639 /* Then see if it is free */
1640 if ((apic_irq_table[i] == NULL) ||
1641 (apic_irq_table[i]->airq_mps_intr_index ==
1642 FREE_INDEX)) {
1643 return (i);
1644 }
1645 }
1646 return (-1);
1647 }
1648
1649 /*
1650 * compute the polarity, trigger mode and vector for programming into
1651 * the I/O apic and record in airq_rdt_entry.
1652 */
1653 void
1654 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1655 {
1656 int ioapicindex, bus_type, vector;
1657 short intr_index;
1658 uint_t level, po, io_po;
1659 struct apic_io_intr *iointrp;
1660
1661 intr_index = irqptr->airq_mps_intr_index;
1662 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1663 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1664 (void *)irqptr->airq_dip, irqptr->airq_vector));
1665
1666 if (intr_index == RESERVE_INDEX) {
1667 apic_error |= APIC_ERR_INVALID_INDEX;
1668 return;
1669 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1670 return;
1671 }
1672
1673 vector = irqptr->airq_vector;
1674 ioapicindex = irqptr->airq_ioapicindex;
1675 /* Assume edge triggered by default */
1676 level = 0;
1677 /* Assume active high by default */
1678 po = 0;
1679
1680 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1681 ASSERT(irq < 16);
1682 if (eisa_level_intr_mask & (1 << irq))
1683 level = AV_LEVEL;
1684 if (intr_index == FREE_INDEX && apic_defconf == 0)
1685 apic_error |= APIC_ERR_INVALID_INDEX;
1686 } else if (intr_index == ACPI_INDEX) {
1687 bus_type = irqptr->airq_iflag.bustype;
1688 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1689 if (bus_type == BUS_PCI)
1690 level = AV_LEVEL;
1691 } else
1692 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1693 AV_LEVEL : 0;
1694 if (level &&
1695 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1696 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1697 bus_type == BUS_PCI)))
1698 po = AV_ACTIVE_LOW;
1699 } else {
1700 iointrp = apic_io_intrp + intr_index;
1701 bus_type = apic_find_bus(iointrp->intr_busid);
1702 if (iointrp->intr_el == INTR_EL_CONFORM) {
1703 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1704 level = AV_LEVEL;
1705 else if (bus_type == BUS_PCI)
1706 level = AV_LEVEL;
1707 } else
1708 level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1709 AV_LEVEL : 0;
1710 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1711 (iointrp->intr_po == INTR_PO_CONFORM &&
1712 bus_type == BUS_PCI)))
1713 po = AV_ACTIVE_LOW;
1714 }
1715 if (level)
1716 apic_level_intr[irq] = 1;
1717 /*
1718 * The 82489DX External APIC cannot do active low polarity interrupts.
1719 */
1720 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1721 io_po = po;
1722 else
1723 io_po = 0;
1724
1725 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1726 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1727 "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1728 irqptr->airq_intin_no, level, io_po, vector,
1729 irqptr->airq_cpu);
1730
1731 irqptr->airq_rdt_entry = level|io_po|vector;
1732 }
1733
1734 int
1735 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1736 int ipin, int *pci_irqp, iflag_t *intr_flagp)
1737 {
1738
1739 int status;
1740 acpi_psm_lnk_t acpipsmlnk;
1741
1742 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1743 intr_flagp)) == ACPI_PSM_SUCCESS) {
1744 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1745 "from cache for device %s, instance #%d\n", psm_name,
1746 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1747 return (status);
1748 }
1749
1750 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1751
1752 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1753 &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1754 APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1755 " acpi_translate_pci_irq failed for device %s, instance"
1756 " #%d", psm_name, ddi_get_name(dip),
1757 ddi_get_instance(dip)));
1758 return (status);
1759 }
1760
1761 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1762 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1763 intr_flagp);
1764 if (status != ACPI_PSM_SUCCESS) {
1765 status = acpi_get_current_irq_resource(&acpipsmlnk,
1766 pci_irqp, intr_flagp);
1767 }
1768 }
1769
1770 if (status == ACPI_PSM_SUCCESS) {
1771 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1772 intr_flagp, &acpipsmlnk);
1773
1774 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1775 "new irq %d for device %s, instance #%d\n", psm_name,
1776 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1777 }
1778
1779 return (status);
1780 }
1781
1782 /*
1783 * Adds an entry to the irq list passed in, and returns the new list.
1784 * Entries are added in priority order (lower numerical priorities are
1785 * placed closer to the head of the list)
1786 */
1787 static prs_irq_list_t *
1788 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1789 iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1790 {
1791 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1792
1793 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1794
1795 newent->list_prio = priority;
1796 newent->irq = irq;
1797 newent->intrflags = *iflagp;
1798 newent->prsprv = *prsprvp;
1799 /* ->next is NULL from kmem_zalloc */
1800
1801 /*
1802 * New list -- return the new entry as the list.
1803 */
1804 if (listp == NULL)
1805 return (newent);
1806
1807 /*
1808 * Save original list pointer for return (since we're not modifying
1809 * the head)
1810 */
1811 origlistp = listp;
1812
1813 /*
1814 * Insertion sort, with entries with identical keys stored AFTER
1815 * existing entries (the less-than-or-equal test of priority does
1816 * this for us).
1817 */
1818 while (listp != NULL && listp->list_prio <= priority) {
1819 prevp = listp;
1820 listp = listp->next;
1821 }
1822
1823 newent->next = listp;
1824
1825 if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1826 return (newent);
1827 } else {
1828 prevp->next = newent;
1829 return (origlistp);
1830 }
1831 }
1832
1833 /*
1834 * Frees the list passed in, deallocating all memory and leaving *listpp
1835 * set to NULL.
1836 */
1837 static void
1838 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1839 {
1840 struct prs_irq_list_ent *nextp;
1841
1842 ASSERT(listpp != NULL);
1843
1844 while (*listpp != NULL) {
1845 nextp = (*listpp)->next;
1846 kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1847 *listpp = nextp;
1848 }
1849 }
1850
1851 /*
1852 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1853 * irqs returned by the link device's _PRS method. The irqs are chosen
1854 * to minimize contention in situations where the interrupt link device
1855 * can be programmed to steer interrupts to different interrupt controller
1856 * inputs (some of which may already be in use). The list is sorted in order
1857 * of irqs to use, with the highest priority given to interrupt controller
1858 * inputs that are not shared. When an interrupt controller input
1859 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1860 * returned list in the order that minimizes sharing (thereby ensuring lowest
1861 * possible latency from interrupt trigger time to ISR execution time).
1862 */
1863 static prs_irq_list_t *
1864 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1865 int crs_irq)
1866 {
1867 int32_t irq;
1868 int i;
1869 prs_irq_list_t *prsirqlistp = NULL;
1870 iflag_t iflags;
1871
1872 while (irqlistent != NULL) {
1873 irqlistent->intr_flags.bustype = BUS_PCI;
1874
1875 for (i = 0; i < irqlistent->num_irqs; i++) {
1876
1877 irq = irqlistent->irqs[i];
1878
1879 if (irq <= 0) {
1880 /* invalid irq number */
1881 continue;
1882 }
1883
1884 if ((irq < 16) && (apic_reserved_irqlist[irq]))
1885 continue;
1886
1887 if ((apic_irq_table[irq] == NULL) ||
1888 (apic_irq_table[irq]->airq_dip == dip)) {
1889
1890 prsirqlistp = acpi_insert_prs_irq_ent(
1891 prsirqlistp, 0 /* Highest priority */, irq,
1892 &irqlistent->intr_flags,
1893 &irqlistent->acpi_prs_prv);
1894
1895 /*
1896 * If we do not prefer the current irq from _CRS
1897 * or if we do and this irq is the same as the
1898 * current irq from _CRS, this is the one
1899 * to pick.
1900 */
1901 if (!(apic_prefer_crs) || (irq == crs_irq)) {
1902 return (prsirqlistp);
1903 }
1904 continue;
1905 }
1906
1907 /*
1908 * Edge-triggered interrupts cannot be shared
1909 */
1910 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1911 continue;
1912
1913 /*
1914 * To work around BIOSes that contain incorrect
1915 * interrupt polarity information in interrupt
1916 * descriptors returned by _PRS, we assume that
1917 * the polarity of the other device sharing this
1918 * interrupt controller input is compatible.
1919 * If it's not, the caller will catch it when
1920 * the caller invokes the link device's _CRS method
1921 * (after invoking its _SRS method).
1922 */
1923 iflags = irqlistent->intr_flags;
1924 iflags.intr_po =
1925 apic_irq_table[irq]->airq_iflag.intr_po;
1926
1927 if (!acpi_intr_compatible(iflags,
1928 apic_irq_table[irq]->airq_iflag)) {
1929 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
1930 "not compatible [%x:%x:%x !~ %x:%x:%x]",
1931 psm_name, irq,
1932 iflags.intr_po,
1933 iflags.intr_el,
1934 iflags.bustype,
1935 apic_irq_table[irq]->airq_iflag.intr_po,
1936 apic_irq_table[irq]->airq_iflag.intr_el,
1937 apic_irq_table[irq]->airq_iflag.bustype));
1938 continue;
1939 }
1940
1941 /*
1942 * If we prefer the irq from _CRS, no need
1943 * to search any further (and make sure
1944 * to add this irq with the highest priority
1945 * so it's tried first).
1946 */
1947 if (crs_irq == irq && apic_prefer_crs) {
1948
1949 return (acpi_insert_prs_irq_ent(
1950 prsirqlistp,
1951 0 /* Highest priority */,
1952 irq, &iflags,
1953 &irqlistent->acpi_prs_prv));
1954 }
1955
1956 /*
1957 * Priority is equal to the share count (lower
1958 * share count is higher priority). Note that
1959 * the intr flags passed in here are the ones we
1960 * changed above -- if incorrect, it will be
1961 * caught by the caller's _CRS flags comparison.
1962 */
1963 prsirqlistp = acpi_insert_prs_irq_ent(
1964 prsirqlistp,
1965 apic_irq_table[irq]->airq_share, irq,
1966 &iflags, &irqlistent->acpi_prs_prv);
1967 }
1968
1969 /* Go to the next irqlist entry */
1970 irqlistent = irqlistent->next;
1971 }
1972
1973 return (prsirqlistp);
1974 }
1975
1976 /*
1977 * Configures the irq for the interrupt link device identified by
1978 * acpipsmlnkp.
1979 *
1980 * Gets the current and the list of possible irq settings for the
1981 * device. If apic_unconditional_srs is not set, and the current
1982 * resource setting is in the list of possible irq settings,
1983 * current irq resource setting is passed to the caller.
1984 *
1985 * Otherwise, picks an irq number from the list of possible irq
1986 * settings, and sets the irq of the device to this value.
1987 * If prefer_crs is set, among a set of irq numbers in the list that have
1988 * the least number of devices sharing the interrupt, we pick current irq
1989 * resource setting if it is a member of this set.
1990 *
1991 * Passes the irq number in the value pointed to by pci_irqp, and
1992 * polarity and sensitivity in the structure pointed to by dipintrflagp
1993 * to the caller.
1994 *
1995 * Note that if setting the irq resource failed, but successfuly obtained
1996 * the current irq resource settings, passes the current irq resources
1997 * and considers it a success.
1998 *
1999 * Returns:
2000 * ACPI_PSM_SUCCESS on success.
2001 *
2002 * ACPI_PSM_FAILURE if an error occured during the configuration or
2003 * if a suitable irq was not found for this device, or if setting the
2004 * irq resource and obtaining the current resource fails.
2005 *
2006 */
2007 static int
2008 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2009 int *pci_irqp, iflag_t *dipintr_flagp)
2010 {
2011 int32_t irq;
2012 int cur_irq = -1;
2013 acpi_irqlist_t *irqlistp;
2014 prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2015 boolean_t found_irq = B_FALSE;
2016
2017 dipintr_flagp->bustype = BUS_PCI;
2018
2019 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2020 == ACPI_PSM_FAILURE) {
2021 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2022 "or assign IRQ for device %s, instance #%d: The system was "
2023 "unable to get the list of potential IRQs from ACPI.",
2024 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2025
2026 return (ACPI_PSM_FAILURE);
2027 }
2028
2029 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2030 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2031 (cur_irq > 0)) {
2032 /*
2033 * If an IRQ is set in CRS and that IRQ exists in the set
2034 * returned from _PRS, return that IRQ, otherwise print
2035 * a warning
2036 */
2037
2038 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2039 == ACPI_PSM_SUCCESS) {
2040
2041 ASSERT(pci_irqp != NULL);
2042 *pci_irqp = cur_irq;
2043 acpi_free_irqlist(irqlistp);
2044 return (ACPI_PSM_SUCCESS);
2045 }
2046
2047 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2048 "current irq %d for device %s, instance #%d in ACPI's "
2049 "list of possible irqs for this device. Picking one from "
2050 " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2051 ddi_get_instance(dip)));
2052 }
2053
2054 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2055 cur_irq)) == NULL) {
2056
2057 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2058 "suitable irq from the list of possible irqs for device "
2059 "%s, instance #%d in ACPI's list of possible irqs",
2060 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2061
2062 acpi_free_irqlist(irqlistp);
2063 return (ACPI_PSM_FAILURE);
2064 }
2065
2066 acpi_free_irqlist(irqlistp);
2067
2068 for (prs_irq_entp = prs_irq_listp;
2069 prs_irq_entp != NULL && found_irq == B_FALSE;
2070 prs_irq_entp = prs_irq_entp->next) {
2071
2072 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2073 irq = prs_irq_entp->irq;
2074
2075 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2076 "device %s instance #%d\n", psm_name, irq,
2077 ddi_get_name(dip), ddi_get_instance(dip)));
2078
2079 if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2080 == ACPI_PSM_SUCCESS) {
2081 /*
2082 * setting irq was successful, check to make sure CRS
2083 * reflects that. If CRS does not agree with what we
2084 * set, return the irq that was set.
2085 */
2086
2087 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2088 dipintr_flagp) == ACPI_PSM_SUCCESS) {
2089
2090 if (cur_irq != irq)
2091 APIC_VERBOSE_IRQ((CE_WARN,
2092 "!%s: IRQ resource set "
2093 "(irqno %d) for device %s "
2094 "instance #%d, differs from "
2095 "current setting irqno %d",
2096 psm_name, irq, ddi_get_name(dip),
2097 ddi_get_instance(dip), cur_irq));
2098 } else {
2099 /*
2100 * On at least one system, there was a bug in
2101 * a DSDT method called by _STA, causing _STA to
2102 * indicate that the link device was disabled
2103 * (when, in fact, it was enabled). Since _SRS
2104 * succeeded, assume that _CRS is lying and use
2105 * the iflags from this _PRS interrupt choice.
2106 * If we're wrong about the flags, the polarity
2107 * will be incorrect and we may get an interrupt
2108 * storm, but there's not much else we can do
2109 * at this point.
2110 */
2111 *dipintr_flagp = prs_irq_entp->intrflags;
2112 }
2113
2114 /*
2115 * Return the irq that was set, and not what _CRS
2116 * reports, since _CRS has been seen to return
2117 * different IRQs than what was passed to _SRS on some
2118 * systems (and just not return successfully on others).
2119 */
2120 cur_irq = irq;
2121 found_irq = B_TRUE;
2122 } else {
2123 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2124 "irq %d failed for device %s instance #%d",
2125 psm_name, irq, ddi_get_name(dip),
2126 ddi_get_instance(dip)));
2127
2128 if (cur_irq == -1) {
2129 acpi_destroy_prs_irq_list(&prs_irq_listp);
2130 return (ACPI_PSM_FAILURE);
2131 }
2132 }
2133 }
2134
2135 acpi_destroy_prs_irq_list(&prs_irq_listp);
2136
2137 if (!found_irq)
2138 return (ACPI_PSM_FAILURE);
2139
2140 ASSERT(pci_irqp != NULL);
2141 *pci_irqp = cur_irq;
2142 return (ACPI_PSM_SUCCESS);
2143 }
2144
2145 void
2146 ioapic_disable_redirection()
2147 {
2148 int ioapic_ix;
2149 int intin_max;
2150 int intin_ix;
2151
2152 /* Disable the I/O APIC redirection entries */
2153 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2154
2155 /* Bits 23-16 define the maximum redirection entries */
2156 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2157 & 0xff;
2158
2159 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2160 /*
2161 * The assumption here is that this is safe, even for
2162 * systems with IOAPICs that suffer from the hardware
2163 * erratum because all devices have been quiesced before
2164 * this function is called from apic_shutdown()
2165 * (or equivalent). If that assumption turns out to be
2166 * false, this mask operation can induce the same
2167 * erratum result we're trying to avoid.
2168 */
2169 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2170 AV_MASK);
2171 }
2172 }
2173 }
2174
2175 /*
2176 * Looks for an IOAPIC with the specified physical address in the /ioapics
2177 * node in the device tree (created by the PCI enumerator).
2178 */
2179 static boolean_t
2180 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2181 {
2182 /*
2183 * Look in /ioapics, for the ioapic with
2184 * the physical address given
2185 */
2186 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2187 dev_info_t *ioapic_child;
2188 boolean_t rv = B_FALSE;
2189 int vid, did;
2190 uint64_t ioapic_paddr;
2191 boolean_t done = B_FALSE;
2192
2193 if (ioapicsnode == NULL)
2194 return (B_FALSE);
2195
2196 /* Load first child: */
2197 ioapic_child = ddi_get_child(ioapicsnode);
2198 while (!done && ioapic_child != 0) { /* Iterate over children */
2199
2200 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2201 ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2202 != 0 && physaddr == ioapic_paddr) {
2203
2204 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2205 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2206
2207 if (vid == VENID_AMD) {
2208
2209 did = ddi_prop_get_int(DDI_DEV_T_ANY,
2210 ioapic_child, DDI_PROP_DONTPASS,
2211 IOAPICS_PROP_DEVID, 0);
2212
2213 if (did == DEVID_8131_IOAPIC ||
2214 did == DEVID_8132_IOAPIC) {
2215 rv = B_TRUE;
2216 done = B_TRUE;
2217 }
2218 }
2219 }
2220
2221 if (!done)
2222 ioapic_child = ddi_get_next_sibling(ioapic_child);
2223 }
2224
2225 /* The ioapics node was held by ddi_find_devinfo, so release it */
2226 ndi_rele_devi(ioapicsnode);
2227 return (rv);
2228 }
2229
2230 struct apic_state {
2231 int32_t as_task_reg;
2232 int32_t as_dest_reg;
2233 int32_t as_format_reg;
2234 int32_t as_local_timer;
2235 int32_t as_pcint_vect;
2236 int32_t as_int_vect0;
2237 int32_t as_int_vect1;
2238 int32_t as_err_vect;
2239 int32_t as_init_count;
2240 int32_t as_divide_reg;
2241 int32_t as_spur_int_reg;
2242 uint32_t as_ioapic_ids[MAX_IO_APIC];
2243 };
2244
2245
2246 static int
2247 apic_acpi_enter_apicmode(void)
2248 {
2249 ACPI_OBJECT_LIST arglist;
2250 ACPI_OBJECT arg;
2251 ACPI_STATUS status;
2252
2253 /* Setup parameter object */
2254 arglist.Count = 1;
2255 arglist.Pointer = &arg;
2256 arg.Type = ACPI_TYPE_INTEGER;
2257 arg.Integer.Value = ACPI_APIC_MODE;
2258
2259 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2260 if (ACPI_FAILURE(status))
2261 return (PSM_FAILURE);
2262 else
2263 return (PSM_SUCCESS);
2264 }
2265
2266
2267 static void
2268 apic_save_state(struct apic_state *sp)
2269 {
2270 int i, cpuid;
2271 ulong_t iflag;
2272
2273 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2274 /*
2275 * First the local APIC.
2276 */
2277 sp->as_task_reg = apic_reg_ops->apic_get_pri();
2278 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG);
2279 if (apic_mode == LOCAL_APIC)
2280 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2281 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2282 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2283 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2284 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2285 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2286 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2287 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2288 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2289
2290 /*
2291 * If on the boot processor then save the IOAPICs' IDs
2292 */
2293 if ((cpuid = psm_get_cpu_id()) == 0) {
2294
2295 iflag = intr_clear();
2296 lock_set(&apic_ioapic_lock);
2297
2298 for (i = 0; i < apic_io_max; i++)
2299 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2300
2301 lock_clear(&apic_ioapic_lock);
2302 intr_restore(iflag);
2303 }
2304
2305 /* apic_state() is currently invoked only in Suspend/Resume */
2306 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2307 }
2308
2309 static void
2310 apic_restore_state(struct apic_state *sp)
2311 {
2312 int i;
2313 ulong_t iflag;
2314
2315 /*
2316 * First the local APIC.
2317 */
2318 apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2319 if (apic_mode == LOCAL_APIC) {
2320 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2321 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2322 }
2323 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2324 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2325 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2326 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2327 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2328 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2329 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2330 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2331
2332 /*
2333 * the following only needs to be done once, so we do it on the
2334 * boot processor, since we know that we only have one of those
2335 */
2336 if (psm_get_cpu_id() == 0) {
2337
2338 iflag = intr_clear();
2339 lock_set(&apic_ioapic_lock);
2340
2341 /* Restore IOAPICs' APIC IDs */
2342 for (i = 0; i < apic_io_max; i++) {
2343 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2344 }
2345
2346 lock_clear(&apic_ioapic_lock);
2347 intr_restore(iflag);
2348
2349 /*
2350 * Reenter APIC mode before restoring LNK devices
2351 */
2352 (void) apic_acpi_enter_apicmode();
2353
2354 /*
2355 * restore acpi link device mappings
2356 */
2357 acpi_restore_link_devices();
2358 }
2359 }
2360
2361 /*
2362 * Returns 0 on success
2363 */
2364 int
2365 apic_state(psm_state_request_t *rp)
2366 {
2367 PMD(PMD_SX, ("apic_state "))
2368 switch (rp->psr_cmd) {
2369 case PSM_STATE_ALLOC:
2370 rp->req.psm_state_req.psr_state =
2371 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2372 if (rp->req.psm_state_req.psr_state == NULL)
2373 return (ENOMEM);
2374 rp->req.psm_state_req.psr_state_size =
2375 sizeof (struct apic_state);
2376 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2377 rp->req.psm_state_req.psr_state,
2378 rp->req.psm_state_req.psr_state_size))
2379 return (0);
2380
2381 case PSM_STATE_FREE:
2382 kmem_free(rp->req.psm_state_req.psr_state,
2383 rp->req.psm_state_req.psr_state_size);
2384 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2385 rp->req.psm_state_req.psr_state,
2386 rp->req.psm_state_req.psr_state_size))
2387 return (0);
2388
2389 case PSM_STATE_SAVE:
2390 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2391 rp->req.psm_state_req.psr_state,
2392 rp->req.psm_state_req.psr_state_size))
2393 apic_save_state(rp->req.psm_state_req.psr_state);
2394 return (0);
2395
2396 case PSM_STATE_RESTORE:
2397 apic_restore_state(rp->req.psm_state_req.psr_state);
2398 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2399 rp->req.psm_state_req.psr_state,
2400 rp->req.psm_state_req.psr_state_size))
2401 return (0);
2402
2403 default:
2404 return (EINVAL);
2405 }
2406 }
Unleashed OS