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Unleashed v1.4
[unleashed.git] / usr / src / uts / i86pc / io / mp_platform_common.c
blob79237f08f41dcd047210f453722714cb536a5de5
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2016 Nexenta Systems, Inc.
24 * Copyright (c) 2017 by Delphix. All rights reserved.
25 * Copyright (c) 2018, Joyent, Inc.
26 */
27 /*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
31
32 /*
33 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
34 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
35 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
36 * PSMI 1.5 extensions are supported in Solaris Nevada.
37 * PSMI 1.6 extensions are supported in Solaris Nevada.
38 * PSMI 1.7 extensions are supported in Solaris Nevada.
39 */
40 #define PSMI_1_7
41
42 #include <sys/processor.h>
43 #include <sys/time.h>
44 #include <sys/psm.h>
45 #include <sys/smp_impldefs.h>
46 #include <sys/cram.h>
47 #include <sys/acpi/acpi.h>
48 #include <sys/acpica.h>
49 #include <sys/psm_common.h>
50 #include <sys/apic.h>
51 #include <sys/apic_timer.h>
52 #include <sys/pit.h>
53 #include <sys/ddi.h>
54 #include <sys/sunddi.h>
55 #include <sys/ddi_impldefs.h>
56 #include <sys/pci.h>
57 #include <sys/promif.h>
58 #include <sys/x86_archext.h>
59 #include <sys/cpc_impl.h>
60 #include <sys/uadmin.h>
61 #include <sys/panic.h>
62 #include <sys/debug.h>
63 #include <sys/archsystm.h>
64 #include <sys/trap.h>
65 #include <sys/machsystm.h>
66 #include <sys/cpuvar.h>
67 #include <sys/rm_platter.h>
68 #include <sys/privregs.h>
69 #include <sys/cyclic.h>
70 #include <sys/note.h>
71 #include <sys/pci_intr_lib.h>
72 #include <sys/sunndi.h>
73 #include <sys/hpet.h>
74 #include <sys/clock.h>
75
76 /*
77 * Local Function Prototypes
78 */
79 static int apic_handle_defconf();
80 static int apic_parse_mpct(caddr_t mpct, int bypass);
81 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
82 static int apic_checksum(caddr_t bptr, int len);
83 static int apic_find_bus_type(char *bus);
84 static int apic_find_bus(int busid);
85 static struct apic_io_intr *apic_find_io_intr(int irqno);
86 static int apic_find_free_irq(int start, int end);
87 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
88 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
89 static void apic_free_apic_cpus(void);
90 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
91 static int apic_acpi_enter_apicmode(void);
92
93 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
94 int child_ipin, struct apic_io_intr **intrp);
95 int apic_find_bus_id(int bustype);
96 int apic_find_intin(uchar_t ioapic, uchar_t intin);
97 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
98
99 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
100
101 /* ACPI SCI interrupt configuration; -1 if SCI not used */
102 int apic_sci_vect = -1;
103 iflag_t apic_sci_flags;
104
105 /* ACPI HPET interrupt configuration; -1 if HPET not used */
106 int apic_hpet_vect = -1;
107 iflag_t apic_hpet_flags;
108
109 /*
110 * psm name pointer
111 */
112 char *psm_name;
113
114 /* ACPI support routines */
115 static int acpi_probe(char *);
116 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
117 int *pci_irqp, iflag_t *intr_flagp);
118
119 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
120 int ipin, int *pci_irqp, iflag_t *intr_flagp);
121 uchar_t acpi_find_ioapic(int irq);
122 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
123
124 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
125 int apic_max_reps_clear_pending = 1000;
126
127 int apic_intr_policy = INTR_ROUND_ROBIN;
128
129 int apic_next_bind_cpu = 1; /* For round robin assignment */
130 /* start with cpu 1 */
131
132 /*
133 * If enabled, the distribution works as follows:
134 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
135 * and the irq corresponding to the ipl is also set in the aci_current array.
136 * interrupt exit and setspl (due to soft interrupts) will cause the current
137 * ipl to be be changed. This is cache friendly as these frequently used
138 * paths write into a per cpu structure.
139 *
140 * Sampling is done by checking the structures for all CPUs and incrementing
141 * the busy field of the irq (if any) executing on each CPU and the busy field
142 * of the corresponding CPU.
143 * In periodic mode this is done on every clock interrupt.
144 * In one-shot mode, this is done thru a cyclic with an interval of
145 * apic_redistribute_sample_interval (default 10 milli sec).
146 *
147 * Every apic_sample_factor_redistribution times we sample, we do computations
148 * to decide which interrupt needs to be migrated (see comments
149 * before apic_intr_redistribute().
150 */
151
152 /*
153 * Following 3 variables start as % and can be patched or set using an
154 * API to be defined in future. They will be scaled to
155 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
156 * mode), or 101 in one-shot mode to stagger it away from one sec processing
157 */
158
159 int apic_int_busy_mark = 60;
160 int apic_int_free_mark = 20;
161 int apic_diff_for_redistribution = 10;
162
163 /* sampling interval for interrupt redistribution for dynamic migration */
164 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
165
166 /*
167 * number of times we sample before deciding to redistribute interrupts
168 * for dynamic migration
169 */
170 int apic_sample_factor_redistribution = 101;
171
172 int apic_redist_cpu_skip = 0;
173 int apic_num_imbalance = 0;
174 int apic_num_rebind = 0;
175
176 /*
177 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
178 * allocation of CPU ids is disabled.
179 */
180 int apic_max_nproc = -1;
181 int apic_nproc = 0;
182 size_t apic_cpus_size = 0;
183 int apic_defconf = 0;
184 int apic_irq_translate = 0;
185 int apic_spec_rev = 0;
186 int apic_imcrp = 0;
187
188 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */
189 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
190
191 /*
192 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
193 * will be assigned (via _SRS). If it is not set, use the current
194 * irq setting (via _CRS), but only if that irq is in the set of possible
195 * irqs (returned by _PRS) for the device.
196 */
197 int apic_unconditional_srs = 1;
198
199 /*
200 * For interrupt link devices, if apic_prefer_crs is set when we are
201 * assigning an IRQ resource to a device, prefer the current IRQ setting
202 * over other possible irq settings under same conditions.
203 */
204
205 int apic_prefer_crs = 1;
206
207 uchar_t apic_io_id[MAX_IO_APIC];
208 volatile uint32_t *apicioadr[MAX_IO_APIC];
209 uchar_t apic_io_ver[MAX_IO_APIC];
210 uchar_t apic_io_vectbase[MAX_IO_APIC];
211 uchar_t apic_io_vectend[MAX_IO_APIC];
212 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
213 uint32_t apic_physaddr[MAX_IO_APIC];
214
215 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
216
217 /*
218 * First available slot to be used as IRQ index into the apic_irq_table
219 * for those interrupts (like MSI/X) that don't have a physical IRQ.
220 */
221 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ;
222
223 /*
224 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
225 * and bound elements of cpus_info and the temp_cpu element of irq_struct
226 */
227 lock_t apic_ioapic_lock;
228
229 int apic_io_max = 0; /* no. of i/o apics enabled */
230
231 struct apic_io_intr *apic_io_intrp = NULL;
232 static struct apic_bus *apic_busp;
233
234 uchar_t apic_resv_vector[MAXIPL+1];
235
236 char apic_level_intr[APIC_MAX_VECTOR+1];
237
238 uint32_t eisa_level_intr_mask = 0;
239 /* At least MSB will be set if EISA bus */
240
241 int apic_pci_bus_total = 0;
242 uchar_t apic_single_pci_busid = 0;
243
244 /*
245 * airq_mutex protects additions to the apic_irq_table - the first
246 * pointer and any airq_nexts off of that one. It also protects
247 * apic_max_device_irq & apic_min_device_irq. It also guarantees
248 * that share_id is unique as new ids are generated only when new
249 * irq_t structs are linked in. Once linked in the structs are never
250 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
251 * or allocated. Note that there is a slight gap between allocating in
252 * apic_introp_xlate and programming in addspl.
253 */
254 kmutex_t airq_mutex;
255 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
256 int apic_max_device_irq = 0;
257 int apic_min_device_irq = APIC_MAX_VECTOR;
258
259 typedef struct prs_irq_list_ent {
260 int list_prio;
261 int32_t irq;
262 iflag_t intrflags;
263 acpi_prs_private_t prsprv;
264 struct prs_irq_list_ent *next;
265 } prs_irq_list_t;
266
267
268 /*
269 * ACPI variables
270 */
271 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
272 int apic_enable_acpi = 0;
273
274 /* ACPI Multiple APIC Description Table ptr */
275 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
276
277 /* ACPI Interrupt Source Override Structure ptr */
278 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
279 int acpi_iso_cnt = 0;
280
281 /* ACPI Non-maskable Interrupt Sources ptr */
282 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
283 static int acpi_nmi_scnt = 0;
284 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
285 static int acpi_nmi_ccnt = 0;
286
287 static boolean_t acpi_found_smp_config = B_FALSE;
288
289 /*
290 * The following added to identify a software poweroff method if available.
291 */
292
293 static struct {
294 int poweroff_method;
295 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */
296 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */
297 } apic_mps_ids[] = {
298 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */
299 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */
300 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */
301 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */
302 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */
303 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */
304 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */
305 };
306
307 int apic_poweroff_method = APIC_POWEROFF_NONE;
308
309 /*
310 * Auto-configuration routines
311 */
312
313 /*
314 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
315 * May work with 1.1 - but not guaranteed.
316 * According to the MP Spec, the MP floating pointer structure
317 * will be searched in the order described below:
318 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
319 * 2. Within the last kilobyte of system base memory
320 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
321 * Once we find the right signature with proper checksum, we call
322 * either handle_defconf or parse_mpct to get all info necessary for
323 * subsequent operations.
324 */
325 int
326 apic_probe_common(char *modname)
327 {
328 uint32_t mpct_addr, ebda_start = 0, base_mem_end;
329 caddr_t biosdatap;
330 caddr_t mpct = NULL;
331 caddr_t fptr;
332 int i, mpct_size = 0, mapsize, retval = PSM_FAILURE;
333 ushort_t ebda_seg, base_mem_size;
334 struct apic_mpfps_hdr *fpsp;
335 struct apic_mp_cnf_hdr *hdrp;
336 int bypass_cpu_and_ioapics_in_mptables;
337 int acpi_user_options;
338
339 if (apic_forceload < 0)
340 return (retval);
341
342 /*
343 * Remember who we are
344 */
345 psm_name = modname;
346
347 /* Allow override for MADT-only mode */
348 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
349 "acpi-user-options", 0);
350 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
351
352 /* Allow apic_use_acpi to override MADT-only mode */
353 if (!apic_use_acpi)
354 apic_use_acpi_madt_only = 0;
355
356 retval = acpi_probe(modname);
357
358 /* in UEFI system, there is no BIOS data */
359 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab"))
360 goto apic_ret;
361
362 /*
363 * mapin the bios data area 40:0
364 * 40:13h - two-byte location reports the base memory size
365 * 40:0Eh - two-byte location for the exact starting address of
366 * the EBDA segment for EISA
367 */
368 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
369 if (!biosdatap)
370 goto apic_ret;
371 fpsp = NULL;
372 mapsize = MPFPS_RAM_WIN_LEN;
373 /*LINTED: pointer cast may result in improper alignment */
374 ebda_seg = *((ushort_t *)(biosdatap+0xe));
375 /* check the 1k of EBDA */
376 if (ebda_seg) {
377 ebda_start = ((uint32_t)ebda_seg) << 4;
378 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
379 if (fptr) {
380 if (!(fpsp =
381 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
382 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
383 }
384 }
385 /* If not in EBDA, check the last k of system base memory */
386 if (!fpsp) {
387 /*LINTED: pointer cast may result in improper alignment */
388 base_mem_size = *((ushort_t *)(biosdatap + 0x13));
389
390 if (base_mem_size > 512)
391 base_mem_end = 639 * 1024;
392 else
393 base_mem_end = 511 * 1024;
394 /* if ebda == last k of base mem, skip to check BIOS ROM */
395 if (base_mem_end != ebda_start) {
396
397 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
398 PROT_READ);
399
400 if (fptr) {
401 if (!(fpsp = apic_find_fps_sig(fptr,
402 MPFPS_RAM_WIN_LEN)))
403 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
404 }
405 }
406 }
407 psm_unmap_phys(biosdatap, 0x20);
408
409 /* If still cannot find it, check the BIOS ROM space */
410 if (!fpsp) {
411 mapsize = MPFPS_ROM_WIN_LEN;
412 fptr = psm_map_phys(MPFPS_ROM_WIN_START,
413 MPFPS_ROM_WIN_LEN, PROT_READ);
414 if (fptr) {
415 if (!(fpsp =
416 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
417 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
418 goto apic_ret;
419 }
420 }
421 }
422
423 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
424 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
425 goto apic_ret;
426 }
427
428 apic_spec_rev = fpsp->mpfps_spec_rev;
429 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
430 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
431 goto apic_ret;
432 }
433
434 /* check IMCR is present or not */
435 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
436
437 /* check default configuration (dual CPUs) */
438 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
439 psm_unmap_phys(fptr, mapsize);
440 if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
441 return (retval);
442
443 goto apic_ret;
444 }
445
446 /* MP Configuration Table */
447 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
448
449 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
450
451 /*
452 * Map in enough memory for the MP Configuration Table Header.
453 * Use this table to read the total length of the BIOS data and
454 * map in all the info
455 */
456 /*LINTED: pointer cast may result in improper alignment */
457 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
458 sizeof (struct apic_mp_cnf_hdr), PROT_READ);
459 if (!hdrp)
460 goto apic_ret;
461
462 /* check mp configuration table signature PCMP */
463 if (hdrp->mpcnf_sig != 0x504d4350) {
464 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
465 goto apic_ret;
466 }
467 mpct_size = (int)hdrp->mpcnf_tbl_length;
468
469 apic_set_pwroff_method_from_mpcnfhdr(hdrp);
470
471 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
472
473 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
474 /* This is an ACPI machine No need for further checks */
475 goto apic_ret;
476 }
477
478 /*
479 * Map in the entries for this machine, ie. Processor
480 * Entry Tables, Bus Entry Tables, etc.
481 * They are in fixed order following one another
482 */
483 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
484 if (!mpct)
485 goto apic_ret;
486
487 if (apic_checksum(mpct, mpct_size) != 0)
488 goto apic_fail1;
489
490 /*LINTED: pointer cast may result in improper alignment */
491 hdrp = (struct apic_mp_cnf_hdr *)mpct;
492 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
493 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
494 if (!apicadr)
495 goto apic_fail1;
496
497 /* Parse all information in the tables */
498 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
499 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
500 PSM_SUCCESS) {
501 retval = PSM_SUCCESS;
502 goto apic_ret;
503 }
504
505 apic_fail1:
506 psm_unmap_phys(mpct, mpct_size);
507 mpct = NULL;
508
509 apic_ret:
510 if (retval == PSM_SUCCESS) {
511 extern int apic_ioapic_method_probe();
512
513 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS)
514 return (PSM_SUCCESS);
515 }
516
517 for (i = 0; i < apic_io_max; i++)
518 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
519 if (apic_cpus) {
520 kmem_free(apic_cpus, apic_cpus_size);
521 apic_cpus = NULL;
522 }
523 if (apicadr) {
524 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
525 apicadr = NULL;
526 }
527 if (mpct)
528 psm_unmap_phys(mpct, mpct_size);
529
530 return (retval);
531 }
532
533 static void
534 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
535 {
536 int i;
537
538 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
539 i++) {
540 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
541 strlen(apic_mps_ids[i].oem_id)) == 0) &&
542 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
543 strlen(apic_mps_ids[i].prod_id)) == 0)) {
544
545 apic_poweroff_method = apic_mps_ids[i].poweroff_method;
546 break;
547 }
548 }
549
550 if (apic_debug_mps_id != 0) {
551 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
552 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
553 psm_name,
554 hdrp->mpcnf_oem_str[0],
555 hdrp->mpcnf_oem_str[1],
556 hdrp->mpcnf_oem_str[2],
557 hdrp->mpcnf_oem_str[3],
558 hdrp->mpcnf_oem_str[4],
559 hdrp->mpcnf_oem_str[5],
560 hdrp->mpcnf_oem_str[6],
561 hdrp->mpcnf_oem_str[7],
562 hdrp->mpcnf_prod_str[0],
563 hdrp->mpcnf_prod_str[1],
564 hdrp->mpcnf_prod_str[2],
565 hdrp->mpcnf_prod_str[3],
566 hdrp->mpcnf_prod_str[4],
567 hdrp->mpcnf_prod_str[5],
568 hdrp->mpcnf_prod_str[6],
569 hdrp->mpcnf_prod_str[7],
570 hdrp->mpcnf_prod_str[8],
571 hdrp->mpcnf_prod_str[9],
572 hdrp->mpcnf_prod_str[10],
573 hdrp->mpcnf_prod_str[11]);
574 }
575 }
576
577 static void
578 apic_free_apic_cpus(void)
579 {
580 if (apic_cpus != NULL) {
581 kmem_free(apic_cpus, apic_cpus_size);
582 apic_cpus = NULL;
583 apic_cpus_size = 0;
584 }
585 }
586
587 static int
588 acpi_probe(char *modname)
589 {
590 int i, intmax, index;
591 uint32_t id, ver;
592 int acpi_verboseflags = 0;
593 int madt_seen, madt_size;
594 ACPI_SUBTABLE_HEADER *ap;
595 ACPI_MADT_LOCAL_APIC *mpa;
596 ACPI_MADT_LOCAL_X2APIC *mpx2a;
597 ACPI_MADT_IO_APIC *mia;
598 ACPI_MADT_IO_SAPIC *misa;
599 ACPI_MADT_INTERRUPT_OVERRIDE *mio;
600 ACPI_MADT_NMI_SOURCE *mns;
601 ACPI_MADT_INTERRUPT_SOURCE *mis;
602 ACPI_MADT_LOCAL_APIC_NMI *mlan;
603 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan;
604 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao;
605 int sci;
606 iflag_t sci_flags;
607 volatile uint32_t *ioapic;
608 int ioapic_ix;
609 uint32_t *local_ids;
610 uint32_t *proc_ids;
611 uchar_t hid;
612 int warned = 0;
613
614 if (!apic_use_acpi)
615 return (PSM_FAILURE);
616
617 if (AcpiGetTable(ACPI_SIG_MADT, 1,
618 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) {
619 cmn_err(CE_WARN, "!acpi_probe: No MADT found!");
620 return (PSM_FAILURE);
621 }
622
623 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
624 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
625 if (!apicadr)
626 return (PSM_FAILURE);
627
628 if ((local_ids = kmem_zalloc(NCPU * sizeof (uint32_t),
629 KM_NOSLEEP)) == NULL)
630 return (PSM_FAILURE);
631
632 if ((proc_ids = kmem_zalloc(NCPU * sizeof (uint32_t),
633 KM_NOSLEEP)) == NULL) {
634 kmem_free(local_ids, NCPU * sizeof (uint32_t));
635 return (PSM_FAILURE);
636 }
637
638 id = apic_reg_ops->apic_read(APIC_LID_REG);
639 local_ids[0] = (uchar_t)(id >> 24);
640 apic_nproc = index = 1;
641 apic_io_max = 0;
642
643 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
644 madt_size = acpi_mapic_dtp->Header.Length;
645 madt_seen = sizeof (*acpi_mapic_dtp);
646
647 while (madt_seen < madt_size) {
648 switch (ap->Type) {
649 case ACPI_MADT_TYPE_LOCAL_APIC:
650 mpa = (ACPI_MADT_LOCAL_APIC *) ap;
651 if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
652 if (mpa->Id == 255) {
653 cmn_err(CE_WARN, "!%s: encountered "
654 "invalid entry in MADT: CPU %d "
655 "has Local APIC Id equal to 255 ",
656 psm_name, mpa->ProcessorId);
657 }
658 if (mpa->Id == local_ids[0]) {
659 ASSERT(index == 1);
660 proc_ids[0] = mpa->ProcessorId;
661 } else if (apic_nproc < NCPU && use_mp &&
662 apic_nproc < boot_ncpus) {
663 local_ids[index] = mpa->Id;
664 proc_ids[index] = mpa->ProcessorId;
665 index++;
666 apic_nproc++;
667 } else if (apic_nproc == NCPU && !warned) {
668 cmn_err(CE_WARN, "%s: CPU limit "
669 "exceeded"
670 #if !defined(__amd64)
671 " for 32-bit mode"
672 #endif
673 "; Solaris will use %d CPUs.",
674 psm_name, NCPU);
675 warned = 1;
676 }
677 }
678 break;
679
680 case ACPI_MADT_TYPE_IO_APIC:
681 mia = (ACPI_MADT_IO_APIC *) ap;
682 if (apic_io_max < MAX_IO_APIC) {
683 ioapic_ix = apic_io_max;
684 apic_io_id[apic_io_max] = mia->Id;
685 apic_io_vectbase[apic_io_max] =
686 mia->GlobalIrqBase;
687 apic_physaddr[apic_io_max] =
688 (uint32_t)mia->Address;
689 ioapic = apicioadr[apic_io_max] =
690 mapin_ioapic((uint32_t)mia->Address,
691 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
692 if (!ioapic)
693 goto cleanup;
694 ioapic_mask_workaround[apic_io_max] =
695 apic_is_ioapic_AMD_813x(mia->Address);
696 apic_io_max++;
697 }
698 break;
699
700 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
701 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
702 if (acpi_isop == NULL)
703 acpi_isop = mio;
704 acpi_iso_cnt++;
705 break;
706
707 case ACPI_MADT_TYPE_NMI_SOURCE:
708 /* UNIMPLEMENTED */
709 mns = (ACPI_MADT_NMI_SOURCE *) ap;
710 if (acpi_nmi_sp == NULL)
711 acpi_nmi_sp = mns;
712 acpi_nmi_scnt++;
713
714 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n",
715 mns->GlobalIrq, mns->IntiFlags);
716 break;
717
718 case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
719 /* UNIMPLEMENTED */
720 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
721 if (acpi_nmi_cp == NULL)
722 acpi_nmi_cp = mlan;
723 acpi_nmi_ccnt++;
724
725 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n",
726 mlan->ProcessorId, mlan->IntiFlags,
727 mlan->Lint);
728 break;
729
730 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
731 /* UNIMPLEMENTED */
732 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
733 cmn_err(CE_NOTE, "!apic: address override: %lx\n",
734 (long)mao->Address);
735 break;
736
737 case ACPI_MADT_TYPE_IO_SAPIC:
738 /* UNIMPLEMENTED */
739 misa = (ACPI_MADT_IO_SAPIC *) ap;
740
741 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n",
742 misa->Id, misa->GlobalIrqBase,
743 (long)misa->Address);
744 break;
745
746 case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
747 /* UNIMPLEMENTED */
748 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
749
750 cmn_err(CE_NOTE,
751 "!apic: irq source: %d %d %d 0x%x %d %d\n",
752 mis->Id, mis->Eid, mis->GlobalIrq,
753 mis->IntiFlags, mis->Type,
754 mis->IoSapicVector);
755 break;
756
757 case ACPI_MADT_TYPE_LOCAL_X2APIC:
758 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
759
760 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
761 if (mpx2a->LocalApicId == local_ids[0]) {
762 ASSERT(index == 1);
763 proc_ids[0] = mpx2a->Uid;
764 } else if (apic_nproc < NCPU && use_mp &&
765 apic_nproc < boot_ncpus) {
766 local_ids[index] = mpx2a->LocalApicId;
767 proc_ids[index] = mpx2a->Uid;
768 index++;
769 apic_nproc++;
770 } else if (apic_nproc == NCPU && !warned) {
771 cmn_err(CE_WARN, "%s: CPU limit "
772 "exceeded"
773 #if !defined(__amd64)
774 " for 32-bit mode"
775 #endif
776 "; Solaris will use %d CPUs.",
777 psm_name, NCPU);
778 warned = 1;
779 }
780 }
781
782 break;
783
784 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
785 /* UNIMPLEMENTED */
786 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
787 if (mx2alan->Uid >> 8)
788 acpi_nmi_ccnt++;
789
790 #ifdef DEBUG
791 cmn_err(CE_NOTE,
792 "!apic: local x2apic nmi: %d 0x%x %d\n",
793 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
794 #endif
795
796 break;
797
798 case ACPI_MADT_TYPE_RESERVED:
799 default:
800 break;
801 }
802
803 /* advance to next entry */
804 madt_seen += ap->Length;
805 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
806 }
807
808 /* We found multiple enabled cpus via MADT */
809 if ((apic_nproc > 1) && (apic_io_max > 0)) {
810 acpi_found_smp_config = B_TRUE;
811 cmn_err(CE_NOTE,
812 "!apic: Using ACPI (MADT) for SMP configuration");
813 }
814
815 /*
816 * allocate enough space for possible hot-adding of CPUs.
817 * max_ncpus may be less than apic_nproc if it's set by user.
818 */
819 if (plat_dr_support_cpu()) {
820 apic_max_nproc = max_ncpus;
821 }
822 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
823 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
824 goto cleanup;
825
826 /*
827 * ACPI doesn't provide the local apic ver, get it directly from the
828 * local apic
829 */
830 ver = apic_reg_ops->apic_read(APIC_VERS_REG);
831 for (i = 0; i < apic_nproc; i++) {
832 apic_cpus[i].aci_local_id = local_ids[i];
833 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
834 apic_cpus[i].aci_processor_id = proc_ids[i];
835 /* Only build mapping info for CPUs present at boot. */
836 if (i < boot_ncpus)
837 (void) acpica_map_cpu(i, proc_ids[i]);
838 }
839
840 /*
841 * To support CPU dynamic reconfiguration, the apic CPU info structure
842 * for each possible CPU will be pre-allocated at boot time.
843 * The state for each apic CPU info structure will be assigned according
844 * to the following rules:
845 * Rule 1:
846 * Slot index range: [0, min(apic_nproc, boot_ncpus))
847 * State flags: 0
848 * Note: cpu exists and will be configured/enabled at boot time
849 * Rule 2:
850 * Slot index range: [boot_ncpus, apic_nproc)
851 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
852 * Note: cpu exists but won't be configured/enabled at boot time
853 * Rule 3:
854 * Slot index range: [apic_nproc, boot_ncpus)
855 * State flags: APIC_CPU_FREE
856 * Note: cpu doesn't exist at boot time
857 * Rule 4:
858 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
859 * State flags: APIC_CPU_FREE
860 * Note: cpu doesn't exist at boot time
861 */
862 CPUSET_ZERO(apic_cpumask);
863 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
864 CPUSET_ADD(apic_cpumask, i);
865 apic_cpus[i].aci_status = 0;
866 }
867 for (i = boot_ncpus; i < apic_nproc; i++) {
868 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
869 }
870 for (i = apic_nproc; i < boot_ncpus; i++) {
871 apic_cpus[i].aci_status = APIC_CPU_FREE;
872 }
873 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
874 apic_cpus[i].aci_status = APIC_CPU_FREE;
875 }
876
877 for (i = 0; i < apic_io_max; i++) {
878 ioapic_ix = i;
879
880 /*
881 * need to check Sitka on the following acpi problem
882 * On the Sitka, the ioapic's apic_id field isn't reporting
883 * the actual io apic id. We have reported this problem
884 * to Intel. Until they fix the problem, we will get the
885 * actual id directly from the ioapic.
886 */
887 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
888 hid = (uchar_t)(id >> 24);
889
890 if (hid != apic_io_id[i]) {
891 if (apic_io_id[i] == 0)
892 apic_io_id[i] = hid;
893 else { /* set ioapic id to whatever reported by ACPI */
894 id = ((uint32_t)apic_io_id[i]) << 24;
895 ioapic_write(ioapic_ix, APIC_ID_CMD, id);
896 }
897 }
898 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
899 apic_io_ver[i] = (uchar_t)(ver & 0xff);
900 intmax = (ver >> 16) & 0xff;
901 apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
902 if (apic_first_avail_irq <= apic_io_vectend[i])
903 apic_first_avail_irq = apic_io_vectend[i] + 1;
904 }
905
906
907 /*
908 * Process SCI configuration here
909 * An error may be returned here if
910 * acpi-user-options specifies legacy mode
911 * (no SCI, no ACPI mode)
912 */
913 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
914 sci = -1;
915
916 /*
917 * Now call acpi_init() to generate namespaces
918 * If this fails, we don't attempt to use ACPI
919 * even if we were able to get a MADT above
920 */
921 if (acpica_init() != AE_OK) {
922 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!");
923 goto cleanup;
924 }
925
926 /*
927 * Call acpica_build_processor_map() now that we have
928 * ACPI namesspace access
929 */
930 (void) acpica_build_processor_map();
931
932 /*
933 * Squirrel away the SCI and flags for later on
934 * in apic_picinit() when we're ready
935 */
936 apic_sci_vect = sci;
937 apic_sci_flags = sci_flags;
938
939 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
940 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
941
942 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
943 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
944
945 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
946 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
947
948 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
949 goto cleanup;
950
951 /* Enable ACPI APIC interrupt routing */
952 if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
953 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode");
954 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
955 apic_enable_acpi = 1;
956 if (apic_sci_vect > 0) {
957 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
958 }
959 if (apic_use_acpi_madt_only) {
960 cmn_err(CE_CONT,
961 "?Using ACPI for CPU/IOAPIC information ONLY\n");
962 }
963
964 /*
965 * probe ACPI for hpet information here which is used later
966 * in apic_picinit().
967 */
968 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) {
969 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n");
970 }
971
972 kmem_free(local_ids, NCPU * sizeof (uint32_t));
973 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
974 return (PSM_SUCCESS);
975 }
976 /* if setting APIC mode failed above, we fall through to cleanup */
977
978 cleanup:
979 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s",
980 acpi_found_smp_config ? "found" : "not found");
981 apic_free_apic_cpus();
982 if (apicadr != NULL) {
983 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
984 apicadr = NULL;
985 }
986 apic_max_nproc = -1;
987 apic_nproc = 0;
988 for (i = 0; i < apic_io_max; i++) {
989 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
990 apicioadr[i] = NULL;
991 }
992 apic_io_max = 0;
993 acpi_isop = NULL;
994 acpi_iso_cnt = 0;
995 acpi_nmi_sp = NULL;
996 acpi_nmi_scnt = 0;
997 acpi_nmi_cp = NULL;
998 acpi_nmi_ccnt = 0;
999 acpi_found_smp_config = B_FALSE;
1000 kmem_free(local_ids, NCPU * sizeof (uint32_t));
1001 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1002 return (PSM_FAILURE);
1003 }
1004
1005 /*
1006 * Handle default configuration. Fill in reqd global variables & tables
1007 * Fill all details as MP table does not give any more info
1008 */
1009 static int
1010 apic_handle_defconf()
1011 {
1012 uint_t lid;
1013
1014 /* Failed to probe ACPI MADT tables, disable CPU DR. */
1015 apic_max_nproc = -1;
1016 apic_free_apic_cpus();
1017 plat_dr_disable_cpu();
1018
1019 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1020 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1021 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1022 APIC_LOCAL_MEMLEN, PROT_READ);
1023 apic_cpus_size = 2 * sizeof (*apic_cpus);
1024 apic_cpus = (apic_cpus_info_t *)
1025 kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1026 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1027 goto apic_handle_defconf_fail;
1028 CPUSET_ONLY(apic_cpumask, 0);
1029 CPUSET_ADD(apic_cpumask, 1);
1030 apic_nproc = 2;
1031 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1032 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET);
1033 /*
1034 * According to the PC+MP spec 1.1, the local ids
1035 * for the default configuration has to be 0 or 1
1036 */
1037 if (apic_cpus[0].aci_local_id == 1)
1038 apic_cpus[1].aci_local_id = 0;
1039 else if (apic_cpus[0].aci_local_id == 0)
1040 apic_cpus[1].aci_local_id = 1;
1041 else
1042 goto apic_handle_defconf_fail;
1043
1044 apic_io_id[0] = 2;
1045 apic_io_max = 1;
1046 if (apic_defconf >= 5) {
1047 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1048 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1049 apic_io_ver[0] = APIC_INTEGRATED_VERS;
1050 } else {
1051 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */
1052 apic_cpus[1].aci_local_ver = 0;
1053 apic_io_ver[0] = 0;
1054 }
1055 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1056 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1057 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1058 return (PSM_SUCCESS);
1059
1060 apic_handle_defconf_fail:
1061 if (apicadr)
1062 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1063 if (apicioadr[0])
1064 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1065 return (PSM_FAILURE);
1066 }
1067
1068 /* Parse the entries in MP configuration table and collect info that we need */
1069 static int
1070 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1071 {
1072 struct apic_procent *procp;
1073 struct apic_bus *busp;
1074 struct apic_io_entry *ioapicp;
1075 struct apic_io_intr *intrp;
1076 int ioapic_ix;
1077 uint_t lid;
1078 uint32_t id;
1079 uchar_t hid;
1080 int warned = 0;
1081
1082 /*LINTED: pointer cast may result in improper alignment */
1083 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1084
1085 /* No need to count cpu entries if we won't use them */
1086 if (!bypass_cpus_and_ioapics) {
1087
1088 /* Find max # of CPUS and allocate structure accordingly */
1089 apic_nproc = 0;
1090 CPUSET_ZERO(apic_cpumask);
1091 while (procp->proc_entry == APIC_CPU_ENTRY) {
1092 if (procp->proc_cpuflags & CPUFLAGS_EN) {
1093 if (apic_nproc < NCPU && use_mp &&
1094 apic_nproc < boot_ncpus) {
1095 CPUSET_ADD(apic_cpumask, apic_nproc);
1096 apic_nproc++;
1097 } else if (apic_nproc == NCPU && !warned) {
1098 cmn_err(CE_WARN, "%s: CPU limit "
1099 "exceeded"
1100 #if !defined(__amd64)
1101 " for 32-bit mode"
1102 #endif
1103 "; Solaris will use %d CPUs.",
1104 psm_name, NCPU);
1105 warned = 1;
1106 }
1107
1108 }
1109 procp++;
1110 }
1111 apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1112 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1113 kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1114 return (PSM_FAILURE);
1115 }
1116
1117 /*LINTED: pointer cast may result in improper alignment */
1118 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1119
1120 /*
1121 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1122 * if we're bypassing this information, it has already been filled
1123 * in by acpi_probe(), so don't overwrite it.
1124 */
1125 if (!bypass_cpus_and_ioapics)
1126 apic_nproc = 1;
1127
1128 while (procp->proc_entry == APIC_CPU_ENTRY) {
1129 /* check whether the cpu exists or not */
1130 if (!bypass_cpus_and_ioapics &&
1131 procp->proc_cpuflags & CPUFLAGS_EN) {
1132 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1133 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1134 apic_cpus[0].aci_local_id = procp->proc_apicid;
1135 if (apic_cpus[0].aci_local_id !=
1136 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) {
1137 return (PSM_FAILURE);
1138 }
1139 apic_cpus[0].aci_local_ver =
1140 procp->proc_version;
1141 } else if (apic_nproc < NCPU && use_mp &&
1142 apic_nproc < boot_ncpus) {
1143 apic_cpus[apic_nproc].aci_local_id =
1144 procp->proc_apicid;
1145
1146 apic_cpus[apic_nproc].aci_local_ver =
1147 procp->proc_version;
1148 apic_nproc++;
1149
1150 }
1151 }
1152 procp++;
1153 }
1154
1155 /*
1156 * Save start of bus entries for later use.
1157 * Get EISA level cntrl if EISA bus is present.
1158 * Also get the CPI bus id for single CPI bus case
1159 */
1160 apic_busp = busp = (struct apic_bus *)procp;
1161 while (busp->bus_entry == APIC_BUS_ENTRY) {
1162 lid = apic_find_bus_type((char *)&busp->bus_str1);
1163 if (lid == BUS_EISA) {
1164 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1165 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1166 } else if (lid == BUS_PCI) {
1167 /*
1168 * apic_single_pci_busid will be used only if
1169 * apic_pic_bus_total is equal to 1
1170 */
1171 apic_pci_bus_total++;
1172 apic_single_pci_busid = busp->bus_id;
1173 }
1174 busp++;
1175 }
1176
1177 ioapicp = (struct apic_io_entry *)busp;
1178
1179 if (!bypass_cpus_and_ioapics)
1180 apic_io_max = 0;
1181 do {
1182 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1183 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1184 apic_io_id[apic_io_max] = ioapicp->io_apicid;
1185 apic_io_ver[apic_io_max] = ioapicp->io_version;
1186 apicioadr[apic_io_max] =
1187 (void *)mapin_ioapic(
1188 (uint32_t)ioapicp->io_apic_addr,
1189 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1190
1191 if (!apicioadr[apic_io_max])
1192 return (PSM_FAILURE);
1193
1194 ioapic_mask_workaround[apic_io_max] =
1195 apic_is_ioapic_AMD_813x(
1196 ioapicp->io_apic_addr);
1197
1198 ioapic_ix = apic_io_max;
1199 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1200 hid = (uchar_t)(id >> 24);
1201
1202 if (hid != apic_io_id[apic_io_max]) {
1203 if (apic_io_id[apic_io_max] == 0)
1204 apic_io_id[apic_io_max] = hid;
1205 else {
1206 /*
1207 * set ioapic id to whatever
1208 * reported by MPS
1209 *
1210 * may not need to set index
1211 * again ???
1212 * take it out and try
1213 */
1214
1215 id = ((uint32_t)
1216 apic_io_id[apic_io_max]) <<
1217 24;
1218
1219 ioapic_write(ioapic_ix,
1220 APIC_ID_CMD, id);
1221 }
1222 }
1223 apic_io_max++;
1224 }
1225 }
1226 ioapicp++;
1227 } while (ioapicp->io_entry == APIC_IO_ENTRY);
1228
1229 apic_io_intrp = (struct apic_io_intr *)ioapicp;
1230
1231 intrp = apic_io_intrp;
1232 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1233 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1234 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1235 apic_irq_translate = 1;
1236 break;
1237 }
1238 intrp++;
1239 }
1240
1241 return (PSM_SUCCESS);
1242 }
1243
1244 boolean_t
1245 apic_cpu_in_range(int cpu)
1246 {
1247 cpu &= ~IRQ_USER_BOUND;
1248 /* Check whether cpu id is in valid range. */
1249 if (cpu < 0 || cpu >= apic_nproc) {
1250 return (B_FALSE);
1251 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1252 /*
1253 * Check whether cpuid is in valid range if CPU DR is enabled.
1254 */
1255 return (B_FALSE);
1256 } else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1257 return (B_FALSE);
1258 }
1259
1260 return (B_TRUE);
1261 }
1262
1263 processorid_t
1264 apic_get_next_bind_cpu(void)
1265 {
1266 int i, count;
1267 processorid_t cpuid = 0;
1268
1269 for (count = 0; count < apic_nproc; count++) {
1270 if (apic_next_bind_cpu >= apic_nproc) {
1271 apic_next_bind_cpu = 0;
1272 }
1273 i = apic_next_bind_cpu++;
1274 if (apic_cpu_in_range(i)) {
1275 cpuid = i;
1276 break;
1277 }
1278 }
1279
1280 return (cpuid);
1281 }
1282
1283 uint16_t
1284 apic_get_apic_version()
1285 {
1286 int i;
1287 uchar_t min_io_apic_ver = 0;
1288 static uint16_t version; /* Cache as value is constant */
1289 static boolean_t found = B_FALSE; /* Accomodate zero version */
1290
1291 if (found == B_FALSE) {
1292 found = B_TRUE;
1293
1294 /*
1295 * Don't assume all IO APICs in the system are the same.
1296 *
1297 * Set to the minimum version.
1298 */
1299 for (i = 0; i < apic_io_max; i++) {
1300 if ((apic_io_ver[i] != 0) &&
1301 ((min_io_apic_ver == 0) ||
1302 (min_io_apic_ver >= apic_io_ver[i])))
1303 min_io_apic_ver = apic_io_ver[i];
1304 }
1305
1306 /* Assume all local APICs are of the same version. */
1307 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1308 }
1309 return (version);
1310 }
1311
1312 static struct apic_mpfps_hdr *
1313 apic_find_fps_sig(caddr_t cptr, int len)
1314 {
1315 int i;
1316
1317 /* Look for the pattern "_MP_" */
1318 for (i = 0; i < len; i += 16) {
1319 if ((*(cptr+i) == '_') &&
1320 (*(cptr+i+1) == 'M') &&
1321 (*(cptr+i+2) == 'P') &&
1322 (*(cptr+i+3) == '_'))
1323 /*LINTED: pointer cast may result in improper alignment */
1324 return ((struct apic_mpfps_hdr *)(cptr + i));
1325 }
1326 return (NULL);
1327 }
1328
1329 static int
1330 apic_checksum(caddr_t bptr, int len)
1331 {
1332 int i;
1333 uchar_t cksum;
1334
1335 cksum = 0;
1336 for (i = 0; i < len; i++)
1337 cksum += *bptr++;
1338 return ((int)cksum);
1339 }
1340
1341 /*
1342 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1343 * needs special handling. We may need to chase up the device tree,
1344 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1345 * to find the IPIN at the root bus that relates to the IPIN on the
1346 * subsidiary bus (for ACPI or MP). We may, however, have an entry
1347 * in the MP table or the ACPI namespace for this device itself.
1348 * We handle both cases in the search below.
1349 */
1350 /* this is the non-acpi version */
1351 int
1352 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1353 struct apic_io_intr **intrp)
1354 {
1355 dev_info_t *dipp, *dip;
1356 int pci_irq;
1357 ddi_acc_handle_t cfg_handle;
1358 int bridge_devno, bridge_bus;
1359 int ipin;
1360
1361 dip = idip;
1362
1363 /*CONSTCOND*/
1364 while (1) {
1365 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1366 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1367 return (-1);
1368 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1369 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1370 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1371 pci_config_teardown(&cfg_handle);
1372 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1373 NULL) != 0)
1374 return (-1);
1375 /*
1376 * This is the rotating scheme documented in the
1377 * PCI-to-PCI spec. If the PCI-to-PCI bridge is
1378 * behind another PCI-to-PCI bridge, then it needs
1379 * to keep ascending until an interrupt entry is
1380 * found or the root is reached.
1381 */
1382 ipin = (child_devno + child_ipin) % PCI_INTD;
1383 if (bridge_bus == 0 && apic_pci_bus_total == 1)
1384 bridge_bus = (int)apic_single_pci_busid;
1385 pci_irq = ((bridge_devno & 0x1f) << 2) |
1386 (ipin & 0x3);
1387 if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1388 bridge_bus)) != NULL) {
1389 return (pci_irq);
1390 }
1391 dip = dipp;
1392 child_devno = bridge_devno;
1393 child_ipin = ipin;
1394 } else {
1395 pci_config_teardown(&cfg_handle);
1396 return (-1);
1397 }
1398 }
1399 /*LINTED: function will not fall off the bottom */
1400 }
1401
1402 uchar_t
1403 acpi_find_ioapic(int irq)
1404 {
1405 int i;
1406
1407 for (i = 0; i < apic_io_max; i++) {
1408 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1409 return ((uchar_t)i);
1410 }
1411 return (0xFF); /* shouldn't happen */
1412 }
1413
1414 /*
1415 * See if two irqs are compatible for sharing a vector.
1416 * Currently we only support sharing of PCI devices.
1417 */
1418 static int
1419 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1420 {
1421 uint_t level1, po1;
1422 uint_t level2, po2;
1423
1424 /* Assume active high by default */
1425 po1 = 0;
1426 po2 = 0;
1427
1428 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1429 return (0);
1430
1431 if (iflag1.intr_el == INTR_EL_CONFORM)
1432 level1 = AV_LEVEL;
1433 else
1434 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1435
1436 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1437 (iflag1.intr_po == INTR_PO_CONFORM)))
1438 po1 = AV_ACTIVE_LOW;
1439
1440 if (iflag2.intr_el == INTR_EL_CONFORM)
1441 level2 = AV_LEVEL;
1442 else
1443 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1444
1445 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1446 (iflag2.intr_po == INTR_PO_CONFORM)))
1447 po2 = AV_ACTIVE_LOW;
1448
1449 if ((level1 == level2) && (po1 == po2))
1450 return (1);
1451
1452 return (0);
1453 }
1454
1455 struct apic_io_intr *
1456 apic_find_io_intr_w_busid(int irqno, int busid)
1457 {
1458 struct apic_io_intr *intrp;
1459
1460 /*
1461 * It can have more than 1 entry with same source bus IRQ,
1462 * but unique with the source bus id
1463 */
1464 intrp = apic_io_intrp;
1465 if (intrp != NULL) {
1466 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1467 if (intrp->intr_irq == irqno &&
1468 intrp->intr_busid == busid &&
1469 intrp->intr_type == IO_INTR_INT)
1470 return (intrp);
1471 intrp++;
1472 }
1473 }
1474 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1475 "busid %x:%x\n", irqno, busid));
1476 return (NULL);
1477 }
1478
1479
1480 struct mps_bus_info {
1481 char *bus_name;
1482 int bus_id;
1483 } bus_info_array[] = {
1484 "ISA ", BUS_ISA,
1485 "PCI ", BUS_PCI,
1486 "EISA ", BUS_EISA,
1487 "XPRESS", BUS_XPRESS,
1488 "PCMCIA", BUS_PCMCIA,
1489 "VL ", BUS_VL,
1490 "CBUS ", BUS_CBUS,
1491 "CBUSII", BUS_CBUSII,
1492 "FUTURE", BUS_FUTURE,
1493 "INTERN", BUS_INTERN,
1494 "MBI ", BUS_MBI,
1495 "MBII ", BUS_MBII,
1496 "MPI ", BUS_MPI,
1497 "MPSA ", BUS_MPSA,
1498 "NUBUS ", BUS_NUBUS,
1499 "TC ", BUS_TC,
1500 "VME ", BUS_VME,
1501 "PCI-E ", BUS_PCIE
1502 };
1503
1504 static int
1505 apic_find_bus_type(char *bus)
1506 {
1507 int i = 0;
1508
1509 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1510 if (strncmp(bus, bus_info_array[i].bus_name,
1511 strlen(bus_info_array[i].bus_name)) == 0)
1512 return (bus_info_array[i].bus_id);
1513 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1514 return (0);
1515 }
1516
1517 static int
1518 apic_find_bus(int busid)
1519 {
1520 struct apic_bus *busp;
1521
1522 busp = apic_busp;
1523 while (busp->bus_entry == APIC_BUS_ENTRY) {
1524 if (busp->bus_id == busid)
1525 return (apic_find_bus_type((char *)&busp->bus_str1));
1526 busp++;
1527 }
1528 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1529 return (0);
1530 }
1531
1532 int
1533 apic_find_bus_id(int bustype)
1534 {
1535 struct apic_bus *busp;
1536
1537 busp = apic_busp;
1538 while (busp->bus_entry == APIC_BUS_ENTRY) {
1539 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1540 return (busp->bus_id);
1541 busp++;
1542 }
1543 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1544 bustype));
1545 return (-1);
1546 }
1547
1548 /*
1549 * Check if a particular irq need to be reserved for any io_intr
1550 */
1551 static struct apic_io_intr *
1552 apic_find_io_intr(int irqno)
1553 {
1554 struct apic_io_intr *intrp;
1555
1556 intrp = apic_io_intrp;
1557 if (intrp != NULL) {
1558 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1559 if (intrp->intr_irq == irqno &&
1560 intrp->intr_type == IO_INTR_INT)
1561 return (intrp);
1562 intrp++;
1563 }
1564 }
1565 return (NULL);
1566 }
1567
1568 /*
1569 * Check if the given ioapicindex intin combination has already been assigned
1570 * an irq. If so return irqno. Else -1
1571 */
1572 int
1573 apic_find_intin(uchar_t ioapic, uchar_t intin)
1574 {
1575 apic_irq_t *irqptr;
1576 int i;
1577
1578 /* find ioapic and intin in the apic_irq_table[] and return the index */
1579 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1580 irqptr = apic_irq_table[i];
1581 while (irqptr) {
1582 if ((irqptr->airq_mps_intr_index >= 0) &&
1583 (irqptr->airq_intin_no == intin) &&
1584 (irqptr->airq_ioapicindex == ioapic)) {
1585 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1586 "entry for ioapic:intin %x:%x "
1587 "shared interrupts ?", ioapic, intin));
1588 return (i);
1589 }
1590 irqptr = irqptr->airq_next;
1591 }
1592 }
1593 return (-1);
1594 }
1595
1596 int
1597 apic_allocate_irq(int irq)
1598 {
1599 int freeirq, i;
1600
1601 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1)
1602 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1603 (irq - 1))) == -1) {
1604 /*
1605 * if BIOS really defines every single irq in the mps
1606 * table, then don't worry about conflicting with
1607 * them, just use any free slot in apic_irq_table
1608 */
1609 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1610 if ((apic_irq_table[i] == NULL) ||
1611 apic_irq_table[i]->airq_mps_intr_index ==
1612 FREE_INDEX) {
1613 freeirq = i;
1614 break;
1615 }
1616 }
1617 if (freeirq == -1) {
1618 /* This shouldn't happen, but just in case */
1619 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1620 return (-1);
1621 }
1622 }
1623 if (apic_irq_table[freeirq] == NULL) {
1624 apic_irq_table[freeirq] =
1625 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1626 if (apic_irq_table[freeirq] == NULL) {
1627 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1628 psm_name);
1629 return (-1);
1630 }
1631 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1632 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1633 }
1634 return (freeirq);
1635 }
1636
1637 static int
1638 apic_find_free_irq(int start, int end)
1639 {
1640 int i;
1641
1642 for (i = start; i <= end; i++)
1643 /* Check if any I/O entry needs this IRQ */
1644 if (apic_find_io_intr(i) == NULL) {
1645 /* Then see if it is free */
1646 if ((apic_irq_table[i] == NULL) ||
1647 (apic_irq_table[i]->airq_mps_intr_index ==
1648 FREE_INDEX)) {
1649 return (i);
1650 }
1651 }
1652 return (-1);
1653 }
1654
1655 /*
1656 * compute the polarity, trigger mode and vector for programming into
1657 * the I/O apic and record in airq_rdt_entry.
1658 */
1659 void
1660 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1661 {
1662 int ioapicindex, bus_type, vector;
1663 short intr_index;
1664 uint_t level, po, io_po;
1665 struct apic_io_intr *iointrp;
1666
1667 intr_index = irqptr->airq_mps_intr_index;
1668 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1669 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1670 (void *)irqptr->airq_dip, irqptr->airq_vector));
1671
1672 if (intr_index == RESERVE_INDEX) {
1673 apic_error |= APIC_ERR_INVALID_INDEX;
1674 return;
1675 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1676 return;
1677 }
1678
1679 vector = irqptr->airq_vector;
1680 ioapicindex = irqptr->airq_ioapicindex;
1681 /* Assume edge triggered by default */
1682 level = 0;
1683 /* Assume active high by default */
1684 po = 0;
1685
1686 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1687 ASSERT(irq < 16);
1688 if (eisa_level_intr_mask & (1 << irq))
1689 level = AV_LEVEL;
1690 if (intr_index == FREE_INDEX && apic_defconf == 0)
1691 apic_error |= APIC_ERR_INVALID_INDEX;
1692 } else if (intr_index == ACPI_INDEX) {
1693 bus_type = irqptr->airq_iflag.bustype;
1694 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1695 if (bus_type == BUS_PCI)
1696 level = AV_LEVEL;
1697 } else
1698 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1699 AV_LEVEL : 0;
1700 if (level &&
1701 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1702 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1703 bus_type == BUS_PCI)))
1704 po = AV_ACTIVE_LOW;
1705 } else {
1706 iointrp = apic_io_intrp + intr_index;
1707 bus_type = apic_find_bus(iointrp->intr_busid);
1708 if (iointrp->intr_el == INTR_EL_CONFORM) {
1709 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1710 level = AV_LEVEL;
1711 else if (bus_type == BUS_PCI)
1712 level = AV_LEVEL;
1713 } else
1714 level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1715 AV_LEVEL : 0;
1716 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1717 (iointrp->intr_po == INTR_PO_CONFORM &&
1718 bus_type == BUS_PCI)))
1719 po = AV_ACTIVE_LOW;
1720 }
1721 if (level)
1722 apic_level_intr[irq] = 1;
1723 /*
1724 * The 82489DX External APIC cannot do active low polarity interrupts.
1725 */
1726 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1727 io_po = po;
1728 else
1729 io_po = 0;
1730
1731 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1732 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1733 "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1734 irqptr->airq_intin_no, level, io_po, vector,
1735 irqptr->airq_cpu);
1736
1737 irqptr->airq_rdt_entry = level|io_po|vector;
1738 }
1739
1740 int
1741 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1742 int ipin, int *pci_irqp, iflag_t *intr_flagp)
1743 {
1744
1745 int status;
1746 acpi_psm_lnk_t acpipsmlnk;
1747
1748 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1749 intr_flagp)) == ACPI_PSM_SUCCESS) {
1750 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1751 "from cache for device %s, instance #%d\n", psm_name,
1752 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1753 return (status);
1754 }
1755
1756 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1757
1758 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1759 &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1760 APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1761 " acpi_translate_pci_irq failed for device %s, instance"
1762 " #%d", psm_name, ddi_get_name(dip),
1763 ddi_get_instance(dip)));
1764 return (status);
1765 }
1766
1767 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1768 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1769 intr_flagp);
1770 if (status != ACPI_PSM_SUCCESS) {
1771 status = acpi_get_current_irq_resource(&acpipsmlnk,
1772 pci_irqp, intr_flagp);
1773 }
1774 }
1775
1776 if (status == ACPI_PSM_SUCCESS) {
1777 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1778 intr_flagp, &acpipsmlnk);
1779
1780 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1781 "new irq %d for device %s, instance #%d\n", psm_name,
1782 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1783 }
1784
1785 return (status);
1786 }
1787
1788 /*
1789 * Adds an entry to the irq list passed in, and returns the new list.
1790 * Entries are added in priority order (lower numerical priorities are
1791 * placed closer to the head of the list)
1792 */
1793 static prs_irq_list_t *
1794 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1795 iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1796 {
1797 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1798
1799 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1800
1801 newent->list_prio = priority;
1802 newent->irq = irq;
1803 newent->intrflags = *iflagp;
1804 newent->prsprv = *prsprvp;
1805 /* ->next is NULL from kmem_zalloc */
1806
1807 /*
1808 * New list -- return the new entry as the list.
1809 */
1810 if (listp == NULL)
1811 return (newent);
1812
1813 /*
1814 * Save original list pointer for return (since we're not modifying
1815 * the head)
1816 */
1817 origlistp = listp;
1818
1819 /*
1820 * Insertion sort, with entries with identical keys stored AFTER
1821 * existing entries (the less-than-or-equal test of priority does
1822 * this for us).
1823 */
1824 while (listp != NULL && listp->list_prio <= priority) {
1825 prevp = listp;
1826 listp = listp->next;
1827 }
1828
1829 newent->next = listp;
1830
1831 if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1832 return (newent);
1833 } else {
1834 prevp->next = newent;
1835 return (origlistp);
1836 }
1837 }
1838
1839 /*
1840 * Frees the list passed in, deallocating all memory and leaving *listpp
1841 * set to NULL.
1842 */
1843 static void
1844 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1845 {
1846 struct prs_irq_list_ent *nextp;
1847
1848 ASSERT(listpp != NULL);
1849
1850 while (*listpp != NULL) {
1851 nextp = (*listpp)->next;
1852 kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1853 *listpp = nextp;
1854 }
1855 }
1856
1857 /*
1858 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1859 * irqs returned by the link device's _PRS method. The irqs are chosen
1860 * to minimize contention in situations where the interrupt link device
1861 * can be programmed to steer interrupts to different interrupt controller
1862 * inputs (some of which may already be in use). The list is sorted in order
1863 * of irqs to use, with the highest priority given to interrupt controller
1864 * inputs that are not shared. When an interrupt controller input
1865 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1866 * returned list in the order that minimizes sharing (thereby ensuring lowest
1867 * possible latency from interrupt trigger time to ISR execution time).
1868 */
1869 static prs_irq_list_t *
1870 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1871 int crs_irq)
1872 {
1873 int32_t irq;
1874 int i;
1875 prs_irq_list_t *prsirqlistp = NULL;
1876 iflag_t iflags;
1877
1878 while (irqlistent != NULL) {
1879 irqlistent->intr_flags.bustype = BUS_PCI;
1880
1881 for (i = 0; i < irqlistent->num_irqs; i++) {
1882
1883 irq = irqlistent->irqs[i];
1884
1885 if (irq <= 0) {
1886 /* invalid irq number */
1887 continue;
1888 }
1889
1890 if ((irq < 16) && (apic_reserved_irqlist[irq]))
1891 continue;
1892
1893 if ((apic_irq_table[irq] == NULL) ||
1894 (apic_irq_table[irq]->airq_dip == dip)) {
1895
1896 prsirqlistp = acpi_insert_prs_irq_ent(
1897 prsirqlistp, 0 /* Highest priority */, irq,
1898 &irqlistent->intr_flags,
1899 &irqlistent->acpi_prs_prv);
1900
1901 /*
1902 * If we do not prefer the current irq from _CRS
1903 * or if we do and this irq is the same as the
1904 * current irq from _CRS, this is the one
1905 * to pick.
1906 */
1907 if (!(apic_prefer_crs) || (irq == crs_irq)) {
1908 return (prsirqlistp);
1909 }
1910 continue;
1911 }
1912
1913 /*
1914 * Edge-triggered interrupts cannot be shared
1915 */
1916 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1917 continue;
1918
1919 /*
1920 * To work around BIOSes that contain incorrect
1921 * interrupt polarity information in interrupt
1922 * descriptors returned by _PRS, we assume that
1923 * the polarity of the other device sharing this
1924 * interrupt controller input is compatible.
1925 * If it's not, the caller will catch it when
1926 * the caller invokes the link device's _CRS method
1927 * (after invoking its _SRS method).
1928 */
1929 iflags = irqlistent->intr_flags;
1930 iflags.intr_po =
1931 apic_irq_table[irq]->airq_iflag.intr_po;
1932
1933 if (!acpi_intr_compatible(iflags,
1934 apic_irq_table[irq]->airq_iflag)) {
1935 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
1936 "not compatible [%x:%x:%x !~ %x:%x:%x]",
1937 psm_name, irq,
1938 iflags.intr_po,
1939 iflags.intr_el,
1940 iflags.bustype,
1941 apic_irq_table[irq]->airq_iflag.intr_po,
1942 apic_irq_table[irq]->airq_iflag.intr_el,
1943 apic_irq_table[irq]->airq_iflag.bustype));
1944 continue;
1945 }
1946
1947 /*
1948 * If we prefer the irq from _CRS, no need
1949 * to search any further (and make sure
1950 * to add this irq with the highest priority
1951 * so it's tried first).
1952 */
1953 if (crs_irq == irq && apic_prefer_crs) {
1954
1955 return (acpi_insert_prs_irq_ent(
1956 prsirqlistp,
1957 0 /* Highest priority */,
1958 irq, &iflags,
1959 &irqlistent->acpi_prs_prv));
1960 }
1961
1962 /*
1963 * Priority is equal to the share count (lower
1964 * share count is higher priority). Note that
1965 * the intr flags passed in here are the ones we
1966 * changed above -- if incorrect, it will be
1967 * caught by the caller's _CRS flags comparison.
1968 */
1969 prsirqlistp = acpi_insert_prs_irq_ent(
1970 prsirqlistp,
1971 apic_irq_table[irq]->airq_share, irq,
1972 &iflags, &irqlistent->acpi_prs_prv);
1973 }
1974
1975 /* Go to the next irqlist entry */
1976 irqlistent = irqlistent->next;
1977 }
1978
1979 return (prsirqlistp);
1980 }
1981
1982 /*
1983 * Configures the irq for the interrupt link device identified by
1984 * acpipsmlnkp.
1985 *
1986 * Gets the current and the list of possible irq settings for the
1987 * device. If apic_unconditional_srs is not set, and the current
1988 * resource setting is in the list of possible irq settings,
1989 * current irq resource setting is passed to the caller.
1990 *
1991 * Otherwise, picks an irq number from the list of possible irq
1992 * settings, and sets the irq of the device to this value.
1993 * If prefer_crs is set, among a set of irq numbers in the list that have
1994 * the least number of devices sharing the interrupt, we pick current irq
1995 * resource setting if it is a member of this set.
1996 *
1997 * Passes the irq number in the value pointed to by pci_irqp, and
1998 * polarity and sensitivity in the structure pointed to by dipintrflagp
1999 * to the caller.
2000 *
2001 * Note that if setting the irq resource failed, but successfuly obtained
2002 * the current irq resource settings, passes the current irq resources
2003 * and considers it a success.
2004 *
2005 * Returns:
2006 * ACPI_PSM_SUCCESS on success.
2007 *
2008 * ACPI_PSM_FAILURE if an error occured during the configuration or
2009 * if a suitable irq was not found for this device, or if setting the
2010 * irq resource and obtaining the current resource fails.
2011 *
2012 */
2013 static int
2014 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2015 int *pci_irqp, iflag_t *dipintr_flagp)
2016 {
2017 int32_t irq;
2018 int cur_irq = -1;
2019 acpi_irqlist_t *irqlistp;
2020 prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2021 boolean_t found_irq = B_FALSE;
2022
2023 dipintr_flagp->bustype = BUS_PCI;
2024
2025 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2026 == ACPI_PSM_FAILURE) {
2027 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2028 "or assign IRQ for device %s, instance #%d: The system was "
2029 "unable to get the list of potential IRQs from ACPI.",
2030 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2031
2032 return (ACPI_PSM_FAILURE);
2033 }
2034
2035 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2036 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2037 (cur_irq > 0)) {
2038 /*
2039 * If an IRQ is set in CRS and that IRQ exists in the set
2040 * returned from _PRS, return that IRQ, otherwise print
2041 * a warning
2042 */
2043
2044 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2045 == ACPI_PSM_SUCCESS) {
2046
2047 ASSERT(pci_irqp != NULL);
2048 *pci_irqp = cur_irq;
2049 acpi_free_irqlist(irqlistp);
2050 return (ACPI_PSM_SUCCESS);
2051 }
2052
2053 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2054 "current irq %d for device %s, instance #%d in ACPI's "
2055 "list of possible irqs for this device. Picking one from "
2056 " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2057 ddi_get_instance(dip)));
2058 }
2059
2060 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2061 cur_irq)) == NULL) {
2062
2063 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2064 "suitable irq from the list of possible irqs for device "
2065 "%s, instance #%d in ACPI's list of possible irqs",
2066 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2067
2068 acpi_free_irqlist(irqlistp);
2069 return (ACPI_PSM_FAILURE);
2070 }
2071
2072 acpi_free_irqlist(irqlistp);
2073
2074 for (prs_irq_entp = prs_irq_listp;
2075 prs_irq_entp != NULL && found_irq == B_FALSE;
2076 prs_irq_entp = prs_irq_entp->next) {
2077
2078 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2079 irq = prs_irq_entp->irq;
2080
2081 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2082 "device %s instance #%d\n", psm_name, irq,
2083 ddi_get_name(dip), ddi_get_instance(dip)));
2084
2085 if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2086 == ACPI_PSM_SUCCESS) {
2087 /*
2088 * setting irq was successful, check to make sure CRS
2089 * reflects that. If CRS does not agree with what we
2090 * set, return the irq that was set.
2091 */
2092
2093 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2094 dipintr_flagp) == ACPI_PSM_SUCCESS) {
2095
2096 if (cur_irq != irq)
2097 APIC_VERBOSE_IRQ((CE_WARN,
2098 "!%s: IRQ resource set "
2099 "(irqno %d) for device %s "
2100 "instance #%d, differs from "
2101 "current setting irqno %d",
2102 psm_name, irq, ddi_get_name(dip),
2103 ddi_get_instance(dip), cur_irq));
2104 } else {
2105 /*
2106 * On at least one system, there was a bug in
2107 * a DSDT method called by _STA, causing _STA to
2108 * indicate that the link device was disabled
2109 * (when, in fact, it was enabled). Since _SRS
2110 * succeeded, assume that _CRS is lying and use
2111 * the iflags from this _PRS interrupt choice.
2112 * If we're wrong about the flags, the polarity
2113 * will be incorrect and we may get an interrupt
2114 * storm, but there's not much else we can do
2115 * at this point.
2116 */
2117 *dipintr_flagp = prs_irq_entp->intrflags;
2118 }
2119
2120 /*
2121 * Return the irq that was set, and not what _CRS
2122 * reports, since _CRS has been seen to return
2123 * different IRQs than what was passed to _SRS on some
2124 * systems (and just not return successfully on others).
2125 */
2126 cur_irq = irq;
2127 found_irq = B_TRUE;
2128 } else {
2129 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2130 "irq %d failed for device %s instance #%d",
2131 psm_name, irq, ddi_get_name(dip),
2132 ddi_get_instance(dip)));
2133
2134 if (cur_irq == -1) {
2135 acpi_destroy_prs_irq_list(&prs_irq_listp);
2136 return (ACPI_PSM_FAILURE);
2137 }
2138 }
2139 }
2140
2141 acpi_destroy_prs_irq_list(&prs_irq_listp);
2142
2143 if (!found_irq)
2144 return (ACPI_PSM_FAILURE);
2145
2146 ASSERT(pci_irqp != NULL);
2147 *pci_irqp = cur_irq;
2148 return (ACPI_PSM_SUCCESS);
2149 }
2150
2151 void
2152 ioapic_disable_redirection()
2153 {
2154 int ioapic_ix;
2155 int intin_max;
2156 int intin_ix;
2157
2158 /* Disable the I/O APIC redirection entries */
2159 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2160
2161 /* Bits 23-16 define the maximum redirection entries */
2162 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2163 & 0xff;
2164
2165 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2166 /*
2167 * The assumption here is that this is safe, even for
2168 * systems with IOAPICs that suffer from the hardware
2169 * erratum because all devices have been quiesced before
2170 * this function is called from apic_shutdown()
2171 * (or equivalent). If that assumption turns out to be
2172 * false, this mask operation can induce the same
2173 * erratum result we're trying to avoid.
2174 */
2175 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2176 AV_MASK);
2177 }
2178 }
2179 }
2180
2181 /*
2182 * Looks for an IOAPIC with the specified physical address in the /ioapics
2183 * node in the device tree (created by the PCI enumerator).
2184 */
2185 static boolean_t
2186 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2187 {
2188 /*
2189 * Look in /ioapics, for the ioapic with
2190 * the physical address given
2191 */
2192 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2193 dev_info_t *ioapic_child;
2194 boolean_t rv = B_FALSE;
2195 int vid, did;
2196 uint64_t ioapic_paddr;
2197 boolean_t done = B_FALSE;
2198
2199 if (ioapicsnode == NULL)
2200 return (B_FALSE);
2201
2202 /* Load first child: */
2203 ioapic_child = ddi_get_child(ioapicsnode);
2204 while (!done && ioapic_child != 0) { /* Iterate over children */
2205
2206 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2207 ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2208 != 0 && physaddr == ioapic_paddr) {
2209
2210 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2211 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2212
2213 if (vid == VENID_AMD) {
2214
2215 did = ddi_prop_get_int(DDI_DEV_T_ANY,
2216 ioapic_child, DDI_PROP_DONTPASS,
2217 IOAPICS_PROP_DEVID, 0);
2218
2219 if (did == DEVID_8131_IOAPIC ||
2220 did == DEVID_8132_IOAPIC) {
2221 rv = B_TRUE;
2222 done = B_TRUE;
2223 }
2224 }
2225 }
2226
2227 if (!done)
2228 ioapic_child = ddi_get_next_sibling(ioapic_child);
2229 }
2230
2231 /* The ioapics node was held by ddi_find_devinfo, so release it */
2232 ndi_rele_devi(ioapicsnode);
2233 return (rv);
2234 }
2235
2236 struct apic_state {
2237 int32_t as_task_reg;
2238 int32_t as_dest_reg;
2239 int32_t as_format_reg;
2240 int32_t as_local_timer;
2241 int32_t as_pcint_vect;
2242 int32_t as_int_vect0;
2243 int32_t as_int_vect1;
2244 int32_t as_err_vect;
2245 int32_t as_init_count;
2246 int32_t as_divide_reg;
2247 int32_t as_spur_int_reg;
2248 uint32_t as_ioapic_ids[MAX_IO_APIC];
2249 };
2250
2251
2252 static int
2253 apic_acpi_enter_apicmode(void)
2254 {
2255 ACPI_OBJECT_LIST arglist;
2256 ACPI_OBJECT arg;
2257 ACPI_STATUS status;
2258
2259 /* Setup parameter object */
2260 arglist.Count = 1;
2261 arglist.Pointer = &arg;
2262 arg.Type = ACPI_TYPE_INTEGER;
2263 arg.Integer.Value = ACPI_APIC_MODE;
2264
2265 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2266 /*
2267 * Per ACPI spec - section 5.8.1 _PIC Method
2268 * calling the \_PIC control method is optional for the OS
2269 * and might not be found. It's ok to not fail in such cases.
2270 * This is the case on linux KVM and qemu (status AE_NOT_FOUND)
2271 */
2272 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
2273 cmn_err(CE_NOTE,
2274 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x",
2275 ACPI_FAILURE(status));
2276 return (PSM_FAILURE);
2277 } else {
2278 return (PSM_SUCCESS);
2279 }
2280 }
2281
2282
2283 static void
2284 apic_save_state(struct apic_state *sp)
2285 {
2286 int i, cpuid;
2287 ulong_t iflag;
2288
2289 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2290 /*
2291 * First the local APIC.
2292 */
2293 sp->as_task_reg = apic_reg_ops->apic_get_pri();
2294 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG);
2295 if (apic_mode == LOCAL_APIC)
2296 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2297 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2298 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2299 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2300 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2301 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2302 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2303 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2304 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2305
2306 /*
2307 * If on the boot processor then save the IOAPICs' IDs
2308 */
2309 if ((cpuid = psm_get_cpu_id()) == 0) {
2310
2311 iflag = intr_clear();
2312 lock_set(&apic_ioapic_lock);
2313
2314 for (i = 0; i < apic_io_max; i++)
2315 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2316
2317 lock_clear(&apic_ioapic_lock);
2318 intr_restore(iflag);
2319 }
2320
2321 /* apic_state() is currently invoked only in Suspend/Resume */
2322 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2323 }
2324
2325 static void
2326 apic_restore_state(struct apic_state *sp)
2327 {
2328 int i;
2329 ulong_t iflag;
2330
2331 /*
2332 * First the local APIC.
2333 */
2334 apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2335 if (apic_mode == LOCAL_APIC) {
2336 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2337 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2338 }
2339 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2340 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2341 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2342 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2343 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2344 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2345 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2346 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2347
2348 /*
2349 * the following only needs to be done once, so we do it on the
2350 * boot processor, since we know that we only have one of those
2351 */
2352 if (psm_get_cpu_id() == 0) {
2353
2354 iflag = intr_clear();
2355 lock_set(&apic_ioapic_lock);
2356
2357 /* Restore IOAPICs' APIC IDs */
2358 for (i = 0; i < apic_io_max; i++) {
2359 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2360 }
2361
2362 lock_clear(&apic_ioapic_lock);
2363 intr_restore(iflag);
2364
2365 /*
2366 * Reenter APIC mode before restoring LNK devices
2367 */
2368 (void) apic_acpi_enter_apicmode();
2369
2370 /*
2371 * restore acpi link device mappings
2372 */
2373 acpi_restore_link_devices();
2374 }
2375 }
2376
2377 /*
2378 * Returns 0 on success
2379 */
2380 int
2381 apic_state(psm_state_request_t *rp)
2382 {
2383 PMD(PMD_SX, ("apic_state "))
2384 switch (rp->psr_cmd) {
2385 case PSM_STATE_ALLOC:
2386 rp->req.psm_state_req.psr_state =
2387 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2388 if (rp->req.psm_state_req.psr_state == NULL)
2389 return (ENOMEM);
2390 rp->req.psm_state_req.psr_state_size =
2391 sizeof (struct apic_state);
2392 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2393 rp->req.psm_state_req.psr_state,
2394 rp->req.psm_state_req.psr_state_size))
2395 return (0);
2396
2397 case PSM_STATE_FREE:
2398 kmem_free(rp->req.psm_state_req.psr_state,
2399 rp->req.psm_state_req.psr_state_size);
2400 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2401 rp->req.psm_state_req.psr_state,
2402 rp->req.psm_state_req.psr_state_size))
2403 return (0);
2404
2405 case PSM_STATE_SAVE:
2406 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2407 rp->req.psm_state_req.psr_state,
2408 rp->req.psm_state_req.psr_state_size))
2409 apic_save_state(rp->req.psm_state_req.psr_state);
2410 return (0);
2411
2412 case PSM_STATE_RESTORE:
2413 apic_restore_state(rp->req.psm_state_req.psr_state);
2414 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2415 rp->req.psm_state_req.psr_state,
2416 rp->req.psm_state_req.psr_state_size))
2417 return (0);
2418
2419 default:
2420 return (EINVAL);
2421 }
2422 }
Unleashed OS