usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore.h

   1 /*
   2 * CDDL HEADER START
   3 *
   4 * The contents of this file are subject to the terms of the
   5 * Common Development and Distribution License, v.1,  (the "License").
   6 * You may not use this file except in compliance with the License.
   7 *
   8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9 * or http://opensource.org/licenses/CDDL-1.0.
  10 * See the License for the specific language governing permissions
  11 * and limitations under the License.
  12 *
  13 * When distributing Covered Code, include this CDDL HEADER in each
  14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15 * If applicable, add the following below this CDDL HEADER, with the
  16 * fields enclosed by brackets "[]" replaced with your own identifying
  17 * information: Portions Copyright [yyyy] [name of copyright owner]
  18 *
  19 * CDDL HEADER END
  20 */
  21
  22 /*
  23 * Copyright 2014-2017 Cavium, Inc.
  24 * The contents of this file are subject to the terms of the Common Development
  25 * and Distribution License, v.1,  (the "License").
  26
  27 * You may not use this file except in compliance with the License.
  28
  29 * You can obtain a copy of the License at available
  30 * at http://opensource.org/licenses/CDDL-1.0
  31
  32 * See the License for the specific language governing permissions and
  33 * limitations under the License.
  34 */
  35
  36 #ifndef __ECORE_H
  37 #define __ECORE_H
  38
  39 #include "ecore_hsi_common.h"
  40 #include "ecore_hsi_debug_tools.h"
  41 #include "ecore_hsi_init_func.h"
  42 #include "ecore_hsi_init_tool.h"
  43 #include "ecore_proto_if.h"
  44 #include "mcp_public.h"
  45
  46 #define ECORE_MAJOR_VERSION             8
  47 #define ECORE_MINOR_VERSION             18
  48 #define ECORE_REVISION_VERSION          18
  49 #define ECORE_ENGINEERING_VERSION       0
  50
  51 #define ECORE_VERSION                                                   \
  52         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  53          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  54
  55 #define STORM_FW_VERSION                                                \
  56         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  57          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  58
  59 #define MAX_HWFNS_PER_DEVICE    2
  60 #define NAME_SIZE 16
  61 #define ARRAY_DECL static const
  62 #define ECORE_WFQ_UNIT  100
  63
  64 /* Constants */
  65 #define ECORE_WID_SIZE          (1024)
  66
  67 /* Configurable */
  68 #define ECORE_PF_DEMS_SIZE      (4)
  69
  70 /* cau states */
  71 enum ecore_coalescing_mode {
  72         ECORE_COAL_MODE_DISABLE,
  73         ECORE_COAL_MODE_ENABLE
  74 };
  75
  76 enum ecore_nvm_cmd {
  77         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  78         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  79         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  80         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  81         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  82         ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
  83         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  84         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  85         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  86         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  87         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  88         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  89 };
  90
  91 #ifndef LINUX_REMOVE
  92 #if !defined(CONFIG_ECORE_L2) && !defined(CONFIG_ECORE_ROCE) && \
  93     !defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI)
  94 #define CONFIG_ECORE_L2
  95 #define CONFIG_ECORE_SRIOV
  96 #define CONFIG_ECORE_ROCE
  97 #define CONFIG_ECORE_IWARP
  98 #define CONFIG_ECORE_FCOE
  99 #define CONFIG_ECORE_ISCSI
 100 #define CONFIG_ECORE_LL2
 101 #endif
 102 #endif
 103
 104 /* helpers */
 105 #ifndef __EXTRACT__LINUX__
 106 #define MASK_FIELD(_name, _value)                                       \
 107                 ((_value) &= (_name##_MASK))
 108
 109 #define FIELD_VALUE(_name, _value)                                      \
 110                 ((_value & _name##_MASK) << _name##_SHIFT)
 111
 112 #define SET_FIELD(value, name, flag)                                    \
 113 do {                                                                    \
 114         (value) &= ~(name##_MASK << name##_SHIFT);                      \
 115         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
 116 } while (0)
 117
 118 #define GET_FIELD(value, name)                                          \
 119         (((value) >> (name##_SHIFT)) & name##_MASK)
 120 #endif
 121
 122 #define ECORE_MFW_GET_FIELD(name, field)                                \
 123         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
 124
 125 #define ECORE_MFW_SET_FIELD(name, field, value)                         \
 126 do {                                                                    \
 127         (name) &= ~((field ## _MASK) << (field ## _SHIFT));             \
 128         (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));  \
 129 } while (0)
 130
 131 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 132 {
 133         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 134                       (cid * ECORE_PF_DEMS_SIZE);
 135
 136         return db_addr;
 137 }
 138
 139 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 140 {
 141         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 142                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 143
 144         return db_addr;
 145 }
 146
 147 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 148         ((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \
 149          ~((1<<(p_hwfn->p_dev->cache_shift))-1))
 150
 151 #ifndef LINUX_REMOVE
 152 #ifndef U64_HI
 153 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 154 #endif
 155
 156 #ifndef U64_LO
 157 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 158 #endif
 159 #endif
 160
 161 #ifndef __EXTRACT__LINUX__
 162 #ifndef UEFI
 163 /* Debug print definitions */
 164 #define DP_ERR(p_dev, fmt, ...)                         \
 165 do {                                                    \
 166         PRINT_ERR((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt,   \
 167                   __func__, __LINE__,                   \
 168                   (p_dev)->name ? (p_dev)->name : "",   \
 169                   ##__VA_ARGS__);                       \
 170 } while (0)
 171
 172 #define DP_NOTICE(p_dev, is_assert, fmt, ...)                           \
 173 do {                                                                    \
 174         if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_NOTICE)) {   \
 175                 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt,               \
 176                       __func__, __LINE__,                               \
 177                       (p_dev)->name ? (p_dev)->name : "",               \
 178                       ##__VA_ARGS__);                                   \
 179                 OSAL_ASSERT(!is_assert);                                \
 180         }                                                               \
 181 } while (0)
 182
 183 #define DP_INFO(p_dev, fmt, ...)                                      \
 184 do {                                                                  \
 185         if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_INFO)) {   \
 186                 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt,             \
 187                       __func__, __LINE__,                             \
 188                       (p_dev)->name ? (p_dev)->name : "",             \
 189                       ##__VA_ARGS__);                                 \
 190         }                                                             \
 191 } while (0)
 192
 193 #define DP_VERBOSE(p_dev, module, fmt, ...)                             \
 194 do {                                                                    \
 195         if (OSAL_UNLIKELY(((p_dev)->dp_level <= ECORE_LEVEL_VERBOSE) && \
 196             ((p_dev)->dp_module & module))) {                           \
 197                 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt,               \
 198                       __func__, __LINE__,                               \
 199                       (p_dev)->name ? (p_dev)->name : "",               \
 200                       ##__VA_ARGS__);                                   \
 201         }                                                               \
 202 } while (0)
 203 #endif
 204
 205 enum DP_LEVEL {
 206         ECORE_LEVEL_VERBOSE     = 0x0,
 207         ECORE_LEVEL_INFO        = 0x1,
 208         ECORE_LEVEL_NOTICE      = 0x2,
 209         ECORE_LEVEL_ERR         = 0x3,
 210 };
 211
 212 #define ECORE_LOG_LEVEL_SHIFT   (30)
 213 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 214 #define ECORE_LOG_INFO_MASK     (0x40000000)
 215 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 216
 217 enum DP_MODULE {
 218 #ifndef LINUX_REMOVE
 219         ECORE_MSG_DRV           = 0x0001,
 220         ECORE_MSG_PROBE         = 0x0002,
 221         ECORE_MSG_LINK          = 0x0004,
 222         ECORE_MSG_TIMER         = 0x0008,
 223         ECORE_MSG_IFDOWN        = 0x0010,
 224         ECORE_MSG_IFUP          = 0x0020,
 225         ECORE_MSG_RX_ERR        = 0x0040,
 226         ECORE_MSG_TX_ERR        = 0x0080,
 227         ECORE_MSG_TX_QUEUED     = 0x0100,
 228         ECORE_MSG_INTR          = 0x0200,
 229         ECORE_MSG_TX_DONE       = 0x0400,
 230         ECORE_MSG_RX_STATUS     = 0x0800,
 231         ECORE_MSG_PKTDATA       = 0x1000,
 232         ECORE_MSG_HW            = 0x2000,
 233         ECORE_MSG_WOL           = 0x4000,
 234 #endif
 235         ECORE_MSG_SPQ           = 0x10000,
 236         ECORE_MSG_STATS         = 0x20000,
 237         ECORE_MSG_DCB           = 0x40000,
 238         ECORE_MSG_IOV           = 0x80000,
 239         ECORE_MSG_SP            = 0x100000,
 240         ECORE_MSG_STORAGE       = 0x200000,
 241         ECORE_MSG_OOO           = 0x200000,
 242         ECORE_MSG_CXT           = 0x800000,
 243         ECORE_MSG_LL2           = 0x1000000,
 244         ECORE_MSG_ILT           = 0x2000000,
 245         ECORE_MSG_RDMA          = 0x4000000,
 246         ECORE_MSG_DEBUG         = 0x8000000,
 247         /* to be added...up to 0x8000000 */
 248 };
 249 #endif
 250
 251 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 252
 253 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 254         (val == (cond1) ? true1 : \
 255          (val == (cond2) ? true2 : def))
 256
 257 /* forward */
 258 struct ecore_ptt_pool;
 259 struct ecore_spq;
 260 struct ecore_sb_info;
 261 struct ecore_sb_attn_info;
 262 struct ecore_cxt_mngr;
 263 struct ecore_dma_mem;
 264 struct ecore_sb_sp_info;
 265 struct ecore_ll2_info;
 266 struct ecore_l2_info;
 267 struct ecore_igu_info;
 268 struct ecore_mcp_info;
 269 struct ecore_dcbx_info;
 270
 271 struct ecore_rt_data {
 272         u32     *init_val;
 273         bool    *b_valid;
 274 };
 275
 276 enum ecore_tunn_mode {
 277         ECORE_MODE_L2GENEVE_TUNN,
 278         ECORE_MODE_IPGENEVE_TUNN,
 279         ECORE_MODE_L2GRE_TUNN,
 280         ECORE_MODE_IPGRE_TUNN,
 281         ECORE_MODE_VXLAN_TUNN,
 282 };
 283
 284 enum ecore_tunn_clss {
 285         ECORE_TUNN_CLSS_MAC_VLAN,
 286         ECORE_TUNN_CLSS_MAC_VNI,
 287         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 288         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 289         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 290         MAX_ECORE_TUNN_CLSS,
 291 };
 292
 293 struct ecore_tunn_update_type {
 294         bool b_update_mode;
 295         bool b_mode_enabled;
 296         enum ecore_tunn_clss tun_cls;
 297 };
 298
 299 struct ecore_tunn_update_udp_port {
 300         bool b_update_port;
 301         u16 port;
 302 };
 303
 304 struct ecore_tunnel_info {
 305         struct ecore_tunn_update_type vxlan;
 306         struct ecore_tunn_update_type l2_geneve;
 307         struct ecore_tunn_update_type ip_geneve;
 308         struct ecore_tunn_update_type l2_gre;
 309         struct ecore_tunn_update_type ip_gre;
 310
 311         struct ecore_tunn_update_udp_port vxlan_port;
 312         struct ecore_tunn_update_udp_port geneve_port;
 313
 314         bool b_update_rx_cls;
 315         bool b_update_tx_cls;
 316 };
 317
 318 /* The PCI personality is not quite synonymous to protocol ID:
 319  * 1. All personalities need CORE connections
 320  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 321  */
 322 enum ecore_pci_personality {
 323         ECORE_PCI_ETH,
 324         ECORE_PCI_FCOE,
 325         ECORE_PCI_ISCSI,
 326         ECORE_PCI_ETH_ROCE,
 327         ECORE_PCI_ETH_IWARP,
 328         ECORE_PCI_ETH_RDMA,
 329         ECORE_PCI_DEFAULT /* default in shmem */
 330 };
 331
 332 /* All VFs are symetric, all counters are PF + all VFs */
 333 struct ecore_qm_iids {
 334         u32 cids;
 335         u32 vf_cids;
 336         u32 tids;
 337 };
 338
 339 #define MAX_PF_PER_PORT 8
 340
 341 /* HW / FW resources, output of features supported below, most information
 342  * is received from MFW.
 343  */
 344 enum ecore_resources {
 345         ECORE_L2_QUEUE,
 346         ECORE_VPORT,
 347         ECORE_RSS_ENG,
 348         ECORE_PQ,
 349         ECORE_RL,
 350         ECORE_MAC,
 351         ECORE_VLAN,
 352         ECORE_RDMA_CNQ_RAM,
 353         ECORE_ILT,
 354         ECORE_LL2_QUEUE,
 355         ECORE_CMDQS_CQS,
 356         ECORE_RDMA_STATS_QUEUE,
 357         ECORE_BDQ,
 358
 359         /* This is needed only internally for matching against the IGU.
 360          * In case of legacy MFW, would be set to `0'.
 361          */
 362         ECORE_SB,
 363
 364         ECORE_MAX_RESC,
 365 };
 366
 367 /* Features that require resources, given as input to the resource management
 368  * algorithm, the output are the resources above
 369  */
 370 enum ecore_feature {
 371         ECORE_PF_L2_QUE,
 372         ECORE_PF_TC,
 373         ECORE_VF,
 374         ECORE_EXTRA_VF_QUE,
 375         ECORE_VMQ,
 376         ECORE_RDMA_CNQ,
 377         ECORE_ISCSI_CQ,
 378         ECORE_FCOE_CQ,
 379         ECORE_VF_L2_QUE,
 380         ECORE_MAX_FEATURES,
 381 };
 382
 383 enum ecore_port_mode {
 384         ECORE_PORT_MODE_DE_2X40G,
 385         ECORE_PORT_MODE_DE_2X50G,
 386         ECORE_PORT_MODE_DE_1X100G,
 387         ECORE_PORT_MODE_DE_4X10G_F,
 388         ECORE_PORT_MODE_DE_4X10G_E,
 389         ECORE_PORT_MODE_DE_4X20G,
 390         ECORE_PORT_MODE_DE_1X40G,
 391         ECORE_PORT_MODE_DE_2X25G,
 392         ECORE_PORT_MODE_DE_1X25G,
 393         ECORE_PORT_MODE_DE_4X25G,
 394         ECORE_PORT_MODE_DE_2X10G,
 395 };
 396
 397 enum ecore_dev_cap {
 398         ECORE_DEV_CAP_ETH,
 399         ECORE_DEV_CAP_FCOE,
 400         ECORE_DEV_CAP_ISCSI,
 401         ECORE_DEV_CAP_ROCE,
 402         ECORE_DEV_CAP_IWARP
 403 };
 404
 405 #ifndef __EXTRACT__LINUX__
 406 enum ecore_hw_err_type {
 407         ECORE_HW_ERR_FAN_FAIL,
 408         ECORE_HW_ERR_MFW_RESP_FAIL,
 409         ECORE_HW_ERR_HW_ATTN,
 410         ECORE_HW_ERR_DMAE_FAIL,
 411         ECORE_HW_ERR_RAMROD_FAIL,
 412         ECORE_HW_ERR_FW_ASSERT,
 413 };
 414 #endif
 415
 416 enum ecore_wol_support {
 417         ECORE_WOL_SUPPORT_NONE,
 418         ECORE_WOL_SUPPORT_PME,
 419 };
 420
 421 struct ecore_hw_info {
 422         /* PCI personality */
 423         enum ecore_pci_personality personality;
 424 #define ECORE_IS_RDMA_PERSONALITY(dev) \
 425         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 426          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 427          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 428 #define ECORE_IS_ROCE_PERSONALITY(dev) \
 429         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 430          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 431 #define ECORE_IS_IWARP_PERSONALITY(dev) \
 432         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 433          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 434 #define ECORE_IS_L2_PERSONALITY(dev) \
 435         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 436          ECORE_IS_RDMA_PERSONALITY(dev))
 437 #define ECORE_IS_FCOE_PERSONALITY(dev) \
 438         ((dev)->hw_info.personality == ECORE_PCI_FCOE)
 439 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
 440         ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
 441
 442         /* Resource Allocation scheme results */
 443         u32 resc_start[ECORE_MAX_RESC];
 444         u32 resc_num[ECORE_MAX_RESC];
 445         u32 feat_num[ECORE_MAX_FEATURES];
 446
 447         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 448         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 449         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 450                                          RESC_NUM(_p_hwfn, resc))
 451         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 452
 453         /* Amount of traffic classes HW supports */
 454         u8 num_hw_tc;
 455
 456         /* Amount of TCs which should be active according to DCBx or upper layer driver configuration */
 457         u8 num_active_tc;
 458
 459         /* The traffic class used by PF for it's offloaded protocol */
 460         u8 offload_tc;
 461
 462         u32 concrete_fid;
 463         u16 opaque_fid;
 464         u16 ovlan;
 465         u32 part_num[4];
 466
 467 #define ETH_ALEN 6 /* @@@ TBD - define somewhere else for Windows */
 468         unsigned char hw_mac_addr[ETH_ALEN];
 469
 470         u16 num_iscsi_conns;
 471         u16 num_fcoe_conns;
 472
 473         struct ecore_igu_info *p_igu_info;
 474         /* Sriov */
 475         u8 max_chains_per_vf;
 476
 477         u32 port_mode;
 478         u32     hw_mode;
 479         unsigned long device_capabilities;
 480
 481         /* Default DCBX mode */
 482         u8 dcbx_mode;
 483
 484         u16 mtu;
 485
 486         enum ecore_wol_support          b_wol_support;
 487 };
 488
 489 /* maximun size of read/write commands (HW limit) */
 490 #define DMAE_MAX_RW_SIZE        0x2000
 491
 492 struct ecore_dmae_info {
 493         /* Mutex for synchronizing access to functions */
 494         osal_mutex_t    mutex;
 495
 496         u8 channel;
 497
 498         dma_addr_t completion_word_phys_addr;
 499
 500         /* The memory location where the DMAE writes the completion
 501          * value when an operation is finished on this context.
 502          */
 503         u32 *p_completion_word;
 504
 505         dma_addr_t intermediate_buffer_phys_addr;
 506
 507         /* An intermediate buffer for DMAE operations that use virtual
 508          * addresses - data is DMA'd to/from this buffer and then
 509          * memcpy'd to/from the virtual address
 510          */
 511         u32 *p_intermediate_buffer;
 512
 513         dma_addr_t dmae_cmd_phys_addr;
 514         struct dmae_cmd *p_dmae_cmd;
 515 };
 516
 517 struct ecore_wfq_data {
 518         u32 default_min_speed; /* When wfq feature is not configured */
 519         u32 min_speed; /* when feature is configured for any 1 vport */
 520         bool configured;
 521 };
 522
 523 struct ecore_qm_info {
 524         struct init_qm_pq_params    *qm_pq_params;
 525         struct init_qm_vport_params *qm_vport_params;
 526         struct init_qm_port_params  *qm_port_params;
 527         u16                     start_pq;
 528         u8                      start_vport;
 529         u16                     pure_lb_pq;
 530         u16                     offload_pq;
 531         u16                     low_latency_pq;
 532         u16                     pure_ack_pq;
 533         u16                     ooo_pq;
 534         u16                     first_vf_pq;
 535         u16                     first_mcos_pq;
 536         u16                     first_rl_pq;
 537         u16                     num_pqs;
 538         u16                     num_vf_pqs;
 539         u8                      num_vports;
 540         u8                      max_phys_tcs_per_port;
 541         u8                      ooo_tc;
 542         bool                    pf_rl_en;
 543         bool                    pf_wfq_en;
 544         bool                    vport_rl_en;
 545         bool                    vport_wfq_en;
 546         u8                      pf_wfq;
 547         u32                     pf_rl;
 548         struct ecore_wfq_data   *wfq_data;
 549         u8                      num_pf_rls;
 550 };
 551
 552 struct storm_stats {
 553         u32 address;
 554         u32 len;
 555 };
 556
 557 struct ecore_fw_data {
 558 #ifdef CONFIG_ECORE_BINARY_FW
 559         struct fw_ver_info *fw_ver_info;
 560 #endif
 561         const u8 *modes_tree_buf;
 562         union init_op *init_ops;
 563         const u32 *arr_data;
 564         u32 init_ops_size;
 565 };
 566
 567 struct ecore_hwfn {
 568         struct ecore_dev                *p_dev;
 569         u8                              my_id;          /* ID inside the PF */
 570 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 571         u8                              rel_pf_id;      /* Relative to engine*/
 572         u8                              abs_pf_id;
 573         #define ECORE_PATH_ID(_p_hwfn) \
 574                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 575         u8                              port_id;
 576         bool                            b_active;
 577
 578         u32                             dp_module;
 579         u8                              dp_level;
 580         char                            name[NAME_SIZE];
 581         void                            *dp_ctx;
 582
 583         bool                            first_on_engine;
 584         bool                            hw_init_done;
 585
 586         u8                              num_funcs_on_engine;
 587         u8                              enabled_func_idx;
 588
 589         /* BAR access */
 590         void OSAL_IOMEM                 *regview;
 591         void OSAL_IOMEM                 *doorbells;
 592         u64                             db_phys_addr;
 593         unsigned long                   db_size;
 594
 595         /* PTT pool */
 596         struct ecore_ptt_pool           *p_ptt_pool;
 597
 598         /* HW info */
 599         struct ecore_hw_info            hw_info;
 600
 601         /* rt_array (for init-tool) */
 602         struct ecore_rt_data            rt_data;
 603
 604         /* SPQ */
 605         struct ecore_spq                *p_spq;
 606
 607         /* EQ */
 608         struct ecore_eq                 *p_eq;
 609
 610         /* Consolidate Q*/
 611         struct ecore_consq              *p_consq;
 612
 613         /* Slow-Path definitions */
 614         osal_dpc_t                      sp_dpc;
 615         bool                            b_sp_dpc_enabled;
 616
 617         struct ecore_ptt                *p_main_ptt;
 618         struct ecore_ptt                *p_dpc_ptt;
 619
 620         struct ecore_sb_sp_info         *p_sp_sb;
 621         struct ecore_sb_attn_info       *p_sb_attn;
 622
 623         /* Protocol related */
 624         bool                            using_ll2;
 625         struct ecore_ll2_info           *p_ll2_info;
 626         struct ecore_ooo_info           *p_ooo_info;
 627         struct ecore_iscsi_info         *p_iscsi_info;
 628         struct ecore_fcoe_info          *p_fcoe_info;
 629         struct ecore_rdma_info          *p_rdma_info;
 630         struct ecore_pf_params          pf_params;
 631
 632         bool                            b_rdma_enabled_in_prs;
 633         u32                             rdma_prs_search_reg;
 634
 635         struct ecore_cxt_mngr           *p_cxt_mngr;
 636
 637         /* Flag indicating whether interrupts are enabled or not*/
 638         bool                            b_int_enabled;
 639         bool                            b_int_requested;
 640
 641         /* True if the driver requests for the link */
 642         bool                            b_drv_link_init;
 643
 644         struct ecore_vf_iov             *vf_iov_info;
 645         struct ecore_pf_iov             *pf_iov_info;
 646         struct ecore_mcp_info           *mcp_info;
 647         struct ecore_dcbx_info          *p_dcbx_info;
 648
 649         struct ecore_dmae_info          dmae_info;
 650
 651         /* QM init */
 652         struct ecore_qm_info            qm_info;
 653
 654         /* Buffer for unzipping firmware data */
 655 #ifdef CONFIG_ECORE_ZIPPED_FW
 656         void *unzip_buf;
 657 #endif
 658
 659         struct dbg_tools_data           dbg_info;
 660
 661         /* PWM region specific data */
 662         u16                             wid_count;
 663         u32                             dpi_size;
 664         u32                             dpi_count;
 665         u32                             dpi_start_offset; /* this is used to
 666                                                            * calculate th
 667                                                            * doorbell address
 668                                                            */
 669
 670         /* If one of the following is set then EDPM shouldn't be used */
 671         u8                              dcbx_no_edpm;
 672         u8                              db_bar_no_edpm;
 673
 674         /* L2-related */
 675         struct ecore_l2_info            *p_l2_info;
 676 };
 677
 678 #ifndef __EXTRACT__LINUX__
 679 enum ecore_mf_mode {
 680         ECORE_MF_DEFAULT,
 681         ECORE_MF_OVLAN,
 682         ECORE_MF_NPAR,
 683 };
 684 #endif
 685
 686 #ifndef __EXTRACT__LINUX__
 687 enum ecore_dev_type {
 688         ECORE_DEV_TYPE_BB,
 689         ECORE_DEV_TYPE_AH,
 690         ECORE_DEV_TYPE_E5,
 691 };
 692 #endif
 693
 694 struct ecore_dev {
 695         u32                             dp_module;
 696         u8                              dp_level;
 697         char                            name[NAME_SIZE];
 698         void                            *dp_ctx;
 699
 700         enum ecore_dev_type             type;
 701 /* Translate type/revision combo into the proper conditions */
 702 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 703 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 704 #ifndef ASIC_ONLY
 705 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 706                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 707 #else
 708 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 709 #endif
 710 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 711 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 712
 713 #define ECORE_IS_E5(dev)        false
 714
 715 #define ECORE_E5_MISSING_CODE   OSAL_BUILD_BUG_ON(false)
 716
 717         u16 vendor_id;
 718         u16 device_id;
 719 #define ECORE_DEV_ID_MASK       0xff00
 720 #define ECORE_DEV_ID_MASK_BB    0x1600
 721 #define ECORE_DEV_ID_MASK_AH    0x8000
 722
 723         u16                             chip_num;
 724         #define CHIP_NUM_MASK                   0xffff
 725         #define CHIP_NUM_SHIFT                  16
 726
 727         u16                             chip_rev;
 728         #define CHIP_REV_MASK                   0xf
 729         #define CHIP_REV_SHIFT                  12
 730 #ifndef ASIC_ONLY
 731         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 732         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 733         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 734         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 735                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 736         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 737         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 738         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 739                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 740         #define CHIP_REV_IS_SLOW(_p_dev) \
 741                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 742         #define CHIP_REV_IS_A0(_p_dev) \
 743                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 744                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 745                  !(_p_dev)->chip_rev)
 746         #define CHIP_REV_IS_B0(_p_dev) \
 747                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 748                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 749                  (_p_dev)->chip_rev == 1)
 750         #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
 751 #else
 752         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 753         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 754 #endif
 755
 756         u16                             chip_metal;
 757         #define CHIP_METAL_MASK                 0xff
 758         #define CHIP_METAL_SHIFT                4
 759
 760         u16                             chip_bond_id;
 761         #define CHIP_BOND_ID_MASK               0xf
 762         #define CHIP_BOND_ID_SHIFT              0
 763
 764         u8                              num_engines;
 765         u8                              num_ports_in_engine;
 766         u8                              num_funcs_in_port;
 767
 768         u8                              path_id;
 769         enum ecore_mf_mode              mf_mode;
 770         #define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 771         #define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 772         #define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 773
 774         int                             pcie_width;
 775         int                             pcie_speed;
 776
 777         /* Add MF related configuration */
 778         u8                              mcp_rev;
 779         u8                              boot_mode;
 780
 781         /* WoL related configurations */
 782         u8                              wol_config;
 783         u8                              wol_mac[ETH_ALEN];
 784
 785         u32                             int_mode;
 786         enum ecore_coalescing_mode      int_coalescing_mode;
 787         u16                             rx_coalesce_usecs;
 788         u16                             tx_coalesce_usecs;
 789
 790         /* Start Bar offset of first hwfn */
 791         void OSAL_IOMEM                 *regview;
 792         void OSAL_IOMEM                 *doorbells;
 793         u64                             db_phys_addr;
 794         unsigned long                   db_size;
 795
 796         /* PCI */
 797         u8                              cache_shift;
 798
 799         /* Init */
 800         const struct iro                *iro_arr;
 801         #define IRO (p_hwfn->p_dev->iro_arr)
 802
 803         /* HW functions */
 804         u8                              num_hwfns;
 805         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 806
 807         /* SRIOV */
 808         struct ecore_hw_sriov_info      *p_iov_info;
 809 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 810 #ifdef CONFIG_ECORE_SW_CHANNEL
 811         bool                            b_hw_channel;
 812 #endif
 813         struct ecore_tunnel_info        tunnel;
 814         bool                            b_is_vf;
 815         bool                            b_dont_override_vf_msix;
 816
 817         u32                             drv_type;
 818
 819         u32                             rdma_max_sge;
 820         u32                             rdma_max_inline;
 821         u32                             rdma_max_srq_sge;
 822
 823         struct ecore_eth_stats          *reset_stats;
 824         struct ecore_fw_data            *fw_data;
 825
 826         u32                             mcp_nvm_resp;
 827
 828         /* Recovery */
 829         bool                            recov_in_prog;
 830
 831         /* Indicates whether should prevent attentions from being reasserted */
 832         bool                            attn_clr_en;
 833
 834         /* Indicates whether allowing the MFW to collect a crash dump */
 835         bool                            allow_mdump;
 836
 837         /* Indicates if the reg_fifo is checked after any register access */
 838         bool                            chk_reg_fifo;
 839
 840 #ifndef ASIC_ONLY
 841         bool                            b_is_emul_full;
 842 #endif
 843 };
 844
 845 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 846                                                   : MAX_NUM_VFS_K2)
 847 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 848                                                   : MAX_NUM_L2_QUEUES_K2)
 849 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 850                                                   : MAX_NUM_PORTS_K2)
 851 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 852                                                   : MAX_SB_PER_PATH_K2)
 853 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 854                                                   : MAX_NUM_PFS_K2)
 855 /**
 856  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 857  *        the concrete value.
 858  *
 859  * @param concrete_fid
 860  *
 861  * @return OSAL_INLINE u8
 862  */
 863 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
 864                                           u32 concrete_fid)
 865 {
 866         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 867         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 868         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 869         u8 sw_fid;
 870
 871         if (vf_valid)
 872                 sw_fid = vfid + MAX_NUM_PFS;
 873         else
 874                 sw_fid = pfid;
 875
 876         return sw_fid;
 877 }
 878
 879 #define PURE_LB_TC 8
 880 #define PKT_LB_TC 9
 881
 882 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 883 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 884                                            struct ecore_ptt *p_ptt,
 885                                            u32 min_pf_rate);
 886
 887 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 888 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 889 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 890 int ecore_device_num_engines(struct ecore_dev *p_dev);
 891 int ecore_device_num_ports(struct ecore_dev *p_dev);
 892 int ecore_device_get_port_id(struct ecore_dev *p_dev);
 893 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 894                            u8 *mac);
 895
 896 /* Flags for indication of required queues */
 897 #define PQ_FLAGS_RLS    (1 << 0)
 898 #define PQ_FLAGS_MCOS   (1 << 1)
 899 #define PQ_FLAGS_LB     (1 << 2)
 900 #define PQ_FLAGS_OOO    (1 << 3)
 901 #define PQ_FLAGS_ACK    (1 << 4)
 902 #define PQ_FLAGS_OFLD   (1 << 5)
 903 #define PQ_FLAGS_VFS    (1 << 6)
 904 #define PQ_FLAGS_LLT    (1 << 7)
 905
 906 /* physical queue index for cm context intialization */
 907 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 908 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 909 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 910 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 911
 912 /* amount of resources used in qm init */
 913 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 914 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 915 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 916 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 917 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 918
 919 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 920
 921 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
 922
 923 #endif /* __ECORE_H */