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Unleashed v1.4
[unleashed.git] / usr / src / uts / common / io / qede / 579xx / drivers / ecore / ecore.h
bloba8e3034a58fe9ef30d8f306e3a11180d31a5c372
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1, (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1, (the "License").
26
27 * You may not use this file except in compliance with the License.
28
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35
36 #ifndef __ECORE_H
37 #define __ECORE_H
38
39 #include "ecore_hsi_common.h"
40 #include "ecore_hsi_debug_tools.h"
41 #include "ecore_hsi_init_func.h"
42 #include "ecore_hsi_init_tool.h"
43 #include "ecore_proto_if.h"
44 #include "mcp_public.h"
45
46 #define ECORE_MAJOR_VERSION 8
47 #define ECORE_MINOR_VERSION 18
48 #define ECORE_REVISION_VERSION 18
49 #define ECORE_ENGINEERING_VERSION 0
50
51 #define ECORE_VERSION \
52 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
53 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
54
55 #define STORM_FW_VERSION \
56 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
57 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
58
59 #define MAX_HWFNS_PER_DEVICE 2
60 #define NAME_SIZE 16
61 #define ARRAY_DECL static const
62 #define ECORE_WFQ_UNIT 100
63
64 /* Constants */
65 #define ECORE_WID_SIZE (1024)
66
67 /* Configurable */
68 #define ECORE_PF_DEMS_SIZE (4)
69
70 /* cau states */
71 enum ecore_coalescing_mode {
72 ECORE_COAL_MODE_DISABLE,
73 ECORE_COAL_MODE_ENABLE
74 };
75
76 enum ecore_nvm_cmd {
77 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
78 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
79 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
80 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
81 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
82 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
83 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
84 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
85 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
86 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
87 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
88 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
89 };
90
91 #ifndef LINUX_REMOVE
92 #if !defined(CONFIG_ECORE_L2) && !defined(CONFIG_ECORE_ROCE) && \
93 !defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI)
94 #define CONFIG_ECORE_L2
95 #define CONFIG_ECORE_SRIOV
96 #define CONFIG_ECORE_ROCE
97 #define CONFIG_ECORE_IWARP
98 #define CONFIG_ECORE_FCOE
99 #define CONFIG_ECORE_ISCSI
100 #define CONFIG_ECORE_LL2
101 #endif
102 #endif
103
104 /* helpers */
105 #ifndef __EXTRACT__LINUX__
106 #define MASK_FIELD(_name, _value) \
107 ((_value) &= (_name##_MASK))
108
109 #define FIELD_VALUE(_name, _value) \
110 ((_value & _name##_MASK) << _name##_SHIFT)
111
112 #define SET_FIELD(value, name, flag) \
113 do { \
114 (value) &= ~((u64)name##_MASK << (u64)name##_SHIFT); \
115 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
116 } while (0)
117
118 #define GET_FIELD(value, name) \
119 (((value) >> (name##_SHIFT)) & name##_MASK)
120 #endif
121
122 #define ECORE_MFW_GET_FIELD(name, field) \
123 (((name) & (field ## _MASK)) >> (field ## _SHIFT))
124
125 #define ECORE_MFW_SET_FIELD(name, field, value) \
126 do { \
127 (name) &= ~(((u64)field ## _MASK) << ((u64)field ## _SHIFT)); \
128 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK)); \
129 } while (0)
130
131
132 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
133 {
134 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
135 (cid * ECORE_PF_DEMS_SIZE);
136
137 return db_addr;
138 }
139
140 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
141 {
142 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
143 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
144
145 return db_addr;
146 }
147
148 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
149 ((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \
150 ~((1<<(p_hwfn->p_dev->cache_shift))-1))
151
152 #ifndef LINUX_REMOVE
153 #ifndef U64_HI
154 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
155 #endif
156
157 #ifndef U64_LO
158 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
159 #endif
160 #endif
161
162 #ifndef __EXTRACT__LINUX__
163 #ifndef UEFI
164 /* Debug print definitions */
165 #define DP_ERR(p_dev, fmt, ...) \
166 do { \
167 PRINT_ERR((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
168 __func__, __LINE__, \
169 (p_dev)->name ? (p_dev)->name : "", \
170 ##__VA_ARGS__); \
171 } while (0)
172
173 #define DP_NOTICE(p_dev, is_assert, fmt, ...) \
174 do { \
175 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_NOTICE)) { \
176 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
177 __func__, __LINE__, \
178 (p_dev)->name ? (p_dev)->name : "", \
179 ##__VA_ARGS__); \
180 OSAL_ASSERT(!is_assert); \
181 } \
182 } while (0)
183
184 #define DP_INFO(p_dev, fmt, ...) \
185 do { \
186 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_INFO)) { \
187 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
188 __func__, __LINE__, \
189 (p_dev)->name ? (p_dev)->name : "", \
190 ##__VA_ARGS__); \
191 } \
192 } while (0)
193
194 #define DP_VERBOSE(p_dev, module, fmt, ...) \
195 do { \
196 if (OSAL_UNLIKELY(((p_dev)->dp_level <= ECORE_LEVEL_VERBOSE) && \
197 ((p_dev)->dp_module & module))) { \
198 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
199 __func__, __LINE__, \
200 (p_dev)->name ? (p_dev)->name : "", \
201 ##__VA_ARGS__); \
202 } \
203 } while (0)
204 #endif
205
206 enum DP_LEVEL {
207 ECORE_LEVEL_VERBOSE = 0x0,
208 ECORE_LEVEL_INFO = 0x1,
209 ECORE_LEVEL_NOTICE = 0x2,
210 ECORE_LEVEL_ERR = 0x3,
211 };
212
213 #define ECORE_LOG_LEVEL_SHIFT (30)
214 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
215 #define ECORE_LOG_INFO_MASK (0x40000000)
216 #define ECORE_LOG_NOTICE_MASK (0x80000000)
217
218 enum DP_MODULE {
219 #ifndef LINUX_REMOVE
220 ECORE_MSG_DRV = 0x0001,
221 ECORE_MSG_PROBE = 0x0002,
222 ECORE_MSG_LINK = 0x0004,
223 ECORE_MSG_TIMER = 0x0008,
224 ECORE_MSG_IFDOWN = 0x0010,
225 ECORE_MSG_IFUP = 0x0020,
226 ECORE_MSG_RX_ERR = 0x0040,
227 ECORE_MSG_TX_ERR = 0x0080,
228 ECORE_MSG_TX_QUEUED = 0x0100,
229 ECORE_MSG_INTR = 0x0200,
230 ECORE_MSG_TX_DONE = 0x0400,
231 ECORE_MSG_RX_STATUS = 0x0800,
232 ECORE_MSG_PKTDATA = 0x1000,
233 ECORE_MSG_HW = 0x2000,
234 ECORE_MSG_WOL = 0x4000,
235 #endif
236 ECORE_MSG_SPQ = 0x10000,
237 ECORE_MSG_STATS = 0x20000,
238 ECORE_MSG_DCB = 0x40000,
239 ECORE_MSG_IOV = 0x80000,
240 ECORE_MSG_SP = 0x100000,
241 ECORE_MSG_STORAGE = 0x200000,
242 ECORE_MSG_OOO = 0x200000,
243 ECORE_MSG_CXT = 0x800000,
244 ECORE_MSG_LL2 = 0x1000000,
245 ECORE_MSG_ILT = 0x2000000,
246 ECORE_MSG_RDMA = 0x4000000,
247 ECORE_MSG_DEBUG = 0x8000000,
248 /* to be added...up to 0x8000000 */
249 };
250 #endif
251
252 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
253
254 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
255 (val == (cond1) ? true1 : \
256 (val == (cond2) ? true2 : def))
257
258 /* forward */
259 struct ecore_ptt_pool;
260 struct ecore_spq;
261 struct ecore_sb_info;
262 struct ecore_sb_attn_info;
263 struct ecore_cxt_mngr;
264 struct ecore_dma_mem;
265 struct ecore_sb_sp_info;
266 struct ecore_ll2_info;
267 struct ecore_l2_info;
268 struct ecore_igu_info;
269 struct ecore_mcp_info;
270 struct ecore_dcbx_info;
271
272 struct ecore_rt_data {
273 u32 *init_val;
274 bool *b_valid;
275 };
276
277 enum ecore_tunn_mode {
278 ECORE_MODE_L2GENEVE_TUNN,
279 ECORE_MODE_IPGENEVE_TUNN,
280 ECORE_MODE_L2GRE_TUNN,
281 ECORE_MODE_IPGRE_TUNN,
282 ECORE_MODE_VXLAN_TUNN,
283 };
284
285 enum ecore_tunn_clss {
286 ECORE_TUNN_CLSS_MAC_VLAN,
287 ECORE_TUNN_CLSS_MAC_VNI,
288 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
289 ECORE_TUNN_CLSS_INNER_MAC_VNI,
290 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
291 MAX_ECORE_TUNN_CLSS,
292 };
293
294 struct ecore_tunn_update_type {
295 bool b_update_mode;
296 bool b_mode_enabled;
297 enum ecore_tunn_clss tun_cls;
298 };
299
300 struct ecore_tunn_update_udp_port {
301 bool b_update_port;
302 u16 port;
303 };
304
305 struct ecore_tunnel_info {
306 struct ecore_tunn_update_type vxlan;
307 struct ecore_tunn_update_type l2_geneve;
308 struct ecore_tunn_update_type ip_geneve;
309 struct ecore_tunn_update_type l2_gre;
310 struct ecore_tunn_update_type ip_gre;
311
312 struct ecore_tunn_update_udp_port vxlan_port;
313 struct ecore_tunn_update_udp_port geneve_port;
314
315 bool b_update_rx_cls;
316 bool b_update_tx_cls;
317 };
318
319 /* The PCI personality is not quite synonymous to protocol ID:
320 * 1. All personalities need CORE connections
321 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
322 */
323 enum ecore_pci_personality {
324 ECORE_PCI_ETH,
325 ECORE_PCI_FCOE,
326 ECORE_PCI_ISCSI,
327 ECORE_PCI_ETH_ROCE,
328 ECORE_PCI_ETH_IWARP,
329 ECORE_PCI_ETH_RDMA,
330 ECORE_PCI_DEFAULT /* default in shmem */
331 };
332
333 /* All VFs are symetric, all counters are PF + all VFs */
334 struct ecore_qm_iids {
335 u32 cids;
336 u32 vf_cids;
337 u32 tids;
338 };
339
340 #define MAX_PF_PER_PORT 8
341
342 /* HW / FW resources, output of features supported below, most information
343 * is received from MFW.
344 */
345 enum ecore_resources {
346 ECORE_L2_QUEUE,
347 ECORE_VPORT,
348 ECORE_RSS_ENG,
349 ECORE_PQ,
350 ECORE_RL,
351 ECORE_MAC,
352 ECORE_VLAN,
353 ECORE_RDMA_CNQ_RAM,
354 ECORE_ILT,
355 ECORE_LL2_QUEUE,
356 ECORE_CMDQS_CQS,
357 ECORE_RDMA_STATS_QUEUE,
358 ECORE_BDQ,
359
360 /* This is needed only internally for matching against the IGU.
361 * In case of legacy MFW, would be set to `0'.
362 */
363 ECORE_SB,
364
365 ECORE_MAX_RESC,
366 };
367
368 /* Features that require resources, given as input to the resource management
369 * algorithm, the output are the resources above
370 */
371 enum ecore_feature {
372 ECORE_PF_L2_QUE,
373 ECORE_PF_TC,
374 ECORE_VF,
375 ECORE_EXTRA_VF_QUE,
376 ECORE_VMQ,
377 ECORE_RDMA_CNQ,
378 ECORE_ISCSI_CQ,
379 ECORE_FCOE_CQ,
380 ECORE_VF_L2_QUE,
381 ECORE_MAX_FEATURES,
382 };
383
384 enum ecore_port_mode {
385 ECORE_PORT_MODE_DE_2X40G,
386 ECORE_PORT_MODE_DE_2X50G,
387 ECORE_PORT_MODE_DE_1X100G,
388 ECORE_PORT_MODE_DE_4X10G_F,
389 ECORE_PORT_MODE_DE_4X10G_E,
390 ECORE_PORT_MODE_DE_4X20G,
391 ECORE_PORT_MODE_DE_1X40G,
392 ECORE_PORT_MODE_DE_2X25G,
393 ECORE_PORT_MODE_DE_1X25G,
394 ECORE_PORT_MODE_DE_4X25G,
395 ECORE_PORT_MODE_DE_2X10G,
396 };
397
398 enum ecore_dev_cap {
399 ECORE_DEV_CAP_ETH,
400 ECORE_DEV_CAP_FCOE,
401 ECORE_DEV_CAP_ISCSI,
402 ECORE_DEV_CAP_ROCE,
403 ECORE_DEV_CAP_IWARP
404 };
405
406 #ifndef __EXTRACT__LINUX__
407 enum ecore_hw_err_type {
408 ECORE_HW_ERR_FAN_FAIL,
409 ECORE_HW_ERR_MFW_RESP_FAIL,
410 ECORE_HW_ERR_HW_ATTN,
411 ECORE_HW_ERR_DMAE_FAIL,
412 ECORE_HW_ERR_RAMROD_FAIL,
413 ECORE_HW_ERR_FW_ASSERT,
414 };
415 #endif
416
417 enum ecore_wol_support {
418 ECORE_WOL_SUPPORT_NONE,
419 ECORE_WOL_SUPPORT_PME,
420 };
421
422 struct ecore_hw_info {
423 /* PCI personality */
424 enum ecore_pci_personality personality;
425 #define ECORE_IS_RDMA_PERSONALITY(dev) \
426 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
427 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
428 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
429 #define ECORE_IS_ROCE_PERSONALITY(dev) \
430 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
431 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
432 #define ECORE_IS_IWARP_PERSONALITY(dev) \
433 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
434 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
435 #define ECORE_IS_L2_PERSONALITY(dev) \
436 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
437 ECORE_IS_RDMA_PERSONALITY(dev))
438 #define ECORE_IS_FCOE_PERSONALITY(dev) \
439 ((dev)->hw_info.personality == ECORE_PCI_FCOE)
440 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
441 ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
442
443 /* Resource Allocation scheme results */
444 u32 resc_start[ECORE_MAX_RESC];
445 u32 resc_num[ECORE_MAX_RESC];
446 u32 feat_num[ECORE_MAX_FEATURES];
447
448 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
449 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
450 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
451 RESC_NUM(_p_hwfn, resc))
452 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
453
454 /* Amount of traffic classes HW supports */
455 u8 num_hw_tc;
456
457 /* Amount of TCs which should be active according to DCBx or upper layer driver configuration */
458 u8 num_active_tc;
459
460 /* The traffic class used by PF for it's offloaded protocol */
461 u8 offload_tc;
462
463 u32 concrete_fid;
464 u16 opaque_fid;
465 u16 ovlan;
466 u32 part_num[4];
467
468 #define ETH_ALEN 6 /* @@@ TBD - define somewhere else for Windows */
469 unsigned char hw_mac_addr[ETH_ALEN];
470
471 u16 num_iscsi_conns;
472 u16 num_fcoe_conns;
473
474 struct ecore_igu_info *p_igu_info;
475 /* Sriov */
476 u8 max_chains_per_vf;
477
478 u32 port_mode;
479 u32 hw_mode;
480 unsigned long device_capabilities;
481
482 /* Default DCBX mode */
483 u8 dcbx_mode;
484
485 u16 mtu;
486
487 enum ecore_wol_support b_wol_support;
488 };
489
490 /* maximun size of read/write commands (HW limit) */
491 #define DMAE_MAX_RW_SIZE 0x2000
492
493 struct ecore_dmae_info {
494 /* Mutex for synchronizing access to functions */
495 osal_mutex_t mutex;
496
497 u8 channel;
498
499 dma_addr_t completion_word_phys_addr;
500
501 /* The memory location where the DMAE writes the completion
502 * value when an operation is finished on this context.
503 */
504 u32 *p_completion_word;
505
506 dma_addr_t intermediate_buffer_phys_addr;
507
508 /* An intermediate buffer for DMAE operations that use virtual
509 * addresses - data is DMA'd to/from this buffer and then
510 * memcpy'd to/from the virtual address
511 */
512 u32 *p_intermediate_buffer;
513
514 dma_addr_t dmae_cmd_phys_addr;
515 struct dmae_cmd *p_dmae_cmd;
516 };
517
518 struct ecore_wfq_data {
519 u32 default_min_speed; /* When wfq feature is not configured */
520 u32 min_speed; /* when feature is configured for any 1 vport */
521 bool configured;
522 };
523
524 struct ecore_qm_info {
525 struct init_qm_pq_params *qm_pq_params;
526 struct init_qm_vport_params *qm_vport_params;
527 struct init_qm_port_params *qm_port_params;
528 u16 start_pq;
529 u8 start_vport;
530 u16 pure_lb_pq;
531 u16 offload_pq;
532 u16 low_latency_pq;
533 u16 pure_ack_pq;
534 u16 ooo_pq;
535 u16 first_vf_pq;
536 u16 first_mcos_pq;
537 u16 first_rl_pq;
538 u16 num_pqs;
539 u16 num_vf_pqs;
540 u8 num_vports;
541 u8 max_phys_tcs_per_port;
542 u8 ooo_tc;
543 bool pf_rl_en;
544 bool pf_wfq_en;
545 bool vport_rl_en;
546 bool vport_wfq_en;
547 u8 pf_wfq;
548 u32 pf_rl;
549 struct ecore_wfq_data *wfq_data;
550 u8 num_pf_rls;
551 };
552
553 struct storm_stats {
554 u32 address;
555 u32 len;
556 };
557
558 struct ecore_fw_data {
559 #ifdef CONFIG_ECORE_BINARY_FW
560 struct fw_ver_info *fw_ver_info;
561 #endif
562 const u8 *modes_tree_buf;
563 union init_op *init_ops;
564 const u32 *arr_data;
565 u32 init_ops_size;
566 };
567
568 struct ecore_hwfn {
569 struct ecore_dev *p_dev;
570 u8 my_id; /* ID inside the PF */
571 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
572 u8 rel_pf_id; /* Relative to engine*/
573 u8 abs_pf_id;
574 #define ECORE_PATH_ID(_p_hwfn) \
575 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
576 u8 port_id;
577 bool b_active;
578
579 u32 dp_module;
580 u8 dp_level;
581 char name[NAME_SIZE];
582 void *dp_ctx;
583
584 bool first_on_engine;
585 bool hw_init_done;
586
587 u8 num_funcs_on_engine;
588 u8 enabled_func_idx;
589
590 /* BAR access */
591 void OSAL_IOMEM *regview;
592 void OSAL_IOMEM *doorbells;
593 u64 db_phys_addr;
594 unsigned long db_size;
595
596 /* PTT pool */
597 struct ecore_ptt_pool *p_ptt_pool;
598
599 /* HW info */
600 struct ecore_hw_info hw_info;
601
602 /* rt_array (for init-tool) */
603 struct ecore_rt_data rt_data;
604
605 /* SPQ */
606 struct ecore_spq *p_spq;
607
608 /* EQ */
609 struct ecore_eq *p_eq;
610
611 /* Consolidate Q*/
612 struct ecore_consq *p_consq;
613
614 /* Slow-Path definitions */
615 osal_dpc_t sp_dpc;
616 bool b_sp_dpc_enabled;
617
618 struct ecore_ptt *p_main_ptt;
619 struct ecore_ptt *p_dpc_ptt;
620
621 struct ecore_sb_sp_info *p_sp_sb;
622 struct ecore_sb_attn_info *p_sb_attn;
623
624 /* Protocol related */
625 bool using_ll2;
626 struct ecore_ll2_info *p_ll2_info;
627 struct ecore_ooo_info *p_ooo_info;
628 struct ecore_iscsi_info *p_iscsi_info;
629 struct ecore_fcoe_info *p_fcoe_info;
630 struct ecore_rdma_info *p_rdma_info;
631 struct ecore_pf_params pf_params;
632
633 bool b_rdma_enabled_in_prs;
634 u32 rdma_prs_search_reg;
635
636 struct ecore_cxt_mngr *p_cxt_mngr;
637
638 /* Flag indicating whether interrupts are enabled or not*/
639 bool b_int_enabled;
640 bool b_int_requested;
641
642 /* True if the driver requests for the link */
643 bool b_drv_link_init;
644
645 struct ecore_vf_iov *vf_iov_info;
646 struct ecore_pf_iov *pf_iov_info;
647 struct ecore_mcp_info *mcp_info;
648 struct ecore_dcbx_info *p_dcbx_info;
649
650 struct ecore_dmae_info dmae_info;
651
652 /* QM init */
653 struct ecore_qm_info qm_info;
654
655 /* Buffer for unzipping firmware data */
656 #ifdef CONFIG_ECORE_ZIPPED_FW
657 void *unzip_buf;
658 #endif
659
660 struct dbg_tools_data dbg_info;
661
662 /* PWM region specific data */
663 u16 wid_count;
664 u32 dpi_size;
665 u32 dpi_count;
666 u32 dpi_start_offset; /* this is used to
667 * calculate th
668 * doorbell address
669 */
670
671 /* If one of the following is set then EDPM shouldn't be used */
672 u8 dcbx_no_edpm;
673 u8 db_bar_no_edpm;
674
675 /* L2-related */
676 struct ecore_l2_info *p_l2_info;
677 };
678
679 #ifndef __EXTRACT__LINUX__
680 enum ecore_mf_mode {
681 ECORE_MF_DEFAULT,
682 ECORE_MF_OVLAN,
683 ECORE_MF_NPAR,
684 };
685 #endif
686
687 #ifndef __EXTRACT__LINUX__
688 enum ecore_dev_type {
689 ECORE_DEV_TYPE_BB,
690 ECORE_DEV_TYPE_AH,
691 ECORE_DEV_TYPE_E5,
692 };
693 #endif
694
695 struct ecore_dev {
696 u32 dp_module;
697 u8 dp_level;
698 char name[NAME_SIZE];
699 void *dp_ctx;
700
701 enum ecore_dev_type type;
702 /* Translate type/revision combo into the proper conditions */
703 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
704 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
705 #ifndef ASIC_ONLY
706 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
707 (CHIP_REV_IS_TEDIBEAR(dev)))
708 #else
709 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
710 #endif
711 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
712 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
713
714 #define ECORE_IS_E5(dev) false
715
716 #define ECORE_E5_MISSING_CODE OSAL_BUILD_BUG_ON(false)
717
718 u16 vendor_id;
719 u16 device_id;
720 #define ECORE_DEV_ID_MASK 0xff00
721 #define ECORE_DEV_ID_MASK_BB 0x1600
722 #define ECORE_DEV_ID_MASK_AH 0x8000
723
724 u16 chip_num;
725 #define CHIP_NUM_MASK 0xffff
726 #define CHIP_NUM_SHIFT 16
727
728 u16 chip_rev;
729 #define CHIP_REV_MASK 0xf
730 #define CHIP_REV_SHIFT 12
731 #ifndef ASIC_ONLY
732 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
733 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
734 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
735 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
736 CHIP_REV_IS_EMUL_B0(_p_dev))
737 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
738 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
739 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
740 CHIP_REV_IS_FPGA_B0(_p_dev))
741 #define CHIP_REV_IS_SLOW(_p_dev) \
742 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
743 #define CHIP_REV_IS_A0(_p_dev) \
744 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
745 CHIP_REV_IS_FPGA_A0(_p_dev) || \
746 !(_p_dev)->chip_rev)
747 #define CHIP_REV_IS_B0(_p_dev) \
748 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
749 CHIP_REV_IS_FPGA_B0(_p_dev) || \
750 (_p_dev)->chip_rev == 1)
751 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
752 #else
753 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
754 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
755 #endif
756
757 u16 chip_metal;
758 #define CHIP_METAL_MASK 0xff
759 #define CHIP_METAL_SHIFT 4
760
761 u16 chip_bond_id;
762 #define CHIP_BOND_ID_MASK 0xf
763 #define CHIP_BOND_ID_SHIFT 0
764
765 u8 num_engines;
766 u8 num_ports_in_engine;
767 u8 num_funcs_in_port;
768
769 u8 path_id;
770 enum ecore_mf_mode mf_mode;
771 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
772 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
773 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
774
775 int pcie_width;
776 int pcie_speed;
777
778 /* Add MF related configuration */
779 u8 mcp_rev;
780 u8 boot_mode;
781
782 /* WoL related configurations */
783 u8 wol_config;
784 u8 wol_mac[ETH_ALEN];
785
786 u32 int_mode;
787 enum ecore_coalescing_mode int_coalescing_mode;
788 u16 rx_coalesce_usecs;
789 u16 tx_coalesce_usecs;
790
791 /* Start Bar offset of first hwfn */
792 void OSAL_IOMEM *regview;
793 void OSAL_IOMEM *doorbells;
794 u64 db_phys_addr;
795 unsigned long db_size;
796
797 /* PCI */
798 u8 cache_shift;
799
800 /* Init */
801 const struct iro *iro_arr;
802 #define IRO (p_hwfn->p_dev->iro_arr)
803
804 /* HW functions */
805 u8 num_hwfns;
806 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
807
808 /* SRIOV */
809 struct ecore_hw_sriov_info *p_iov_info;
810 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
811 #ifdef CONFIG_ECORE_SW_CHANNEL
812 bool b_hw_channel;
813 #endif
814 struct ecore_tunnel_info tunnel;
815 bool b_is_vf;
816 bool b_dont_override_vf_msix;
817
818 u32 drv_type;
819
820 u32 rdma_max_sge;
821 u32 rdma_max_inline;
822 u32 rdma_max_srq_sge;
823
824 struct ecore_eth_stats *reset_stats;
825 struct ecore_fw_data *fw_data;
826
827 u32 mcp_nvm_resp;
828
829 /* Recovery */
830 bool recov_in_prog;
831
832 /* Indicates whether should prevent attentions from being reasserted */
833 bool attn_clr_en;
834
835 /* Indicates whether allowing the MFW to collect a crash dump */
836 bool allow_mdump;
837
838 /* Indicates if the reg_fifo is checked after any register access */
839 bool chk_reg_fifo;
840
841 #ifndef ASIC_ONLY
842 bool b_is_emul_full;
843 #endif
844 };
845
846 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
847 : MAX_NUM_VFS_K2)
848 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
849 : MAX_NUM_L2_QUEUES_K2)
850 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
851 : MAX_NUM_PORTS_K2)
852 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
853 : MAX_SB_PER_PATH_K2)
854 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
855 : MAX_NUM_PFS_K2)
856 /**
857 * @brief ecore_concrete_to_sw_fid - get the sw function id from
858 * the concrete value.
859 *
860 * @param concrete_fid
861 *
862 * @return OSAL_INLINE u8
863 */
864 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
865 u32 concrete_fid)
866 {
867 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
868 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
869 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
870 u8 sw_fid;
871
872 if (vf_valid)
873 sw_fid = vfid + MAX_NUM_PFS;
874 else
875 sw_fid = pfid;
876
877 return sw_fid;
878 }
879
880 #define PURE_LB_TC 8
881 #define PKT_LB_TC 9
882
883 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
884 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
885 struct ecore_ptt *p_ptt,
886 u32 min_pf_rate);
887
888 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
889 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
890 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
891 int ecore_device_num_engines(struct ecore_dev *p_dev);
892 int ecore_device_num_ports(struct ecore_dev *p_dev);
893 int ecore_device_get_port_id(struct ecore_dev *p_dev);
894 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
895 u8 *mac);
896
897 /* Flags for indication of required queues */
898 #define PQ_FLAGS_RLS (1 << 0)
899 #define PQ_FLAGS_MCOS (1 << 1)
900 #define PQ_FLAGS_LB (1 << 2)
901 #define PQ_FLAGS_OOO (1 << 3)
902 #define PQ_FLAGS_ACK (1 << 4)
903 #define PQ_FLAGS_OFLD (1 << 5)
904 #define PQ_FLAGS_VFS (1 << 6)
905 #define PQ_FLAGS_LLT (1 << 7)
906
907 /* physical queue index for cm context intialization */
908 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
909 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
910 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
911 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
912
913 /* amount of resources used in qm init */
914 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
915 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
916 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
917 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
918 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
919
920 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
921
922 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
923
924 #endif /* __ECORE_H */
Unleashed OS